GitLab

modules.

elements.

Resolve "Extend pyxact generator with VHDL access generation"

Closes #109

See merge request illeondr/CAN_FD_IP_Core!173

CAN FD Registers.

Register map was renamed in IP-XACT, thus the re-generation.
Maybe a little long, but it looks better in IP-XACT. Otherwise
mem map name was just "Regs" which was not what one was seeing
in documentation...

Set reg.map files to VHDL 2008 due to usage
of data_width generic in the same interface list.

ugly but works. I merged some stuff which was not working
to master...

Removed pyXact generator tracked files.

Closes #209

See merge request illeondr/CAN_FD_IP_Core!172

Data brief v 2.1

See merge request illeondr/CAN_FD_IP_Core!171

to determine resource usage for Release v2.1

bus driver.

decoder.