- 11 Jan, 2020 1 commit
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Ille, Ondrej, Ing. authored
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- 08 Jan, 2020 3 commits
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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- 03 Jan, 2020 6 commits
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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- 02 Jan, 2020 2 commits
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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- 27 Dec, 2019 2 commits
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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- 23 Dec, 2019 2 commits
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Ille, Ondrej, Ing. authored
On high data bit-rates this is needed!
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Ille, Ondrej, Ing. authored
If error is forced on 5th bit of error delimiter, this will be already after error frame of the other node, so next error frame will hit Error delimiter of the other node. Due to this, the other node will transmit next error frame and thus after bus is idle, REC will be incremented twice. This is not a bug, but check of REC must be done directly after error is sampled!
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- 21 Dec, 2019 1 commit
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Ille, Ondrej, Ing. authored
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- 20 Dec, 2019 15 commits
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
Keep bit 31 of generated TS equal to 0. This is to avoid overflow on numeric conversion of 31 bit unsigned vector to natural.
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
Here after ACK we can be in EOF if sent frame is FD frame!
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
This is needed since we hardcode the ID in first bits. Extended ID is needed so that we don't overflow base ID limit!
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Ille, Ondrej, Ing. authored
This is needed since default delay can be too high for some bit-rates! Units will not manage to received ACK in time!
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
Each error now kills the test by "error" log!
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Ing. Viktor Fúra authored
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- 06 Dec, 2019 8 commits
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
Avoid using delays multiple of 10 ns. Since we use ceil in the TC, we rely on the fact that ceil will give us one cycle more from input delay! If we have multiple of 10 ns, then delta cycle behavior might cause issues.
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Ille, Ondrej, Ing. authored
RWCNT needs to be modified accordingly, so that TX/RX frame comparison is not confused!
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Ille, Ondrej, Ing. authored
Check must be done immediately, otherwise another error frame might screw REC value and it can be off by 8!
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Ille, Ondrej, Ing. authored
We must wait till bus is idle in both nodes since nodes since TX/RX trigger are validated at different times! If we wait only until frame is sent/ we end up out of sync and one step back on frame that is being sent!
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
RTR must not be present! Also RWCNT must be recalculated accordingly!
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Ille, Ondrej, Ing. authored
Node 2 RX Trigger might come later due to different clocks! We should wait properly till its sample point to be sure that we don't check arbitration lost too soon!
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