- 21 Sep, 2018 2 commits
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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- 20 Sep, 2018 1 commit
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Ille, Ondrej, Ing. authored
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- 11 Sep, 2018 12 commits
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
not number of total transmissions.
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
and set to 0. This caused that first error went to "Failed" instead of "Aborted" from "Abort in Progress". Signed-off-by:
Ille, Ondrej, Ing <illeondr@fel.cvut.cz>
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
upon sucessfull transmission from Abort in progress... Signed-off-by:
Ille, Ondrej, Ing <illeondr@fel.cvut.cz>
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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- 09 Sep, 2018 1 commit
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Ille, Ondrej, Ing. authored
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- 07 Sep, 2018 1 commit
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Ille, Ondrej, Ing. authored
case stuff. Added wait period in the beginning to make sure unit is not integrating anymore!
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- 05 Sep, 2018 8 commits
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Ille, Ondrej, Ing. authored
of inconsistency in the design. If async change occured during this time, then old priorities were used instead of new ones!
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
Allowed one clock cycle mismatch. On more than one clock cycle, error is reported.
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- 03 Sep, 2018 9 commits
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Ille, Ondrej, Ing. authored
for 3, we wont start the transmission right after the Intermission by Node 2, because the frame will be inserted after sample point, and thus Node 2 will send it after 1 bit of being Idle.
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Ille, Ondrej, Ing. authored
CAN FD Standard sets the counter to value between 119 and 127 ich frame is successfully transmitted in error passive!!!
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
after 8 hours of reading documentation on ASIC design flow!!!
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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- 02 Sep, 2018 6 commits
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
measures if length of Suspend field are proper 8 bits. Signed-off-by:
Ille, Ondrej, Ing <illeondr@fel.cvut.cz>
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Ille, Ondrej, Ing. authored
integration finish during bus-start test.
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
Adding 1 is not handled properly and due to that feature test always finds out one iteration later!
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