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EDL/r0 EDl/r1 bits detecting recessive bits are better to mark
this as form error (not bit error) even when FD format is turned
on!

Bit-error in IDE field must be detected always, it is impossible
for it to happend only when "ide_is_arbitration" is true!

On high data bit-rates this is needed!

If error is forced on 5th bit of error delimiter, this will be already
after error frame of the other node, so next error frame will hit Error
delimiter of the other node. Due to this, the other node will transmit
next error frame and thus after bus is idle, REC will be incremented
twice. This is not a bug, but check of REC must be done directly after
error is sampled!

Keep bit 31 of generated TS equal to 0. This is to avoid
overflow on numeric conversion of 31 bit unsigned vector
to natural.

Here after ACK we can be in EOF if sent frame is FD frame!

Now TEC/REC should be incremented by 8 after 14 dominant bits
long error flag and by 8 after each next 8 bits!

When we don't transmitt anything, keep IDE in Arbitration field,
not in Control field! This is better because we won't receive
short is_control pulse for the duration of IDE bit!! We don't mind
that in case of Error, this will be always interpreted as error in
Arbitration field even if BASE frame is being received!

This is needed since we hardcode the ID in first bits. Extended
ID is needed so that we don't overflow base ID limit!

when node is in Overload frame.

When in overload frame, TXT Buffer should have been long unlocked!

If bit error occurs in last bit of Error flag, then Error frame
request, due to Pipeline DFF will occur at first cycle of Error delimiter!
Thus we can't check for it so heavily...

This is needed since default delay can be too high for some
bit-rates! Units will not manage to received ACK in time!

Each error now kills the test by "error" log!