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driver: add measurement of write access time to userspace test application.

See merge request !198

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>

update links to new repository

See merge request !197

ci: do not include huge binaries in artifacts

See merge request illeondr/CAN_FD_IP_Core!196

Resolve "Align TIMESTAMP to 64 bit Address"

Closes #241

See merge request illeondr/CAN_FD_IP_Core!195

Added special treatment for kernel license formatting.
Added Kernel license flag option.

Driver formating

See merge request illeondr/CAN_FD_IP_Core!194

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>

Merge interfacing CAN FD core to PCI Express bus

Closes #216

See merge request illeondr/CAN_FD_IP_Core!179

Driver has been successfully on PCI Devboards Gmb DB4CGX15 card and on Zynq to check that it is correct.

Older (stable) version of CAN CTU FD core has been used for testing.

924e6a00 on Zynq.

7db6025a on DB4CGX15.

Implements #216 (Interfacing CAN FD core to PCI Express bus)

Signed-off-by: Pavel Pisa pisa@cmp.felk.cvut.cz

doc: Avalon/APB typo fix.

Closes #235

See merge request illeondr/CAN_FD_IP_Core!193

Resolve "Regmap gen saturation fix."

Closes #239

See merge request illeondr/CAN_FD_IP_Core!192

Resolve "Accustomize reg.map gen"

Closes #238

See merge request illeondr/CAN_FD_IP_Core!191

Removed scripts introduced by Pavel Pisa as VHDL 2008 workaround for
register map generator.
Template was updated and pushed to origin of Reg.map.gen. Map re-generated
and no change occured (expected).
Randomization of Python dictionaries reported by Pavel Pisa did not
have an impact on generated register map order.
It is to be discussed why.

Resolve "Update Quartus CTU CAN FD core benchmark project."

Closes #237

See merge request illeondr/CAN_FD_IP_Core!190

Closes 237.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>

There are options to disable use of MSI interrupt
and to disable the second core.

When the second core is disable and region is already
mapped by userspace tool then kernel-mode driver can be
tested against core controller by userspace test program.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>

The PCI express card can implement multiple CTU CAN FD
cores which share same PCI device and BAR.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>

It can only simplify generated code because GCC is sure
that it can replace whole register content.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>

Resolve "vivado component: update to match bus_sampling changes."

Closes #236

See merge request illeondr/CAN_FD_IP_Core!189

Closed 236
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>

Added files

  bus_sampling/data_edge_detector.vhd
  spirit:name>bus_sampling/trv_delay_meas.vhd
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>

Resolve VHDL 2008 is not supported in Vivado IP packager still .

Closes #226

See merge request illeondr/CAN_FD_IP_Core!188

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>

This solution is compromise with minimal/no intrusive changes
to pyXact_generator. When file pyXact_generator/templates/memory_reg.vhd
changes a little in mainline then there is chance that patch
succeed. If change more then script fails and manual intervention
is necessary.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>

Fixes Quartus error

  "generic data_width cannot be used in its own interface list"

The function is added which check ascending or descending
direction of index range for data_mask, reset_value and auto_clear
generics and process indexing appropriately.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>

SRC REGISTERS Fixed reset. Fixed reset of memory registers module. Soft reset by MODE[RST] should also reset content of memory register. Added driver of res_out to also reset generated register components.