- 13 Jan, 2019 2 commits
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Pavel Pisa authored
driver: add measurement of write access time to userspace test application. See merge request !198
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Pavel Pisa authored
Signed-off-by:
Pavel Pisa <pisa@cmp.felk.cvut.cz>
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- 10 Jan, 2019 14 commits
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Martin Jeřábek authored
update links to new repository See merge request !197
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Martin Jeřábek authored
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Martin Jeřábek authored
ci: do not include huge binaries in artifacts See merge request illeondr/CAN_FD_IP_Core!196
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Martin Jeřábek authored
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Ille, Ondrej, Ing. authored
Resolve "Align TIMESTAMP to 64 bit Address" Closes #241 See merge request illeondr/CAN_FD_IP_Core!195
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
Added special treatment for kernel license formatting. Added Kernel license flag option.
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Pavel Pisa authored
Driver formating See merge request illeondr/CAN_FD_IP_Core!194
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Pavel Pisa authored
Signed-off-by:
Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Pavel Pisa authored
Signed-off-by:
Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Pavel Pisa authored
Merge interfacing CAN FD core to PCI Express bus Closes #216 See merge request illeondr/CAN_FD_IP_Core!179
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Pavel Pisa authored
Driver has been successfully on PCI Devboards Gmb DB4CGX15 card and on Zynq to check that it is correct. Older (stable) version of CAN CTU FD core has been used for testing. 924e6a00 on Zynq. 7db6025a on DB4CGX15. Implements #216 (Interfacing CAN FD core to PCI Express bus) Signed-off-by: Pavel Pisa pisa@cmp.felk.cvut.cz
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- 09 Jan, 2019 2 commits
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Ille, Ondrej, Ing. authored
doc: Avalon/APB typo fix. Closes #235 See merge request illeondr/CAN_FD_IP_Core!193
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Ille, Ondrej, Ing. authored
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- 08 Jan, 2019 6 commits
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Ille, Ondrej, Ing. authored
Resolve "Regmap gen saturation fix." Closes #239 See merge request illeondr/CAN_FD_IP_Core!192
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
Resolve "Accustomize reg.map gen" Closes #238 See merge request illeondr/CAN_FD_IP_Core!191
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Ille, Ondrej, Ing. authored
Removed scripts introduced by Pavel Pisa as VHDL 2008 workaround for register map generator. Template was updated and pushed to origin of Reg.map.gen. Map re-generated and no change occured (expected). Randomization of Python dictionaries reported by Pavel Pisa did not have an impact on generated register map order. It is to be discussed why.
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Ille, Ondrej, Ing. authored
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- 07 Jan, 2019 11 commits
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Pavel Pisa authored
Resolve "Update Quartus CTU CAN FD core benchmark project." Closes #237 See merge request illeondr/CAN_FD_IP_Core!190
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Pavel Pisa authored
Closes 237. Signed-off-by:
Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Pavel Pisa authored
Signed-off-by:
Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Pavel Pisa authored
There are options to disable use of MSI interrupt and to disable the second core. When the second core is disable and region is already mapped by userspace tool then kernel-mode driver can be tested against core controller by userspace test program. Signed-off-by:
Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Pavel Pisa authored
The PCI express card can implement multiple CTU CAN FD cores which share same PCI device and BAR. Signed-off-by:
Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Pavel Pisa authored
Signed-off-by:
Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Pavel Pisa authored
It can only simplify generated code because GCC is sure that it can replace whole register content. Signed-off-by:
Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Pavel Pisa authored
Resolve "vivado component: update to match bus_sampling changes." Closes #236 See merge request illeondr/CAN_FD_IP_Core!189
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Pavel Pisa authored
Closed 236 Signed-off-by:
Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Pavel Pisa authored
Added files bus_sampling/data_edge_detector.vhd spirit:name>bus_sampling/trv_delay_meas.vhd Signed-off-by:
Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Pavel Pisa authored
Resolve VHDL 2008 is not supported in Vivado IP packager still . Closes #226 See merge request illeondr/CAN_FD_IP_Core!188
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- 06 Jan, 2019 5 commits
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Pavel Pisa authored
Signed-off-by:
Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Pavel Pisa authored
Signed-off-by:
Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Pavel Pisa authored
This solution is compromise with minimal/no intrusive changes to pyXact_generator. When file pyXact_generator/templates/memory_reg.vhd changes a little in mainline then there is chance that patch succeed. If change more then script fails and manual intervention is necessary. Signed-off-by:
Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Pavel Pisa authored
Fixes Quartus error "generic data_width cannot be used in its own interface list" The function is added which check ascending or descending direction of index range for data_mask, reset_value and auto_clear generics and process indexing appropriately. Signed-off-by:
Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Ille, Ondrej, Ing. authored
SRC REGISTERS Fixed reset. Fixed reset of memory registers module. Soft reset by MODE[RST] should also reset content of memory register. Added driver of res_out to also reset generated register components.
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