- 18 Jun, 2018 1 commit
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Martin Jeřábek authored
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- 15 Jun, 2018 2 commits
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Martin Jeřábek authored
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Martin Jeřábek authored
Mainly to silence VUnit warnings. It's also true that it's not a testbench, so it should not look like one.
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- 29 May, 2018 1 commit
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Ille, Ondrej, Ing. authored
to test lib. Modified read function to access individual memory entry to use the same test memories in Protocol control unit test.
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- 19 May, 2018 3 commits
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Ille, Ondrej, Ing. authored
Used array of 64 * std logic vector instead of one long 512 bit vector. Updated sanity and RX Buffer tb accordingly.
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Ille, Ondrej, Ing. authored
If step fails, contents of all memories are printed to console for better overview of situation.
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Ille, Ondrej, Ing. authored
If step fails, contents of all memories are printed to console for better overview of situation.
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- 08 May, 2018 2 commits
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Ille, Ondrej, Ing. authored
functions from CAN Test lib to make use of Hardware abstraction.
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Ille, Ondrej, Ing. authored
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- 30 Apr, 2018 1 commit
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Ille, Ondrej, Ing. authored
Changed TXT Buffer index in sanity test to be 1 based instead of 0 based.
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- 16 Apr, 2018 2 commits
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Martin Jeřábek authored
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Martin Jeřábek authored
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- 12 Mar, 2018 1 commit
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Ille, Ondrej, Ing. authored
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- 23 Feb, 2018 3 commits
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
of identifier. Modified correction function for proper correction on Base and Extended Identifiers.
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Ille, Ondrej, Ing. authored
If frame is base, only base identifier is stored. Thisway identifier is should be stored the same way as in RX and TXT Buffers.
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- 17 Feb, 2018 4 commits
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
brought up with new, prioritized buffer implementation.
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Ille, Ondrej, Ing. authored
brought up with new, prioritized buffer implementation.
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- 10 Feb, 2018 3 commits
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Ille, Ondrej, Ing. authored
there is no need to save LUTs by supporting only non-FD frames on TX.
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Martin Jeřábek authored
Next time I'll try it before pushing lest it bite me again.
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Martin Jeřábek authored
When using valgrind's callgrind to profile the testbench, 80% of time was spent by updating the shift register used for bus delay. signal'delayed is one possibility, but it needs a static value. So I implemented a dynamic signal delayer using a FIFO recording events on signal and then replaying them on the delayed signal.
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- 09 Feb, 2018 1 commit
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Ille, Ondrej, Ing. authored
Field is generated in the FRAME. On transmission field is not inserted (of course, the Protocol control decodes it by itself). Sanity test stores RWCNT to TX memories and reads it back. Thus on TX RWCNT is in TX memorz from frame generation. on RX it is in RX Memory since it was read from the controller. So it is a simple check that HW returns the same RWCNT as SW generated frame has...
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- 06 Feb, 2018 1 commit
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Ille, Ondrej, Ing. authored
register map from IP-XACT
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- 05 Feb, 2018 2 commits
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Martin Jeřábek authored
#23, #24
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Martin Jeřábek authored
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- 30 Jan, 2018 1 commit
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Martin Jeřábek authored
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- 18 Jan, 2018 2 commits
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Ille, Ondrej, Ing. authored
Separate package created. Original constants erased from CAN Constants
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Ille, Ondrej, Ing. authored
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- 20 Dec, 2017 2 commits
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Ille, Ondrej, Ing. authored
Read support remaining.
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Ille, Ondrej, Ing. authored
preparation for automatic generation of register map.
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- 15 Dec, 2017 1 commit
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Ille, Ondrej, Ing. authored
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- 13 Dec, 2017 1 commit
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Ille, Ondrej, Ing. authored
automatic license updater
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- 23 Nov, 2017 2 commits
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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