1. 02 Dec, 2019 1 commit
  2. 27 Nov, 2019 2 commits
  3. 08 Nov, 2019 2 commits
  4. 07 Nov, 2019 1 commit
    • Ille, Ondrej, Ing.'s avatar
      src: Implement SSP generator! · c9bc3517
      Ille, Ondrej, Ing. authored
      This replaces 128 bit shift mux by two coupled counters.
      Controlled by Protocol control FSM. Delays first SSP by
      SSP offset and each next SSP by the value of data bit
      time which it measures!
  5. 09 Oct, 2019 1 commit
  6. 07 Oct, 2019 1 commit
  7. 02 Oct, 2019 1 commit
  8. 13 Sep, 2019 5 commits
  9. 31 Jul, 2019 1 commit
  10. 30 Jul, 2019 1 commit
    • Ille, Ondrej, Ing.'s avatar
      src: Simplify Timestamp storing in RX Buffer. · 9afb98d9
      Ille, Ondrej, Ing. authored
      Always store Timestamp in the end of frame, instead of storing
      it there only for EOF TS. Two states where TS was originally
      stored are replaced by dummy states and only zeroes are first
      stored to timestamp words. After rec_valid, Timestamp is always
      stored. Number of FSM states is not reduced, but FSM state
      transitions are simplified. Also data input decoding logic
      and commiting logic is simplified!
  11. 27 Jul, 2019 1 commit
  12. 12 Jul, 2019 1 commit
  13. 01 Jul, 2019 1 commit
  14. 21 Jun, 2019 1 commit
    • Ille, Ondrej, Ing.'s avatar
      src: Use CRC init vector loading controlled by Protocol control FSM. · 0f1153da
      Ille, Ondrej, Ing. authored
      Init vector is not loaded on by edge on enable but by PC FSM. This
      allows removing special mux on datapath in Bit-destuffing. Thanks
      to this, when H-sync edge occurs in Idle right in Process pipeline
      stage, unit properly samples recessive and not dominant and measures
      length of arbitration field properly.
      CRC Init vector is always loaded in situations:
      1. In Intermission (first or second bit), does not mind being loaded
         twice. Can't be loaded in third one since this can already be SOF
         and first bit of calculation might be executed.
      2. Transfer to Idle after integration or reintegration.
      Note that there is always intermission after every frame so we are
      sure that init vector will get loaded! Loading post re-integration
      and integration is done just to be sure it is loaded after unit
      just joins the bus.
  15. 14 Jun, 2019 3 commits
    • Ille, Ondrej, Ing.'s avatar
      src: Fix calculation of CRC source. · 67ac3805
      Ille, Ondrej, Ing. authored
      Use RX CRC in whole arbitration.
    • Ille, Ondrej, Ing.'s avatar
      src: Add sample control by-passing. · b95cc83d
      Ille, Ondrej, Ing. authored
      This is implemented to so that resynchronisation works properly
      in case of bit-rate shift when there is resynchronisation edge
      just next cycle after Sample point (in Process pipeline stage).
      Single counter solution was reverted since adding it caused critical
      timing paths and core got below 100 MHz. Trade of is sth like:
      Two counters solution: + 50 LUTs, + DFFs, but better timing by
      approx 2.5 ns Setup Slack.
      So in the end we will stick with two counters solution, just fix
      bug that was discovered by sp_control bypass to Process pipeline
    • Ille, Ondrej, Ing.'s avatar
      Revert "src: Remove second bit time counters." · 7ac4f6c6
      Ille, Ondrej, Ing. authored
      This reverts commit e27ab4b2.
  16. 13 Jun, 2019 1 commit
    • Ille, Ondrej, Ing.'s avatar
      src: Remove second bit time counters. · e27ab4b2
      Ille, Ondrej, Ing. authored
      Implemented sample control bypassing scheme which allows
      updating sample control right in first cycle after bit
      rate shift. Added extra load of expected segment length
      register in BRS.
  17. 10 Jun, 2019 1 commit
  18. 09 Jun, 2019 2 commits
  19. 08 Jun, 2019 1 commit
  20. 06 Jun, 2019 5 commits
  21. 05 Jun, 2019 5 commits
  22. 02 Jun, 2019 2 commits