1. 02 Dec, 2019 1 commit
  2. 27 Nov, 2019 2 commits
  3. 08 Nov, 2019 1 commit
  4. 07 Nov, 2019 1 commit
    • Ille, Ondrej, Ing.'s avatar
      src: Implement SSP generator! · c9bc3517
      Ille, Ondrej, Ing. authored
      This replaces 128 bit shift mux by two coupled counters.
      Controlled by Protocol control FSM. Delays first SSP by
      SSP offset and each next SSP by the value of data bit
      time which it measures!
      c9bc3517
  5. 09 Oct, 2019 1 commit
  6. 02 Oct, 2019 1 commit
  7. 13 Sep, 2019 3 commits
  8. 01 Jul, 2019 1 commit
  9. 14 Jun, 2019 1 commit
  10. 13 Jun, 2019 1 commit
    • Ille, Ondrej, Ing.'s avatar
      src: Remove second bit time counters. · e27ab4b2
      Ille, Ondrej, Ing. authored
      Implemented sample control bypassing scheme which allows
      updating sample control right in first cycle after bit
      rate shift. Added extra load of expected segment length
      register in BRS.
      e27ab4b2
  11. 09 Jun, 2019 1 commit
  12. 08 Jun, 2019 1 commit
  13. 06 Jun, 2019 2 commits
  14. 05 Jun, 2019 2 commits
  15. 02 Jun, 2019 1 commit
  16. 28 May, 2019 2 commits
  17. 27 May, 2019 1 commit
  18. 24 May, 2019 1 commit
  19. 19 May, 2019 1 commit
  20. 07 May, 2019 1 commit
  21. 05 May, 2019 1 commit
  22. 04 May, 2019 3 commits
  23. 18 Mar, 2019 2 commits
  24. 13 Mar, 2019 4 commits
  25. 28 Feb, 2019 1 commit
  26. 02 Jan, 2019 2 commits
  27. 29 Dec, 2018 1 commit