1. 02 Dec, 2019 1 commit
  2. 27 Nov, 2019 1 commit
  3. 07 Nov, 2019 1 commit
    • Ille, Ondrej, Ing.'s avatar
      src: Implement SSP generator! · c9bc3517
      Ille, Ondrej, Ing. authored
      This replaces 128 bit shift mux by two coupled counters.
      Controlled by Protocol control FSM. Delays first SSP by
      SSP offset and each next SSP by the value of data bit
      time which it measures!
      c9bc3517
  4. 13 Sep, 2019 4 commits
  5. 01 Jul, 2019 1 commit
    • Ille, Ondrej, Ing.'s avatar
      src: Use TX Trigger for SSP. · d40dc7e5
      Ille, Ondrej, Ing. authored
      One clock cycle delay added so that data are already available on
      TX. This imposes lower limit of 2 on length of SSP! Data are shifted
      to TX Data cache by the same trigger. Furthermore, TX Trigger is
      gated everywhere apart from Secondary sampling!
      d40dc7e5
  6. 27 Jun, 2019 1 commit
  7. 08 Jun, 2019 1 commit
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  9. 02 Jun, 2019 1 commit
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  15. 09 Mar, 2019 1 commit
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  17. 19 Jan, 2019 1 commit
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  20. 02 Jan, 2019 1 commit
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  27. 09 Jul, 2018 1 commit
  28. 29 Jun, 2018 1 commit