- 05 Sep, 2018 4 commits
-
-
Ille, Ondrej, Ing. authored
-
Ille, Ondrej, Ing. authored
-
Ille, Ondrej, Ing. authored
-
Ille, Ondrej, Ing. authored
Allowed one clock cycle mismatch. On more than one clock cycle, error is reported.
-
- 03 Sep, 2018 14 commits
-
-
Ille, Ondrej, Ing. authored
Resolve "Suspend transmission feature test" Closes #166 See merge request illeondr/CAN_FD_IP_Core!147
-
Ille, Ondrej, Ing. authored
for 3, we wont start the transmission right after the Intermission by Node 2, because the frame will be inserted after sample point, and thus Node 2 will send it after 1 bit of being Idle.
-
Ille, Ondrej, Ing. authored
CAN FD Standard sets the counter to value between 119 and 127 ich frame is successfully transmitted in error passive!!!
-
Ille, Ondrej, Ing. authored
-
Ille, Ondrej, Ing. authored
-
Ille, Ondrej, Ing. authored
after 8 hours of reading documentation on ASIC design flow!!!
-
Ille, Ondrej, Ing. authored
-
Ille, Ondrej, Ing. authored
-
Ille, Ondrej, Ing. authored
-
Ille, Ondrej, Ing. authored
-
Martin Jeřábek authored
Resolve "ci: test linux driver build" Closes #162 See merge request illeondr/CAN_FD_IP_Core!145
-
Martin Jeřábek authored
-
Martin Jeřábek authored
-
Martin Jeřábek authored
-
- 02 Sep, 2018 17 commits
-
-
Ille, Ondrej, Ing. authored
-
Ille, Ondrej, Ing. authored
-
Ille, Ondrej, Ing. authored
measures if length of Suspend field are proper 8 bits. Signed-off-by:
Ille, Ondrej, Ing <illeondr@fel.cvut.cz>
-
Ille, Ondrej, Ing. authored
Resolve "Form error detection in delim_ack" Closes #174 See merge request illeondr/CAN_FD_IP_Core!144
-
Ille, Ondrej, Ing. authored
-
Ille, Ondrej, Ing. authored
Resolve "Bus Start Test" Closes #173 See merge request illeondr/CAN_FD_IP_Core!143
-
Ille, Ondrej, Ing. authored
integration finish during bus-start test.
-
Ille, Ondrej, Ing. authored
-
Ille, Ondrej, Ing. authored
Adding 1 is not handled properly and due to that feature test always finds out one iteration later!
-
Ille, Ondrej, Ing. authored
stuff error in arbitration field.
-
Martin Jeřábek authored
add reduce_lib.vhd to vivado component file See merge request illeondr/CAN_FD_IP_Core!142
-
Ille, Ondrej, Ing. authored
-
Martin Jeřábek authored
-
Ille, Ondrej, Ing. authored
-
Ille, Ondrej, Ing. authored
To move from off to interframe, unit must have integration finished! Also, unit must go directly to interm-idle so that it will interpret next DOMINANT as SOF and not as Overload condition!!
-
Ille, Ondrej, Ing. authored
-
Ille, Ondrej, Ing. authored
11 recessivve bits between two frames, not more.
-
- 31 Aug, 2018 5 commits
-
-
Ille, Ondrej, Ing. authored
Resolve "Fixup broken VHDL 2008 synthesis" Closes #180 See merge request illeondr/CAN_FD_IP_Core!141
-
Ille, Ondrej, Ing. authored
which does not support full VHDL 2008...
-
Ille, Ondrej, Ing. authored
Resolve "TXBHCI is triggered on wrong state transitions" Closes #176 See merge request illeondr/CAN_FD_IP_Core!140
-
Ille, Ondrej, Ing. authored
-
Ille, Ondrej, Ing. authored
-