Commit ff941cbf authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Re-factored busSync.

parent 3541a1a2
This diff is collapsed.
...@@ -80,6 +80,7 @@ USE IEEE.std_logic_1164.all; ...@@ -80,6 +80,7 @@ USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL; USE IEEE.numeric_std.ALL;
USE WORK.CANconstants.ALL; USE WORK.CANconstants.ALL;
use work.CANcomponents.ALL; use work.CANcomponents.ALL;
use work.cmn_lib.all;
entity CAN_top_level is entity CAN_top_level is
generic( generic(
......
...@@ -855,19 +855,6 @@ package CANcomponents is ...@@ -855,19 +855,6 @@ package CANcomponents is
end component; end component;
----------------------------------------------------------------------------
-- Asynchronous resset synchroniser
----------------------------------------------------------------------------
component rst_sync is
generic (
constant reset_polarity : std_logic
);
port (
signal clk : in std_logic;
signal arst : in std_logic;
signal rst : out std_logic
);
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- APB Interface -- APB Interface
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
......
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018
--
-- Authors:
-- Ondrej Ille <ondrej.ille@gmail.com>
-- Martin Jerabek <martin.jerabek01@gmail.com>
--
-- Project advisors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
--
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Library with component declarations for common design entities.
--------------------------------------------------------------------------------
-- Revision History:
-- 10.12.2018 Created file
--------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
package cmn_lib is
----------------------------------------------------------------------------
-- Reset synchronizer
----------------------------------------------------------------------------
component rst_sync is
generic (
constant reset_polarity : std_logic
);
port (
signal clk : in std_logic;
signal arst : in std_logic;
signal rst : out std_logic
);
end component rst_sync;
----------------------------------------------------------------------------
-- Signal synchroniser - synchronisation chain
----------------------------------------------------------------------------
component sig_sync is
generic (
constant timing_check : boolean := true
);
port (
signal clk : in std_logic;
signal async : in std_logic;
signal sync : out std_logic
);
end component sig_sync;
----------------------------------------------------------------------------
-- Shift register
----------------------------------------------------------------------------
component shift_reg is
generic (
constant reset_polarity : std_logic;
constant reset_value : std_logic_vector;
constant width : natural;
constant shift_down : boolean
);
port (
signal clk : in std_logic;
signal res_n : in std_logic;
signal input : in std_logic;
signal preload : in std_logic;
signal preload_val : in std_logic_vector(width - 1 downto 0);
signal enable : in std_logic;
signal reg_stat : out std_logic_vector(width - 1 downto 0);
signal output : out std_logic
);
end component shift_reg;
----------------------------------------------------------------------------
-- Majority out of 3 decoder.
----------------------------------------------------------------------------
component majority_decoder_3 is
port (
signal input : in std_logic_vector(2 downto 0);
signal output : out std_logic
);
end component majority_decoder_3;
end package cmn_lib;
...@@ -53,11 +53,11 @@ use ieee.std_logic_1164.all; ...@@ -53,11 +53,11 @@ use ieee.std_logic_1164.all;
entity majority_decoder_3 is entity majority_decoder_3 is
port ( port (
signal input : in std_logic_vector(2 downto 0); signal input : in std_logic_vector(2 downto 0);
signal output : in std_logic signal output : out std_logic
); );
end majority_decoder_3; end majority_decoder_3;
architecture rtl of majority_decoder is architecture rtl of majority_decoder_3 is
begin begin
with input select output <= with input select output <=
...@@ -68,6 +68,7 @@ begin ...@@ -68,6 +68,7 @@ begin
'0' when "100", '0' when "100",
'1' when "101", '1' when "101",
'1' when "110", '1' when "110",
'1' when "111"; '1' when "111",
'X' when others;
end rtl; end rtl;
...@@ -70,7 +70,7 @@ architecture rtl of rst_sync is ...@@ -70,7 +70,7 @@ architecture rtl of rst_sync is
begin begin
-- Reset synchroniser process -- Reset synchroniser process
rst_sync_proc : process (clk, arst_n) rst_sync_proc : process (clk, arst)
begin begin
if (arst = reset_polarity) then if (arst = reset_polarity) then
rff <= reset_polarity; rff <= reset_polarity;
......
...@@ -61,7 +61,7 @@ entity sig_sync is ...@@ -61,7 +61,7 @@ entity sig_sync is
); );
end sig_sync; end sig_sync;
architecture rtl of rst_sync is architecture rtl of sig_sync is
-- Synchroniser registers -- Synchroniser registers
signal rff : std_logic; signal rff : std_logic;
......
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