Commit ff941cbf authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Re-factored busSync.

parent 3541a1a2
...@@ -84,7 +84,8 @@ ...@@ -84,7 +84,8 @@
-- Thus reading TRV_DELAY register would always result in tran- -- Thus reading TRV_DELAY register would always result in tran-
-- sceiver delay of last CAN FD Frame. This is done to avoid -- sceiver delay of last CAN FD Frame. This is done to avoid
-- reading wrong value from TRV_DELAY register during measurment. -- reading wrong value from TRV_DELAY register during measurment.
-- -- 10.12.2018 Re-factored, added generic Shift register instances. Added
-- generic synchronisation chain module.
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Library ieee; Library ieee;
...@@ -92,6 +93,7 @@ USE IEEE.std_logic_1164.all; ...@@ -92,6 +93,7 @@ USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL; USE IEEE.numeric_std.ALL;
USE WORK.CANconstants.ALL; USE WORK.CANconstants.ALL;
use work.CAN_FD_register_map.all; use work.CAN_FD_register_map.all;
use work.cmn_lib.all;
entity busSync is entity busSync is
GENERIC ( GENERIC (
...@@ -178,6 +180,29 @@ entity busSync is ...@@ -178,6 +180,29 @@ entity busSync is
-- Used only for bit error with secondary sample point -- Used only for bit error with secondary sample point
); );
end entity;
architecture rtl of busSync is
-----------------------------------------------------------------------------
-- Internal constants declaration.
-----------------------------------------------------------------------------
-- Shift registers length
constant SSP_SHIFT_LENGTH : natural := 130;
constant TX_DATA_SHIFT_LENGTH : natural := 130;
-- Reset value for secondar sampling point shift registers
constant SSP_SHIFT_RST_VAL : std_logic_vector(SSP_SHIFT_LENGTH - 1
downto 0) :=
(OTHERS => '0');
constant TX_DATA_SHIFT_RST_VAL : std_logic_vector(TX_DATA_SHIFT_LENGTH - 1
downto 0) :=
(OTHERS => RECESSIVE);
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- Driving bus aliases -- Driving bus aliases
...@@ -189,39 +214,48 @@ entity busSync is ...@@ -189,39 +214,48 @@ entity busSync is
-- Enable of the whole driver -- Enable of the whole driver
signal drv_ena : std_logic; signal drv_ena : std_logic;
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- Internal registers and signals -- Internal registers and signals
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- Synchronisation chain for data input (first,second and output register) -- CAN RX synchronisation chain output
signal sync_Chain_1 : std_logic; signal CAN_rx_synced : std_logic;
signal sync_Chain_2 : std_logic;
signal sync_Data : std_logic;
-- Shift registers length
constant shift_length : natural:=130;
-- Bus sampling and edge detection, Previously sampled value on CAN bus -- Internal received CAN Data. Selected between Raw input value and
signal prev_Sample : std_logic; -- synchronised value by signal synchroniser.
signal CAN_rx_i : std_logic;
-- Majority value from all three sampled values in tripple sampling shift -- Majority value from all three sampled values in tripple sampling shift
-- register -- register
signal trs_majority : std_logic; signal CAN_rx_trs_majority : std_logic;
-- CAN RX Data selected between normally sampled data (CAN_rx_i) and
-- Tripple sampled data!
signal data_rx_nbt : std_logic;
-- Bus sampling and edge detection, Previously sampled value on CAN bus
signal prev_Sample : std_logic;
-- Secondary sampling signal (sampling with transciever delay compensation) -- Secondary sampling signal (sampling with transciever delay compensation)
signal sample_sec : std_logic; signal sample_sec : std_logic;
signal sample_sec_comb : std_logic;
-- Secondary sample signal 1 and 2 clk_sys cycles delayed -- Secondary sample signal 1 and 2 clk_sys cycles delayed
signal sample_sec_del_1 : std_logic; signal sample_sec_del_1 : std_logic;
signal sample_sec_del_2 : std_logic; signal sample_sec_del_2 : std_logic;
-- Shift Register for storing the TX data for secondary sample point -- Shift Register for storing the TX data for secondary sample point
signal ssp_shift : std_logic_vector signal tx_data_shift : std_logic_vector
(shift_length - 1 downto 0); (TX_DATA_SHIFT_LENGTH - 1 downto 0);
-- Delayed TX Data from TX Data shift register at position of secondary
-- sampling point.
signal tx_data_delayed : std_logic;
-- Shift Register for generating secondary sampling signal -- Shift Register for generating secondary sampling signal
signal sample_sec_shift : std_logic_vector signal sample_sec_shift : std_logic_vector
(shift_length - 1 downto 0); (SSP_SHIFT_LENGTH - 1 downto 0);
-- Register for edge detection -- Register for edge detection
signal edge_rx_det : std_logic; signal edge_rx_det : std_logic;
...@@ -250,26 +284,41 @@ entity busSync is ...@@ -250,26 +284,41 @@ entity busSync is
signal trv_delay : std_logic_vector(6 downto 0); signal trv_delay : std_logic_vector(6 downto 0);
--Delay compensation measuring is running (between tx edge and rx edge) --Delay compensation measuring is running (between tx edge and rx edge)
signal trv_running : std_logic; signal trv_meas_running : std_logic;
signal trv_to_restart : std_logic; signal trv_meas_to_restart : std_logic;
end entity;
architecture rtl of busSync is
begin begin
--Driving bus alias
---------------------------------------------------------------------------
-- Driving bus alias
---------------------------------------------------------------------------
drv_sam <= drv_bus(DRV_SAM_INDEX); drv_sam <= drv_bus(DRV_SAM_INDEX);
drv_ena <= drv_bus(DRV_ENA_INDEX); drv_ena <= drv_bus(DRV_ENA_INDEX);
--Synchronisation-chain enable
sync_Data <= sync_Chain_2 when use_Sync=true else
CAN_rx;
--Output data propagation ----------------------------------------------------------------------------
CAN_tx <= data_tx; -- Synchronisation chain for input signal
----------------------------------------------------------------------------
can_rx_sig_sync_comp : sig_sync
port map(
clk => clk_sys,
async => CAN_rx,
sync => CAN_rx_synced
);
---------------------------------------------------------------------------
-- Synchronisation-chain selection
---------------------------------------------------------------------------
sync_chain_true : if (use_Sync = true) generate
CAN_rx_i <= CAN_rx_synced;
end generate;
sync_chain_false : if (use_Sync = false) generate
CAN_rx_i <= CAN_rx;
end generate;
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Transceiver delay propagation to output. -- Transceiver delay propagation to output.
-- Transceiver delay is propagated only once the measurement is finished! -- Transceiver delay is propagated only once the measurement is finished!
...@@ -284,74 +333,75 @@ begin ...@@ -284,74 +333,75 @@ begin
elsif (rising_edge(clk_sys)) then elsif (rising_edge(clk_sys)) then
-- Do not propagate during the measurement! -- Do not propagate during the measurement!
if (trv_running = '0') then if (trv_meas_running = '0') then
trv_delay_out <= "000000000" & trv_delay; trv_delay_out <= "000000000" & trv_delay;
end if; end if;
end if; end if;
end process; end process;
-- Registers to output propagation
sample_sec_out <= sample_sec;
sample_sec_del_1_out <= sample_sec_del_1;
sample_sec_del_2_out <= sample_sec_del_2;
-- Bit Error propagation
bit_Error <= bit_Error_reg;
--Tripple sampling majority selection ---------------------------------------------------------------------------
trs_majority <= '1' when trs_reg = "110" else -- Tripple sampling majority selection
'1' when trs_reg = "101" else ---------------------------------------------------------------------------
'1' when trs_reg = "011" else trs_maj_dec_comp : majority_decoder_3
'0' when trs_reg = "001" else port map(
'0' when trs_reg = "010" else input => trs_reg,
'0' when trs_reg = "100" else output => CAN_rx_trs_majority
'0' when trs_reg = "000" else );
'1' when trs_reg = "111" else
'1'; --When unknown rather climb to recessive
---------------------------------------------------------------------------
---------------------------------------------------------------------------- -- Selection of RX Data sampled in Nominal Bit-rate between Normally
-- Synchronisation chain -- sampled and tripple sampled data.
---------------------------------------------------------------------------- ---------------------------------------------------------------------------
sync_chain_proc : process(res_n, clk_sys) data_rx_nbt <= CAN_rx_trs_majority when (drv_sam = TSM_ENABLE) else
begin CAN_rx_i;
if (res_n = '0') then
sync_Chain_1 <= RECESSIVE;
sync_Chain_2 <= RECESSIVE;
elsif (rising_edge(clk_sys)) then
sync_Chain_1 <= CAN_rx;
sync_Chain_2 <= sync_Chain_1;
end if;
end process sync_chain_proc;
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Data Edge detection (for one clk_sys period) -- RX Data Edge detection (for one clk_sys period)
-- Note: Sucessful samplng of previous bit is necessary -- Note: Sucessful samplng of previous bit is necessary
-- (prev_Sample register) -- (prev_Sample register)
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
edge_proc : process(res_n, clk_sys) rx_edge_proc : process(res_n, clk_sys)
begin begin
if (res_n = ACT_RESET) then if (res_n = ACT_RESET) then
edge_rx_det <= RECESSIVE; edge_rx_det <= RECESSIVE;
edge_rx_valid <= '0'; edge_rx_valid <= '0';
edge_tx_det <= RECESSIVE;
edge_tx_valid <= '0';
elsif rising_edge(clk_sys) then elsif rising_edge(clk_sys) then
-- Rx data -- Rx data
edge_rx_det <= sync_Data; edge_rx_det <= CAN_rx_i;
--Rx data edge appeared from recessive to dominant --Rx data edge appeared from recessive to dominant
if ((not edge_rx_det = sync_Data)and if ((not edge_rx_det = CAN_rx_i) and
(not prev_Sample = sync_Data) and (prev_Sample = RECESSIVE)) (not prev_Sample = CAN_rx_i) and (prev_Sample = RECESSIVE))
then then
edge_rx_valid <= '1'; edge_rx_valid <= '1';
else else
edge_rx_valid <= '0'; edge_rx_valid <= '0';
end if; end if;
end if;
end process rx_edge_proc;
----------------------------------------------------------------------------
-- TX Data Edge detection (for one clk_sys period)
----------------------------------------------------------------------------
tx_edge_proc : process(res_n, clk_sys)
begin
if (res_n = ACT_RESET) then
edge_tx_det <= RECESSIVE;
edge_tx_valid <= '0';
elsif rising_edge(clk_sys) then
-- Tx data -- Tx data
edge_tx_det <= data_tx; edge_tx_det <= data_tx;
--Tx data edge appeared from RECESSIVE to dominant --Tx data edge appeared from RECESSIVE to dominant
if ((not (edge_tx_det = data_tx)) and (edge_tx_det = RECESSIVE)) then if ((not (edge_tx_det = data_tx)) and (edge_tx_det = RECESSIVE)) then
edge_tx_valid <= '1'; edge_tx_valid <= '1';
...@@ -360,91 +410,150 @@ begin ...@@ -360,91 +410,150 @@ begin
end if; end if;
end if; end if;
end process edge_proc; end process tx_edge_proc;
-- Propagating edge value on output
sync_edge <= edge_rx_valid;
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Measuring transciever delay compenstaion -- Control for transceiver delay measurement.
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
trv_delay_proc : process(res_n, clk_sys) trv_delay_proc : process(res_n, clk_sys)
begin begin
if (res_n = '0') then if (res_n = '0') then
trv_delay <= (OTHERS => '0'); trv_meas_running <= '0';
trv_running <= '0'; trv_meas_to_restart <= '0';
trv_to_restart <= '0';
elsif (rising_edge(clk_sys)) then elsif (rising_edge(clk_sys)) then
-------------------------------------------------------------------- -- Delay measurement enabled
-- Measuring of delay enabled
--------------------------------------------------------------------
if (trv_delay_calib = '1') then if (trv_delay_calib = '1') then
---------------------------------------------------------------- -- Stop delay measurement upon receiving the edge on RX Data.
-- Starting and stop the counter
----------------------------------------------------------------
if (edge_rx_valid = '1') then if (edge_rx_valid = '1') then
trv_running <= '0'; trv_meas_running <= '0';
elsif (edge_tx_valid = '1' and trv_to_restart = '0') then
trv_running <= '1'; -- Start measurement on edge on TX Data.
trv_to_restart <= '1'; elsif (edge_tx_valid = '1' and trv_meas_to_restart = '0') then
trv_meas_running <= '1';
trv_meas_to_restart <= '1';
end if; end if;
---------------------------------------------------------------- else
-- Counting trv_meas_to_restart <= '0';
---------------------------------------------------------------- end if;
end if;
end process trv_delay_proc;
----------------------------------------------------------------------------
-- Transceiver delay measurement
----------------------------------------------------------------------------
trv_delay_meas_proc : process(res_n, clk_sys)
begin
if (res_n = ACT_RESET) then
trv_delay <= (OTHERS => '0');
elsif (rising_edge(clk_sys)) then
-- Delay measurement enabled
if (trv_delay_calib = '1') then
-- Restart upon edge on TX Data
if (edge_tx_valid = '1') then if (edge_tx_valid = '1') then
trv_delay <= (OTHERS => '0'); trv_delay <= (OTHERS => '0');
elsif (trv_running = '1') then
-- Increment each clock cycle
elsif (trv_meas_running = '1') then
trv_delay <= std_logic_vector(unsigned(trv_delay) + 1); trv_delay <= std_logic_vector(unsigned(trv_delay) + 1);
else
trv_delay <= trv_delay;
end if; end if;
else
trv_running <= trv_running;
trv_to_restart <= '0';
end if; end if;
end if; end if;
end process trv_delay_proc; end process;
----------------------------------------------------------------------------
-- Shift register for secondary sampling point. Normal sample point trigger
-- is shifted into shift register to generate delayed sampling point.
----------------------------------------------------------------------------
ssp_shift_reg_comp : shift_reg
generic map(
reset_polarity => ACT_RESET,
reset_value => SSP_SHIFT_RST_VAL,
width => SSP_SHIFT_LENGTH,
shift_down => false
)
port map(
clk => clk_sys,
res_n => res_n,
input => sample_dbt,
preload => ssp_reset,
preload_val => SSP_SHIFT_RST_VAL,
enable => '1',
reg_stat => sample_sec_shift,
output => open
);
----------------------------------------------------------------------------
-- Shift register for TX data. Stored by shift register to be compared
-- with sampled RX Data in Secondary sampling point to detect bit error.
----------------------------------------------------------------------------
tx_data_shift_reg_comp : shift_reg
generic map(
reset_polarity => ACT_RESET,
reset_value => TX_DATA_SHIFT_RST_VAL,
width => TX_DATA_SHIFT_LENGTH,
shift_down => false
)
port map(
clk => clk_sys,
res_n => res_n,
input => data_tx,
preload => ssp_reset,
preload_val => TX_DATA_SHIFT_RST_VAL,
enable => '1',
reg_stat => tx_data_shift,
output => open
);
----------------------------------------------------------------------------
-- Secondary sampling point address decoder. Secondary sampling point
-- is taken from SSP Shift register at position of transceiver delay.
----------------------------------------------------------------------------
sample_sec_comb <= sample_sec_shift(to_integer(unsigned(trv_delay)));
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Generating shifted sampling signal (sample_sec) -- Delayed TX data address decoder. At the time of secondary sampling point,
-- TX data from TX Data shift register at position of transceiver delay are
-- taken for bit error detection!
----------------------------------------------------------------------------
tx_data_delayed <= tx_data_shift(to_integer(unsigned(trv_delay)));
----------------------------------------------------------------------------
-- Registering secondary sampling point
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
ssp_gen_proc : process(res_n, clk_sys) ssp_gen_proc : process(res_n, clk_sys)
begin begin
if (res_n = '0') then if (res_n = ACT_RESET) then
sample_sec <= '0'; sample_sec <= '0';
sample_sec_shift <= (OTHERS => '0');
ssp_shift <= (OTHERS => RECESSIVE);
elsif rising_edge(clk_sys) then elsif rising_edge(clk_sys) then
if (ssp_reset = '1') then if (ssp_reset = '1') then
sample_sec <= '0';
-- Erasing secondary sampling signal shift register
sample_sec_shift <= (OTHERS => '0');
-- Erasing Shift register for ssp bit error detection
ssp_shift <= (OTHERS => RECESSIVE);
else else
-- Shifting DBT sampling signal sample_sec <= sample_sec_comb;
sample_sec_shift <= sample_sec_shift(shift_length - 2 downto 0)
& sample_dbt;
-- Shifted signal with trv_delay
sample_sec <= sample_sec_shift(
to_integer(unsigned(trv_delay)));
-- Storing TX data
ssp_shift <= ssp_shift(shift_length - 2 downto 0) &
data_tx;
end if; end if;
end if; end if;
end process; end process;
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Delay process for secondary sampling singal -- Delay process for secondary sampling singal
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
...@@ -466,83 +575,119 @@ begin ...@@ -466,83 +575,119 @@ begin
-- desired then majority out of whole shift register is selected as sampled -- desired then majority out of whole shift register is selected as sampled
-- value! -- value!
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
tripple_sam_proc : process(res_n, clk_sys) trs_shift_reg_comp : shift_reg
generic map(
reset_polarity => ACT_RESET,
reset_value => "000",
width => 3,
shift_down => false
)
port map(
clk => clk_sys,
res_n => res_n,
input => CAN_rx_i,
preload => '0',
preload_val => "000",
enable => '1',
reg_stat => trs_reg,
output => open
);
----------------------------------------------------------------------------
-- Sampling of bus value
----------------------------------------------------------------------------
sample_proc : process(res_n, clk_sys)
begin begin
if (res_n = ACT_RESET) then if (res_n = ACT_RESET) then
trs_reg <= (OTHERS => RECESSIVE); prev_Sample <= RECESSIVE;
elsif (rising_edge(clk_sys)) then elsif rising_edge(clk_sys) then
-- Shift register realisation
trs_reg(0) <= sync_Data; if (drv_ena = ENABLED) then
trs_reg(2 downto 1) <= trs_reg(1 downto 0); case sp_control is
----------------------------------------------------------------
-- Sampling with Nominal Bit Time
-- (normal CAN, transceiver, receiver)
--
-- Tripple sampling option selects the majority from last
-- three sampled values
----------------------------------------------------------------
when NOMINAL_SAMPLE =>
if (sample_nbt = '1') then
prev_Sample <= data_rx_nbt;
end if;
----------------------------------------------------------------
-- Sampling with Data Bit Time (CAN FD, reciever).
----------------------------------------------------------------
when DATA_SAMPLE =>
if (sample_dbt = '1') then
prev_Sample <= CAN_rx_i;