Commit ff5fe896 authored by Martin Jeřábek's avatar Martin Jeřábek
Browse files

remove Deprecated sources

parent 10e81648
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com>
--
-- Project advisors and co-authors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
-- Martin Jerabek <jerabma7@fel.cvut.cz>
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
--Serial bit Stuffer with generic number of stuff length (number of maximum following bits of same value). Con----
--tains internal buffer for data. Circuit is started by '1' at start input and valid data size to be stuffed, ----
--and first bit of data on data_in input. Data are propagated to the data_out and if bit is stuffed input data ---
--are stored in internal buffer. Buffer size is calculated in worst possible case (most stuff bits) from maximum--
--data length. Transmission stops by '1' at stop input. If transmision finishes finished output becomes '1'. -----
--Fixed stuff input controls whenever fixed bitStuffing(after length bits of any value reverse bit is inserted) --
--'1' fixed stuff is used, '0' fixed stuff is not used. Fixed stuff for CRC of CAN FD Frames ---------------------
------------------------------------------------------------------------------------------------------------------
-- Revision History:
--
--------------------------------------------------------------------------------
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
--NOTE: Circuit is deprecated, simpler implementation without interal buffer was used!
entity bitStuffer is
--number of equal bits before sutff bit is inserted
generic (
length:natural:=5;
maxDataSize:natural:=512 --Maximal number of consecutive bits sent
);
port(
--INPUTS
signal data_in : in std_logic; --serial data input
signal clk_sys : in std_logic; --System clock
signal clk_nbt : in std_logic; --Nominal bit time clock
signal clk_dbt : in std_logic; --Data bit time clock
signal start : in std_logic; --Logic '1' starts bit stuffing when rising edge on clk_sys and bs_trig_XXX is active
signal data_size : in std_logic_vector (11 downto 0); --must be valid data size to be transmitted when start='1'
signal fixed_stuff : in std_logic; --fixed stuff insert stuffed bit after 'length' bits even if they are not the same value
signal stop : in std_logic; --stops the bit stuffing when 1 is present
signal res_n : in std_logic; --reset (active in '0')
signal bt_type : in std_logic; --Bit time type, if either clk_nbt or clk_dbt is considered as bit time for transcieving
signal bs_trig_nbt : in std_logic; --Trigger signal from prescaler to sample inpu value and propagate or bit stuff
signal bs_trig_dbt : in std_logic; --Trigger signal from prescaler to sample inpu value and propagate or bit stuff
--OUTPUTS
signal data_out : out std_logic; --serial data output
signal finished : out std_logic; --signalizing all data are stuffed
signal valid : out std_logic; --data_out is valid (not valid when stuffing finished,stopped or error)
signal error : out std_logic; --error occurs when input dataSize is bigger than data_buffer size
signal data_rem : out std_logic_vector (11 downto 0); --amount of bits remaining to be transmitted
signal is_stuffed : out std_logic --logic 1 if actual bit is stuffed;
);
--STATE MACHINE OF BIT STUFFER
type stuffing_state is (waiting_s,running_s,stopped_s,finished_s,error_s);
signal state:stuffing_state:=waiting_s;
--DATA BUFFER
signal data_buffer:std_logic_vector(maxDataSize/length downto 0); --maxDataSize/length the worst case, most stuffed bits
--Pointer for position in data_buffer where to add incoming data
signal buffer_pointer:natural:=0;
--Number of following bits that is already with the same value
signal same_bits:natural := 0;
--Value of last bit
signal last_bit:std_logic :='0';
--Remaining data counter
signal data_remaining : std_logic_vector (11 downto 0); --amount of bits remaining to be transmitted
end entity;
architecture rtl of bitStuffer is
begin
data_rem<=data_remaining;
state_machine:process(clk_sys)
variable data_buffer_var:std_logic_vector(maxDataSize/length downto 0);
begin
if(res_n='0')then
state<=waiting_s;
elsif rising_edge(clk_sys) then
--State machine Handling
case state is
when waiting_s =>
if(start='1')and
((bs_trig_nbt='1' and bt_type='0')or
(bs_trig_dbt='1' and bt_type='1'))then
if(data_size>std_logic_vector(to_unsigned(maxDataSize,11)))then
state<=error_s;
else
finished<='0';
error<='0';
valid<='1';
data_remaining<=data_size;
same_bits<=1;
data_buffer<=(OTHERS =>'0');
data_out<=data_in; --First bit is sent directly
last_bit<=data_in;
buffer_pointer<=0;
state<=running_s;
end if;
end if;
when running_s =>
if(bs_trig_nbt='1' and bt_type='0')or
(bs_trig_dbt='1' and bt_type='1')then
--Last bit assignment
if(buffer_pointer=0)then
last_bit<=data_in;
else
last_bit<=data_buffer(0);
end if;
--Incresing number of same bits
--and nulling number of same bits when other bit appears!
--If stuffing just began ,no data in buffer, last_bit is
--compared with data_in, otherwise it is compared with
--actual transcieved data!
if(buffer_pointer=0)then
--If no data are stored in buffer
if((last_bit=data_in) OR (fixed_stuff='1'))then
same_bits<=same_bits+1;
end if;
if((fixed_stuff='0') AND (NOT(last_bit=data_in)))then
same_bits<=1;
end if;
else
--If data are stored in Buffer
if((last_bit=data_buffer(0)) OR (fixed_stuff='1'))then
same_bits<=same_bits+1;
end if;
if((fixed_stuff='0') AND (NOT(last_bit=data_buffer(0))))then
same_bits<=1;
end if;
end if;
--Number of equal bits reached the length
if(same_bits=length)then
data_buffer(buffer_pointer)<=data_in;
buffer_pointer<=buffer_pointer+1;
data_out<=not last_bit;
same_bits<=0;
else
--decreasing remaining data
data_remaining<=std_logic_vector(unsigned(data_remaining)-1);
valid<='1';
if(buffer_pointer=0)then
data_out<=data_in;
else
--Shifting data buffer and storing input data into this position
data_buffer_var:=data_buffer;
data_buffer_var(buffer_pointer):=data_in;
data_buffer_var:='0'&data_buffer_var(maxDataSize/length downto 1);
data_buffer<=data_buffer_var;
data_out<=data_buffer(0);
end if;
end if;
--All the data are sent go to finished state
if(unsigned(data_remaining)=1)then
state<=finished_s;
finished<='1';
valid<='0';
end if;
--If stop is active go to stop state
if(stop='1')then
state<=stopped_s;
end if;
end if;
when stopped_s =>
valid<='0';
state<=waiting_s;
when finished_s =>
state<=waiting_s;
when error_s=>
valid<='0';
error<='1';
state<=waiting_s;
when others =>
end case;
end if;
end process;
end architecture;
\ No newline at end of file
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com>
--
-- Project advisors and co-authors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
-- Martin Jerabek <jerabma7@fel.cvut.cz>
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--Time stamp generator generates 2xtime stamp value from source clock signal
--(either sys_clock,clk_tq_nbt,clk_tq_dbt,clk_nbt,clk_dbt)
--This component originally intended as internal component of CAN controller!
--Not Used anymore, tsGen used instead on system level.
--Therefore all controllers in the system share the same TimeStamp Generator
--NOTE: DRIVING BUS SIGNALS controlling this circuit were deleted!
--------------------------------------------------------------------------------
-- Revision History:
--
--------------------------------------------------------------------------------
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE ieee.math_real.ALL;
entity timeStampGen is
port(
----------
--INPUTS--
----------
--Source clock signals
signal clk_sys: in std_logic; --System clock
signal clk_tq_nbt :in std_logic; --NBT time quantum clock
signal clk_tq_dbt :in std_logic; --DBT time qunatum clock
signal clk_nbt :in std_logic; --NBT Bit time clock
signal clk_dbt :in std_logic; --DBT Bit time clock
signal res_n:in std_logic; --Async reset
--Driving bus from user registers
signal drv_bus:in std_logic_vector(1023 downto 0);
----------
--OUTPUTS-
----------
--TimeStamp counter values
signal ts_1:out std_logic_vector(49 downto 0);
signal ts_2:out std_logic_vector(49 downto 0);
--TimeStamp registers output
signal ts_reg:out std_logic_vector(199 downto 0)
);
-------------------
--INTERNAL SIGNALS-
-------------------
--TimeStamp counter Registers
signal ts_1_value:std_logic_vector(49 downto 0):=(OTHERS=>'0');
signal ts_2_value:std_logic_vector(49 downto 0):=(OTHERS=>'0');
--Stamped values registers
signal ts_A_reg:std_logic_vector(49 downto 0):=(OTHERS=>'0');
signal ts_B_reg:std_logic_vector(49 downto 0):=(OTHERS=>'0');
signal ts_C_reg:std_logic_vector(49 downto 0):=(OTHERS=>'0');
signal ts_D_reg:std_logic_vector(49 downto 0):=(OTHERS=>'0');
--Driving signals aliases
signal drv_ts_1_src:std_logic_vector(2 downto 0); --Source of ts_1 counter
signal drv_ts_1_rst:std_logic; --Reset of counter 1;
signal drv_ts_1_make:std_logic_vector(3 downto 0); --Log the data of ts_1
signal drv_ts_2_src:std_logic_vector(2 downto 0); --Source of ts_1 counter
signal drv_ts_2_rst:std_logic; --Reset of counter 1;
signal drv_ts_2_make:std_logic_vector(3 downto 0); --Log the data of ts_1
--Registers for previous values of clock inputs
signal r_clk_tq_nbt :std_logic;
signal r_clk_tq_dbt :std_logic;
signal r_clk_nbt :std_logic;
signal r_clk_dbt :std_logic;
end entity;
architecture rtl of timeStampGen is
begin
--Outputs
ts_1<=ts_1_value;
ts_2<=ts_2_value;
ts_reg<=ts_D_reg&ts_C_reg&ts_B_reg&ts_A_reg;
--Driving signals aliases
--Note: If this circuit is to be used following driving signals have to be assigned (or put as input control signals)
drv_ts_1_src<=(OTHERS=>'0');
drv_ts_1_rst<='0';
drv_ts_1_make<=(OTHERS=>'0');
drv_ts_2_src<=(OTHERS=>'0');
drv_ts_2_rst<='0';
drv_ts_2_make<=(OTHERS=>'0');
--CLK_SYS process Async reset, Sync Reset, and counter driving
clk_sys_proc:process(clk_sys)
begin
if(res_n='0')then
ts_1_value<=(OTHERS=>'0');
ts_2_value<=(OTHERS=>'0');
ts_A_reg<=(OTHERS=>'0');
ts_B_reg<=(OTHERS=>'0');
ts_C_reg<=(OTHERS=>'0');
ts_D_reg<=(OTHERS=>'0');
r_clk_tq_nbt<='0';
r_clk_tq_dbt<='0';
r_clk_nbt<='0';
r_clk_dbt<='0';
elsif rising_edge(clk_sys)then
--Detecting rising edges on other clocks than clk_sys still synchronous to clk_sys
r_clk_tq_nbt<=clk_tq_nbt;
r_clk_tq_dbt<=clk_tq_dbt;
r_clk_nbt<=clk_nbt;
r_clk_dbt<=r_clk_dbt;
--Counter 1 erase or increment
if(drv_ts_1_rst='1')then
ts_1_value<=(OTHERS =>'0');
elsif ((drv_ts_1_src="0000") or --clk_sys is source clock for timeStamp 1
((drv_ts_1_src="0001") and (clk_tq_nbt='1') and r_clk_tq_nbt='0') or --clk_tq_nbt is source clock for timeStamp 1
((drv_ts_1_src="0010") and (clk_tq_dbt='1') and r_clk_tq_dbt='0') or --clk_tq_dbt is source clock for timeStamp 1
((drv_ts_1_src="0011") and (clk_nbt='1') and r_clk_nbt='0') or --clk_nbt is source clock for timeStamp 1
((drv_ts_1_src="0100") and (clk_dbt='1') and r_clk_dbt='0')) --clk_dbt is source clock for timeStamp 1
then
ts_1_value<=std_logic_vector(unsigned(ts_1_value)+1);
else
ts_1_value<=ts_1_value;
end if;
--Counter 2 erase or increment
if(drv_ts_2_rst='1')then
ts_2_value<=(OTHERS =>'0');
elsif ((drv_ts_2_src="0000") or --clk_sys is source clock for timeStamp 2
((drv_ts_2_src="0001") and (clk_tq_nbt='1') and r_clk_tq_nbt='0') or --clk_tq_nbt is source clock for timeStamp 2
((drv_ts_2_src="0010") and (clk_tq_dbt='1') and r_clk_tq_dbt='0') or --clk_tq_dbt is source clock for timeStamp 2
((drv_ts_2_src="0011") and (clk_nbt='1') and r_clk_nbt='0') or --clk_nbt is source clock for timeStamp 2
((drv_ts_2_src="0100") and (clk_dbt='1') and r_clk_dbt='0')) --clk_dbt is source clock for timeStamp 2
then
ts_2_value<=std_logic_vector(unsigned(ts_2_value)+1);
else
ts_2_value<=ts_2_value;
end if;
--Saving time from timeStamps into registers
if(drv_ts_1_make(0)='1')then
ts_A_reg<=ts_1_value;
elsif (drv_ts_2_make(0)='1') then
ts_A_reg<=ts_2_value;
else
ts_A_reg<=ts_A_reg;
end if;
if(drv_ts_1_make(1)='1')then
ts_B_reg<=ts_1_value;
elsif (drv_ts_2_make(1)='1') then
ts_B_reg<=ts_2_value;
else
ts_B_reg<=ts_B_reg;
end if;
if(drv_ts_1_make(2)='1')then
ts_C_reg<=ts_1_value;
elsif (drv_ts_2_make(2)='1') then
ts_C_reg<=ts_2_value;
else
ts_C_reg<=ts_C_reg;
end if;
if(drv_ts_1_make(3)='1')then
ts_D_reg<=ts_1_value;
elsif (drv_ts_2_make(3)='1') then
ts_D_reg<=ts_2_value;
else
ts_D_reg<=ts_D_reg;
end if;
end if;
end process clk_sys_proc;
end architecture;
\ No newline at end of file
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com>
--
-- Project advisors and co-authors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
-- Martin Jerabek <jerabma7@fel.cvut.cz>
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Revision History:
--
--------------------------------------------------------------------------------
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE ieee.math_real.ALL;
use work.CANconstants.all;
entity txBuffer is
GENERIC (
buff_size:natural:=32 --Only powers of 2 allowed as buff_size!! (32,64,128,256)
);
PORT(
-------------------
--Clock and Reset--
-------------------
signal clk_sys:in std_logic; --System clock
signal res_n:in std_logic; --Async Reset
-------------------------------
--Driving registers inferface--
-------------------------------
signal drv_bus:in std_logic_vector(1023 downto 0); --Driving bus from registers
signal tran_data_in:in std_logic_vector(639 downto 0); --Transcieve data
---------------------------
--TX Arbitrator interface--
---------------------------
signal tx_buffer_out: out std_logic_vector(639 downto 0); --Output frame with TX buffer structure
signal tx_buffer_valid:out std_logic; --Valid data on the output of TX Buffer
signal tx_buffer_ack:in std_logic; --Acknowledge from TX Arbitrator that message was loaded into CAN Core and can be erased
-------------------
--Status signals --
-------------------
signal tx_buff_size:out std_logic_vector(7 downto 0); --Size of transcieve Buffer in 32 bit words
signal tx_full: out std_logic; --Trascieve buffer is full
signal tx_message_count :out std_logic_vector(7 downto 0); --Number of messages in the TX buffer
signal tx_empty:out std_logic; --Buffer empty;
signal tx_mem_free:out std_logic_vector (7 downto 0); --Number of free words in TX counter
signal tx_read_pointer_pos: out std_logic_vector(7 downto 0); --Read pointer value propagated
signal tx_write_pointer_pos: out std_logic_vector(7 downto 0); --Write pointer value propagated
signal tx_message_disc:out std_logic --Signal that acutal message was discarded and not stored for transcieving
);
-----------------------
--Driving bus aliases--
-----------------------
signal drv_erase_tx: std_logic; --Logic 1 Erases the data in transcieve buffer
signal drv_write_tx: std_logic; --Logic 1 Stores the value on tran_data_in into the buffer (Format A Message format)
----------------
--FIFO Memory --
----------------
constant data_width:natural:=32;
type tx_memory is array (0 to buff_size-1) of std_logic_vector(data_width-1 downto 0); --TX Buffer memory type
signal memory:tx_memory; --Memory declaration
signal read_pointer : natural range 0 to buff_size-1; --Read Pointer for data
signal write_pointer : natural range 0 to buff_size-1; --Write pointer
signal prev_store:std_logic; --Previous value of store signal. Used for edge detection of drv_store_tx
--Note: by write in user registers, the drv_store_tx can be in logic one for more cycles (depending on length of write cycle). In order
-- not to store the data into the buffer more times, edge detection has to be performed!
--Note 2: Every command of write into the the buffer has to be separate write command and have the edge on drv_store_tx. Otherwise data will
-- be stored just oonce!
end entity;
architecture rtl of txBuffer is
begin
--Driving bus aliases
drv_erase_tx<=drv_bus(DRV_ERASE_TXT1_INDEX);
drv_write_tx<=drv_bus(DRV_STORE_TXT1_INDEX);
--Registers to output propagation
tx_read_pointer_pos<=std_logic_vector(to_unsigned(read_pointer,8)); --Output information about pointer position
tx_write_pointer_pos<=std_logic_vector(to_unsigned(write_pointer,8));
tx_buff_size<=std_logic_vector(to_unsigned(buff_size,8)); --Buffer size to output
mem_acess:process(res_n,clk_sys)
variable data_length_read:natural range 0 to 16;
variable data_length_write:natural range 0 to 16;
variable mem_free:natural range 0 to buff_size;
variable message_count:natural range 0 to 255;
begin
if(res_n=ACT_RESET) or (drv_erase_tx='1')then
read_pointer<=0;
write_pointer<=0;
memory<=(OTHERS=>(OTHERS=>'0'));
data_length_read:=0;
data_length_write:=0;
mem_free:=buff_size;
message_count:=0;
prev_store<='0';
tx_full<='0';
tx_message_count<=(OTHERS=>'0');
tx_empty<='1';
tx_mem_free<=std_logic_vector(to_unsigned(buff_size,8));
tx_message_disc<='0';
tx_buffer_out<=(OTHERS=>'0');
tx_buffer_valid<='0';
elsif rising_edge(clk_sys) then
prev_store<=drv_write_tx; --Registering the value for edge detection
--Data length encoding, data_length=number of bytes/4 (FIFO is 32 bits)
case memory(read_pointer)(3 downto 0) is
when "0000" => data_length_read:=0;
when "0001" => data_length_read:=1;
when "0010" => data_length_read:=1;
when "0011" => data_length_read:=1;
when "0100" => data_length_read:=1;
when "0101" => data_length_read:=2;
when "0110" => data_length_read:=2;
when "0111" => data_length_read:=2;
when "1000" => data_length_read:=2;
when "1001" => data_length_read:=3;
when "1010" => data_length_read:=4;
when "1011" => data_length_read:=5;
when "1100" => data_length_read:=6;
when "1101" => data_length_read:=8;
when "1110" => data_length_read:=12;
when "1111" => data_length_read:=16;
when others => data_length_read:=0;
end case;
--Oldest message to the TX Arbitrator
if(message_count>0)then
tx_buffer_valid<='1';