Commit ff4090c0 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch '184-fixup-time-transmission-feauture-test' into 'master'

Resolve "Fixup Time transmission feauture test"

Closes #184

See merge request illeondr/CAN_FD_IP_Core!152
parents 924e6a00 ac9fa01a
Pipeline #2066 passed with stages
in 5 minutes and 56 seconds
......@@ -110,6 +110,11 @@ package body tx_arb_time_tran_feature is
o.outcome := true;
------------------------------------------------------------------------
-- Wait until unit for sure comes out of integration.
------------------------------------------------------------------------
wait_rand_cycles(rand_ctr, mem_bus(1).clk_sys, 1600, 1601);
------------------------------------------------------------------------
-- Part 1
------------------------------------------------------------------------
......@@ -147,11 +152,13 @@ package body tx_arb_time_tran_feature is
aux2 := to_integer(unsigned(CAN_frame.timestamp(31 downto 0)));
------------------------------------------------------------------------
-- We tolerate up to 150 clock cycles between actual timestamp and
-- transmitt time. This fits to the default setting of up to 130 clock
-- cycles per bit time!
-- We tolerate up to 190 clock cycles between actual timestamp and
-- transmitt time. Default time settings have 140 clock cycles per Bit
-- Time. There is up to 40 clock cycles of storing CAN frame. 6 clock
-- cycles are delay of TX Arbitrator! This gives possible delay
-- of 186 clock cycles. Let's take 190 to have some reserve!
------------------------------------------------------------------------
if (aux1 - aux2 > 150) then
if (aux1 - aux2 > 190) then
-- LCOV_EXCL_START
o.outcome := false;
report "Frame not sent at time when expected!" severity error;
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment