Commit fec36762 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Code formatting 1

parent e54237d1
......@@ -5,7 +5,7 @@ USE ieee.std_logic_unsigned.All;
USE WORK.CANconstants.ALL;
use work.CANcomponents.ALL;
-------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--
-- CAN with Flexible Data-Rate IP Core
--
......@@ -30,15 +30,17 @@ use work.CANcomponents.ALL;
-- Revision History:
--
-- July 2015 Created file
-- 22.6.2016 1. Added rec_esi signal for error state propagation into the RX buffer.
-- 2. Added explicit architecture selection for each component (RTL)
-- 22.6.2016 1. Added rec_esi signal for error state propagation into
-- RX buffer.
-- 2. Added explicit architecture selection for each component
-- (RTL)
-- 24.8.2016 Added "use_logger" generic to the registers module.
-- 28.11.2017 Added "rst_sync_comp" reset synchroniser.
-- 30.11.2017 Changed TXT buffer to registers interface. The user is now directly accessing the buffer
-- by avalon access.
-------------------------------------------------------------------------------------------------------------
-- 30.11.2017 Changed TXT buffer to registers interface. The user is now
-- directly accessing the buffer by avalon access.
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Enity encapsulating all functionality of CAN FD node.
-- Instances:
......@@ -51,554 +53,749 @@ use work.CANcomponents.ALL;
-- 2x TXT buffer
-- 1x Tx Arbitrator
-- 1x Acceptance filters
------------------------------------------------------------
--------------------------------------------------------------------------------
entity CAN_top_level is
generic(
constant use_logger : boolean :=true; --Whenever event logger should be synthetised
constant rx_buffer_size : natural range 4 to 512 :=128; --Transcieve Buffer size
constant useFDSize : boolean :=true; --Transcieve buffer size should be synthetised as FD Size (640 bits) or normal CAN (128 bits)
constant use_sync : boolean :=true; --Whenever internal synchroniser chain should be used for incoming bus signals
--Dont turn off unless external synchronisation chain is put on input of FPGA by
--synthetiser
constant ID : natural range 0 to 15:=1; --ID (bits 19-16 of adress)
constant sup_filtA : boolean := true; --Optional synthesis of received message filters
constant sup_filtB : boolean := true; -- By default the behaviour is as if all the filters are present
constant sup_filtC : boolean := true;
constant sup_range : boolean := true;
constant logger_size : natural range 0 to 512:=8
);
port(
--------------------------
--System clock and reset--
--------------------------
signal clk_sys :in std_logic;
signal res_n :in std_logic;
---------------------
--Memory interface --
---------------------
signal data_in :in std_logic_vector(31 downto 0);
signal data_out :out std_logic_vector(31 downto 0);
signal adress :in std_logic_vector(23 downto 0);
signal scs :in std_logic; --Chip select
signal srd :in std_logic; --Serial read
signal swr :in std_logic; --Serial write
--Note: This bus is Avalon compatible!
--------------------
--Interrupt output--
--------------------
signal int :out std_logic;
-------------------
--CAN Bus output --
-------------------
signal CAN_tx :out std_logic;
signal CAN_rx :in std_logic;
---------------------------
--Synchronisation signals--
---------------------------
signal time_quanta_clk :out std_logic; --Time Quantum clocks possible to be used for synchronisation
-------------------------------------------
--Timestamp value for time based messages--
-------------------------------------------
signal timestamp :in std_logic_vector(63 downto 0)
);
---------------------
--Internal signals --
---------------------
signal res_n_int : std_logic; -- Overal reset (External+Reset by memory access)
signal res_n_sync : std_logic; -- Synchronised reset
signal drv_bus : std_logic_vector(1023 downto 0);
signal stat_bus : std_logic_vector(511 downto 0);
signal int_vector : std_logic_vector(10 downto 0); --Interrupt vector (Interrupt register of SJA1000)
--Registers <--> RX Buffer Interface
signal rx_read_buff : std_logic_vector(31 downto 0); --Actually loaded data for reading
signal rx_buf_size : std_logic_vector(7 downto 0); --Actual size of synthetised message buffer (in 32 bit words)
signal rx_full : std_logic; --Signal whenever buffer is full
signal rx_empty : std_logic; --Signal whenever buffer is empty
signal rx_message_count : std_logic_vector(7 downto 0); --Number of messaged stored in recieve buffer
signal rx_mem_free : std_logic_vector(7 downto 0); --Number of free 32 bit wide ''windows''
signal rx_read_pointer_pos : std_logic_vector(7 downto 0); --Position of read pointer
signal rx_write_pointer_pos : std_logic_vector(7 downto 0); --Position of write pointer
signal rx_message_disc : std_logic; --Message was discarded since Memory is full
signal rx_data_overrun : std_logic; --Some data were discarded, register
--Registers <--> TX Buffer, TXT Buffer
signal tran_data_in : std_logic_vector(639 downto 0); --Transcieve data (Common for TX Buffer and TXT Buffer)
signal txt1_disc : std_logic; --Info that message store into buffer from driving registers failed because buffer is full
signal txt2_disc : std_logic; --Info that message store into buffer from driving registers failed because buffer is full
signal tran_data : std_logic_vector(31 downto 0); --Data into the RAM of TXT Buffer
signal tran_addr : std_logic_vector(4 downto 0); --Address in the RAM of TXT buffer
--Registers <--> event logger
signal loger_act_data : std_logic_vector(63 downto 0);
signal log_write_pointer : std_logic_vector(7 downto 0);
signal log_read_pointer : std_logic_vector(7 downto 0);
signal log_size : std_logic_vector(7 downto 0);
signal log_state_out : logger_state_type;
-- Whenever event logger should be synthetised
constant use_logger : boolean := true;
--TX Arbitrator <--> TX Buffer, TXT Buffer
signal txt1_buffer_ack : std_logic; --Time buffer acknowledge that message can be erased
signal txt1_buffer_empty : std_logic; --No message in Time TX Buffer
signal txt2_buffer_ack : std_logic; --Time buffer acknowledge that message can be erased
signal txt2_buffer_empty : std_logic; --No message in Time TX Buffer
signal txt1_data_word : std_logic_vector(31 downto 0);
signal txt1_frame_info : std_logic_vector(127 downto 0);
signal txt2_data_word : std_logic_vector(31 downto 0);
signal txt2_frame_info : std_logic_vector(127 downto 0);
--TX Arbitrator <--> CAN Core
signal tran_data_out : std_logic_vector(31 downto 0); --TX Message data
signal tran_ident_out : std_logic_vector(28 downto 0); --TX Identifier
signal tran_dlc_out : std_logic_vector(3 downto 0); --TX Data length code
signal tran_is_rtr : std_logic; --TX is remote frame
signal tran_ident_type_out : std_logic; --TX Identifier type (0-Basic,1-Extended);
signal tran_frame_type_out : std_logic; --TX Frame type
signal tran_brs_out : std_logic; --Bit rate shift for CAN FD frames
signal tran_frame_valid_out : std_logic; --Signal for CAN Core that frame on the output is valid and can be stored for transmitting
signal tran_data_ack : std_logic; --Acknowledge from CAN core that acutal message was stored into internal buffer for transmitting
signal txt_buf_ptr : natural range 0 to 15; --Pointer to TXT buffer memory
--RX Buffer <--> CAN Core
signal rec_ident_in : std_logic_vector(28 downto 0); --Message Identifier
signal rec_data_in : std_logic_vector(511 downto 0); --Message Data (up to 64 bytes);
signal rec_dlc_in : std_logic_vector(3 downto 0); --Data length code
signal rec_ident_type_in : std_logic; --Recieved identifier type (0-BASE Format, 1-Extended Format);
signal rec_frame_type_in : std_logic; --Recieved frame type (0-Normal CAN, 1- CAN FD)
signal rec_is_rtr : std_logic; --Recieved frame is RTR Frame(0-No, 1-Yes)
signal rec_message_valid : std_logic;
signal rec_brs : std_logic; --Whenever frame was recieved with BIT Rate shift
signal rec_message_ack : std_logic; --Acknowledge for CAN Core about accepted data
signal rec_esi : std_logic;
signal rec_dram_word : std_logic_vector(31 downto 0);
signal rec_dram_addr : natural range 0 to 15;
--RX Buffer <--> Message filters
signal out_ident_valid : std_logic; --Signal whenever identifier matches the filter identifiers
--Interrupt manager <--> CAN Core
signal error_valid : std_logic; --Valid Error appeared for interrupt
signal error_passive_changed: std_logic; --Error pasive /Error acitve functionality changed
signal error_warning_limit : std_logic; --Error warning limit reached
signal arbitration_lost : std_logic; --Arbitration was lost input
signal wake_up_valid : std_logic; --Wake up appeared
signal tx_finished : std_logic; --Message stored in CAN Core was sucessfully transmitted
signal br_shifted : std_logic; --Bit Rate Was Shifted
signal loger_finished : std_logic; --Event logging finsihed
--Prescaler <--> CAN Core
signal sync_edge : std_logic; --Edge for synchronisation
signal OP_State : oper_mode_type; --Protocol control state
-- Receive Buffer size
constant rx_buffer_size : natural range 4 to 512 := 128;
signal clk_tq_nbt : std_logic; --Time quantum clock - Nominal bit time
signal clk_tq_dbt : std_logic; --bit time - Nominal bit time
-- Transcieve buffer size should be synthetised as FD Size (640 bits)
-- or normal CAN (128 bits)
constant useFDSize : boolean := true;
signal sample_nbt : std_logic; --Sample signal for nominal bit time
signal sample_dbt : std_logic; --Sample signal of data bit time
signal sample_nbt_del_1 : std_logic;
signal sample_dbt_del_1 : std_logic;
signal sample_nbt_del_2 : std_logic;
signal sample_dbt_del_2 : std_logic;
-- Whenever internal synchroniser chain should be used for incoming bus
-- signals. Dont turn off unless external synchronisation chain is put on
-- input of FPGA by synthetiser
constant use_sync : boolean := true;
signal sync_nbt : std_logic;
signal sync_dbt : std_logic;
signal sync_nbt_del_1 : std_logic;
signal sync_dbt_del_1 : std_logic;
signal sp_control : std_logic_vector(1 downto 0);
signal sync_control : std_logic_vector(1 downto 0);
signal bt_FSM_out : bit_time_type;
signal hard_sync_edge_valid : std_logic; --Validated hard synchronisation edge to start Protocol control FSM
--Note: Sync edge from busSync.vhd cant be used! If it comes during sample nbt, sequence it causes
-- errors! It needs to be strictly before or strictly after this sequence!!!
--Bus Synchroniser
signal data_tx : std_logic; --Transcieve data value
signal data_rx : std_logic; --Recieved data value
signal ssp_reset : std_logic; --Clear the Shift register at the beginning of Data Phase!!!
signal trv_delay_calib : std_logic; --Calibration command for transciever delay compenstation (counter)
signal bit_Error_sec_sam : std_logic; --Bit error with secondary sampling transciever!
-- ID (bits 19-16 of adress)
constant ID : natural range 0 to 15 := 1;
signal sample_sec : std_logic; --Secondary sample signal
signal sample_sec_del_1 : std_logic; --Bit destuffing trigger for secondary sample point
signal sample_sec_del_2 : std_logic; --Rec trig for secondary sample point
-- Optional synthesis of received message filters
-- By default the behaviour is as if all the filters are present
constant sup_filtA : boolean := true;
constant sup_filtB : boolean := true;
constant sup_filtC : boolean := true;
constant sup_range : boolean := true;
constant logger_size : natural range 0 to 512 := 8
);
port(
--------------------------
-- System clock and reset
--------------------------
signal clk_sys : in std_logic;
signal res_n : in std_logic;
---------------------
-- Memory interface
---------------------
signal data_in : in std_logic_vector(31 downto 0);
signal data_out : out std_logic_vector(31 downto 0);
signal adress : in std_logic_vector(23 downto 0);
signal scs : in std_logic; --Chip select
signal srd : in std_logic; --Serial read
signal swr : in std_logic; --Serial write
--Note: This bus is Avalon compatible!
--------------------
-- Interrupt output
--------------------
signal int : out std_logic;
-------------------
-- CAN Bus output
-------------------
signal CAN_tx : out std_logic;
signal CAN_rx : in std_logic;
---------------------------
-- Synchronisation signals
---------------------------
--Time Quantum clocks possible to be used for synchronisation
signal time_quanta_clk : out std_logic;
-------------------------------------------
-- Timestamp value for time based messages
-------------------------------------------
signal timestamp : in std_logic_vector(63 downto 0)
);
------------------------------------------------------------------------------
------------------------------------------------------------------------------
---- Internal signals
------------------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Common control signals
------------------------------------------------------------------------------
-- Overal reset (External+Reset by memory access)
signal res_n_int : std_logic;
signal res_n_sync : std_logic; -- Synchronised reset
signal drv_bus : std_logic_vector(1023 downto 0);
signal stat_bus : std_logic_vector(511 downto 0);
--Interrupt vector (Interrupt register of SJA1000)
signal int_vector : std_logic_vector(10 downto 0);
------------------------------------------------------------------------------
-- Registers <--> RX Buffer Interface
------------------------------------------------------------------------------
--Actually loaded data for reading
signal rx_read_buff : std_logic_vector(31 downto 0);
--Actual size of synthetised message buffer (in 32 bit words)
signal rx_buf_size : std_logic_vector(7 downto 0);
--Signal whenever buffer is full
signal rx_full : std_logic;
--Signal whenever buffer is empty
signal rx_empty : std_logic;
--Number of messaged stored in recieve buffer
signal rx_message_count : std_logic_vector(7 downto 0);
--Number of free 32 bit wide ''windows''
signal rx_mem_free : std_logic_vector(7 downto 0);
--Position of read pointer
signal rx_read_pointer_pos : std_logic_vector(7 downto 0);
--Position of write pointer
signal rx_write_pointer_pos : std_logic_vector(7 downto 0);
--Message was discarded since Memory is full
signal rx_message_disc : std_logic;
--Some data were discarded, register
signal rx_data_overrun : std_logic;
------------------------------------------------------------------------------
-- Registers <--> TX Buffer, TXT Buffer
------------------------------------------------------------------------------
--Transcieve data (Common for TX Buffer and TXT Buffer)
signal tran_data_in : std_logic_vector(639 downto 0);
--Info that message store into buffer from driving registers failed
--because buffer is full
signal txt1_disc : std_logic;
--Info that message store into buffer from driving registers failed
--because buffer is full
signal txt2_disc : std_logic;
--Data into the RAM of TXT Buffer
signal tran_data : std_logic_vector(31 downto 0);
--Address in the RAM of TXT buffer
signal tran_addr : std_logic_vector(4 downto 0);
------------------------------------------------------------------------------
-- Registers <--> event logger
------------------------------------------------------------------------------
signal loger_act_data : std_logic_vector(63 downto 0);
signal log_write_pointer : std_logic_vector(7 downto 0);
signal log_read_pointer : std_logic_vector(7 downto 0);
signal log_size : std_logic_vector(7 downto 0);
signal log_state_out : logger_state_type;
------------------------------------------------------------------------------
--TX Arbitrator <--> TX Buffer, TXT Buffer
------------------------------------------------------------------------------
--Time buffer acknowledge that message can be erased
signal txt1_buffer_ack : std_logic;
--No message in Time TX Buffer
signal txt1_buffer_empty : std_logic;
--Time buffer acknowledge that message can be erased
signal txt2_buffer_ack : std_logic;
--No message in Time TX Buffer
signal txt2_buffer_empty : std_logic;
signal txt1_data_word : std_logic_vector(31 downto 0);
signal txt1_frame_info : std_logic_vector(127 downto 0);
signal txt2_data_word : std_logic_vector(31 downto 0);
signal txt2_frame_info : std_logic_vector(127 downto 0);
------------------------------------------------------------------------------
-- TX Arbitrator <--> CAN Core
------------------------------------------------------------------------------
--TX Message data
signal tran_data_out : std_logic_vector(31 downto 0);
--TX Identifier
signal tran_ident_out : std_logic_vector(28 downto 0);
--TX Data length code
signal tran_dlc_out : std_logic_vector(3 downto 0);
--TX is remote frame
signal tran_is_rtr : std_logic;
--TX Identifier type (0-Basic,1-Extended);
signal tran_ident_type_out : std_logic;
--TX Frame type
signal tran_frame_type_out : std_logic;
--Bit rate shift for CAN FD frames
signal tran_brs_out : std_logic;
--Signal for CAN Core that frame on the output is valid and can be
--stored for transmitting
signal tran_frame_valid_out : std_logic;
--Acknowledge from CAN core that acutal message was stored into internal
--buffer for transmitting
signal tran_data_ack : std_logic;
--Pointer to TXT buffer memory
signal txt_buf_ptr : natural range 0 to 15;
------------------------------------------------------------------------------
--RX Buffer <--> CAN Core
------------------------------------------------------------------------------
--Message Identifier
signal rec_ident_in : std_logic_vector(28 downto 0);
--Message Data (up to 64 bytes);
signal rec_data_in : std_logic_vector(511 downto 0);
--Data length code
signal rec_dlc_in : std_logic_vector(3 downto 0);
--Recieved identifier type (0-BASE Format, 1-Extended Format);
signal rec_ident_type_in : std_logic;
--Recieved frame type (0-Normal CAN, 1- CAN FD)
signal rec_frame_type_in : std_logic;
--Recieved frame is RTR Frame(0-No, 1-Yes)
signal rec_is_rtr : std_logic;
--Frame is received properly
signal rec_message_valid : std_logic;
--Whenever frame was recieved with BIT Rate shift
signal rec_brs : std_logic;
--Acknowledge for CAN Core about accepted data
signal rec_message_ack : std_logic;
signal trv_delay_out : std_logic_vector(15 downto 0);
-- Received Error state indicator
signal rec_esi : std_logic;
-- Pointer to RX Ram in CAN Core and output word with the received data
signal rec_dram_word : std_logic_vector(31 downto 0);
signal rec_dram_addr : natural range 0 to 15;
------------------------------------------------------------------------------
-- RX Buffer <--> Message filters
------------------------------------------------------------------------------
--Signal whenever identifier matches the filter identifiers
signal out_ident_valid : std_logic;
------------------------------------------------------------------------------
-- Interrupt manager <--> CAN Core
------------------------------------------------------------------------------
--Valid Error appeared for interrupt
signal error_valid : std_logic;
--Error pasive /Error acitve functionality changed
signal error_passive_changed : std_logic;
--Error warning limit reached
signal error_warning_limit : std_logic;
--Arbitration was lost input
signal arbitration_lost : std_logic;
--Wake up appeared
signal wake_up_valid : std_logic;
--Message stored in CAN Core was sucessfully transmitted
signal tx_finished : std_logic;
--Bit Rate Was Shifted
signal br_shifted : std_logic;
--Event logging finsihed
signal loger_finished : std_logic;
------------------------------------------------------------------------------
-- Prescaler <--> CAN Core
------------------------------------------------------------------------------
--Edge for synchronisation
signal sync_edge : std_logic;
--Protocol control state
signal OP_State : oper_mode_type;
--Time quantum clock - Nominal bit time
signal clk_tq_nbt : std_logic;
--Bit time - Nominal bit time
signal clk_tq_dbt : std_logic;
--Sample signal for nominal bit time
signal sample_nbt : std_logic;
--Sample signal of data bit time
signal sample_dbt : std_logic;
--Delay sample signals by 1 or 2 clock cycle
signal sample_nbt_del_1 : std_logic;
signal sample_dbt_del_1 : std_logic;
signal sample_nbt_del_2 : std_logic;
signal sample_dbt_del_2 : std_logic;
-- Transmitt signals and delayed transmitt signals by 1 clock cycle
signal sync_nbt : std_logic;
signal sync_dbt : std_logic;
signal sync_nbt_del_1 : std_logic;
signal sync_dbt_del_1 : std_logic;
signal sp_control : std_logic_vector(1 downto 0);
signal sync_control : std_logic_vector(1 downto 0);
signal bt_FSM_out : bit_time_type;
--Validated hard synchronisation edge to start Protocol control FSM
signal hard_sync_edge_valid : std_logic;
--Note: Sync edge from busSync.vhd cant be used! If it comes during sample
-- nbt, sequence it causes errors! It needs to be strictly before or
-- strictly after this sequence!!!
------------------------------------------------------------------------------
-- Bus Synchroniser Interface
------------------------------------------------------------------------------
--Transcieve data value
signal data_tx : std_logic;
--Recieved data value
signal data_rx : std_logic;
--Clear the Shift register at the beginning of Data Phase!!!
signal ssp_reset : std_logic;
--Calibration command for transciever delay compenstation (counter)
signal trv_delay_calib : std_logic;
--Bit error with secondary sampling transciever!
signal bit_Error_sec_sam : std_logic;
--Secondary sample signal
signal sample_sec : std_logic;
--Bit destuffing trigger for secondary sample point
signal sample_sec_del_1 : std_logic;
--Rec trig for secondary sample point
signal sample_sec_del_2 : std_logic;
-- Transceiver delay output
signal trv_delay_out : std_logic_vector(15 downto 0);
end entity CAN_top_level;
architecture rtl of CAN_top_level is
----------------------------------------------------
--Defining explicit architectures for used entites
-- Defining explicit architectures for used entites
----------------------------------------------------
for reg_comp : registers use entity work.registers(rtl);
for rx_buf_comp : rxBuffer use entity work.rxBuffer(rtl);
for txt1_buf_comp : txtBuffer use entity work.txtBuffer(rtl);
for txt2_buf_comp : txtBuffer use entity work.txtBuffer(rtl);
for tx_arb_comp : txArbitrator use entity work.txArbitrator(rtl);
for mes_filt_comp : messageFilter use entity work.messageFilter(rtl);
for int_man_comp : intManager use entity work.intManager(rtl);
for core_top_comp : core_top use entity work.core_top(rtl);
for prescaler_comp : prescaler_v3 use entity work.prescaler_v3(rtl);
for bus_sync_comp : busSync use entity work.busSync(rtl);
for rst_sync_comp : rst_sync use entity work.rst_sync(rtl);
--for log_comp : CAN_logger use entity work.CAN_logger(rtl);
for reg_comp : registers use entity work.registers(rtl);
for rx_buf_comp : rxBuffer use entity work.rxBuffer(rtl);
for txt1_buf_comp : txtBuffer use entity work.txtBuffer(rtl);
for txt2_buf_comp : txtBuffer use entity work.txtBuffer(rtl);
for tx_arb_comp : txArbitrator use entity work.txArbitrator(rtl);
for mes_filt_comp : messageFilter use entity work.messageFilter(rtl);
for int_man_comp : intManager use entity work.intManager(rtl);
for core_top_comp : core_top use entity work.core_top(rtl);
for prescaler_comp : prescaler_v3 use entity work.prescaler_v3(rtl);
for bus_sync_comp : busSync use entity work.busSync(rtl);
for rst_sync_comp : rst_sync use entity work.rst_sync(rtl);
--for log_comp : CAN_logger use entity work.CAN_logger(rtl);
begin