diff --git a/src/CAN_top_level.vhd b/src/CAN_top_level.vhd index 4eb6f52658982ed8eadae8959e931a6e8582b005..ec1253d8239e2c9858d8ae440af3d51d7522b54e 100644 --- a/src/CAN_top_level.vhd +++ b/src/CAN_top_level.vhd @@ -5,7 +5,7 @@ USE ieee.std_logic_unsigned.All; USE WORK.CANconstants.ALL; use work.CANcomponents.ALL; -------------------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- -- -- CAN with Flexible Data-Rate IP Core -- @@ -30,15 +30,17 @@ use work.CANcomponents.ALL; -- Revision History: -- -- July 2015 Created file --- 22.6.2016 1. Added rec_esi signal for error state propagation into the RX buffer. --- 2. Added explicit architecture selection for each component (RTL) +-- 22.6.2016 1. Added rec_esi signal for error state propagation into +-- RX buffer. +-- 2. Added explicit architecture selection for each component +-- (RTL) -- 24.8.2016 Added "use_logger" generic to the registers module. -- 28.11.2017 Added "rst_sync_comp" reset synchroniser. --- 30.11.2017 Changed TXT buffer to registers interface. The user is now directly accessing the buffer --- by avalon access. -------------------------------------------------------------------------------------------------------------- +-- 30.11.2017 Changed TXT buffer to registers interface. The user is now +-- directly accessing the buffer by avalon access. +-------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- -- Purpose: -- Enity encapsulating all functionality of CAN FD node. -- Instances: @@ -51,554 +53,749 @@ use work.CANcomponents.ALL; -- 2x TXT buffer -- 1x Tx Arbitrator -- 1x Acceptance filters ------------------------------------------------------------- +-------------------------------------------------------------------------------- entity CAN_top_level is generic( - constant use_logger : boolean :=true; --Whenever event logger should be synthetised - constant rx_buffer_size : natural range 4 to 512 :=128; --Transcieve Buffer size - constant useFDSize : boolean :=true; --Transcieve buffer size should be synthetised as FD Size (640 bits) or normal CAN (128 bits) - constant use_sync : boolean :=true; --Whenever internal synchroniser chain should be used for incoming bus signals - --Dont turn off unless external synchronisation chain is put on input of FPGA by - --synthetiser - constant ID : natural range 0 to 15:=1; --ID (bits 19-16 of adress) - constant sup_filtA : boolean := true; --Optional synthesis of received message filters - constant sup_filtB : boolean := true; -- By default the behaviour is as if all the filters are present - constant sup_filtC : boolean := true; - constant sup_range : boolean := true; - constant logger_size : natural range 0 to 512:=8 - ); - port( - -------------------------- - --System clock and reset-- - -------------------------- - signal clk_sys :in std_logic; - signal res_n :in std_logic; - - --------------------- - --Memory interface -- - --------------------- - signal data_in :in std_logic_vector(31 downto 0); - signal data_out :out std_logic_vector(31 downto 0); - signal adress :in std_logic_vector(23 downto 0); - signal scs :in std_logic; --Chip select - signal srd :in std_logic; --Serial read - signal swr :in std_logic; --Serial write - --Note: This bus is Avalon compatible! - - -------------------- - --Interrupt output-- - -------------------- - signal int :out std_logic; - - ------------------- - --CAN Bus output -- - ------------------- - signal CAN_tx :out std_logic; - signal CAN_rx :in std_logic; - - --------------------------- - --Synchronisation signals-- - --------------------------- - signal time_quanta_clk :out std_logic; --Time Quantum clocks possible to be used for synchronisation - - ------------------------------------------- - --Timestamp value for time based messages-- - ------------------------------------------- - signal timestamp :in std_logic_vector(63 downto 0) - ); - - --------------------- - --Internal signals -- - --------------------- - signal res_n_int : std_logic; -- Overal reset (External+Reset by memory access) - signal res_n_sync : std_logic; -- Synchronised reset - - signal drv_bus : std_logic_vector(1023 downto 0); - signal stat_bus : std_logic_vector(511 downto 0); - signal int_vector : std_logic_vector(10 downto 0); --Interrupt vector (Interrupt register of SJA1000) - - --Registers <--> RX Buffer Interface - signal rx_read_buff : std_logic_vector(31 downto 0); --Actually loaded data for reading - signal rx_buf_size : std_logic_vector(7 downto 0); --Actual size of synthetised message buffer (in 32 bit words) - signal rx_full : std_logic; --Signal whenever buffer is full - signal rx_empty : std_logic; --Signal whenever buffer is empty - signal rx_message_count : std_logic_vector(7 downto 0); --Number of messaged stored in recieve buffer - signal rx_mem_free : std_logic_vector(7 downto 0); --Number of free 32 bit wide ''windows'' - signal rx_read_pointer_pos : std_logic_vector(7 downto 0); --Position of read pointer - signal rx_write_pointer_pos : std_logic_vector(7 downto 0); --Position of write pointer - signal rx_message_disc : std_logic; --Message was discarded since Memory is full - signal rx_data_overrun : std_logic; --Some data were discarded, register - - --Registers <--> TX Buffer, TXT Buffer - signal tran_data_in : std_logic_vector(639 downto 0); --Transcieve data (Common for TX Buffer and TXT Buffer) - signal txt1_disc : std_logic; --Info that message store into buffer from driving registers failed because buffer is full - signal txt2_disc : std_logic; --Info that message store into buffer from driving registers failed because buffer is full - signal tran_data : std_logic_vector(31 downto 0); --Data into the RAM of TXT Buffer - signal tran_addr : std_logic_vector(4 downto 0); --Address in the RAM of TXT buffer - - --Registers <--> event logger - signal loger_act_data : std_logic_vector(63 downto 0); - signal log_write_pointer : std_logic_vector(7 downto 0); - signal log_read_pointer : std_logic_vector(7 downto 0); - signal log_size : std_logic_vector(7 downto 0); - signal log_state_out : logger_state_type; + -- Whenever event logger should be synthetised + constant use_logger : boolean := true; - --TX Arbitrator <--> TX Buffer, TXT Buffer - signal txt1_buffer_ack : std_logic; --Time buffer acknowledge that message can be erased - signal txt1_buffer_empty : std_logic; --No message in Time TX Buffer - signal txt2_buffer_ack : std_logic; --Time buffer acknowledge that message can be erased - signal txt2_buffer_empty : std_logic; --No message in Time TX Buffer - - signal txt1_data_word : std_logic_vector(31 downto 0); - signal txt1_frame_info : std_logic_vector(127 downto 0); - signal txt2_data_word : std_logic_vector(31 downto 0); - signal txt2_frame_info : std_logic_vector(127 downto 0); - - --TX Arbitrator <--> CAN Core - signal tran_data_out : std_logic_vector(31 downto 0); --TX Message data - signal tran_ident_out : std_logic_vector(28 downto 0); --TX Identifier - signal tran_dlc_out : std_logic_vector(3 downto 0); --TX Data length code - signal tran_is_rtr : std_logic; --TX is remote frame - signal tran_ident_type_out : std_logic; --TX Identifier type (0-Basic,1-Extended); - signal tran_frame_type_out : std_logic; --TX Frame type - signal tran_brs_out : std_logic; --Bit rate shift for CAN FD frames - signal tran_frame_valid_out : std_logic; --Signal for CAN Core that frame on the output is valid and can be stored for transmitting - signal tran_data_ack : std_logic; --Acknowledge from CAN core that acutal message was stored into internal buffer for transmitting - signal txt_buf_ptr : natural range 0 to 15; --Pointer to TXT buffer memory - - --RX Buffer <--> CAN Core - signal rec_ident_in : std_logic_vector(28 downto 0); --Message Identifier - signal rec_data_in : std_logic_vector(511 downto 0); --Message Data (up to 64 bytes); - signal rec_dlc_in : std_logic_vector(3 downto 0); --Data length code - signal rec_ident_type_in : std_logic; --Recieved identifier type (0-BASE Format, 1-Extended Format); - signal rec_frame_type_in : std_logic; --Recieved frame type (0-Normal CAN, 1- CAN FD) - signal rec_is_rtr : std_logic; --Recieved frame is RTR Frame(0-No, 1-Yes) - signal rec_message_valid : std_logic; - signal rec_brs : std_logic; --Whenever frame was recieved with BIT Rate shift - signal rec_message_ack : std_logic; --Acknowledge for CAN Core about accepted data - signal rec_esi : std_logic; - - signal rec_dram_word : std_logic_vector(31 downto 0); - signal rec_dram_addr : natural range 0 to 15; - - - --RX Buffer <--> Message filters - signal out_ident_valid : std_logic; --Signal whenever identifier matches the filter identifiers - - --Interrupt manager <--> CAN Core - signal error_valid : std_logic; --Valid Error appeared for interrupt - signal error_passive_changed: std_logic; --Error pasive /Error acitve functionality changed - signal error_warning_limit : std_logic; --Error warning limit reached - signal arbitration_lost : std_logic; --Arbitration was lost input - signal wake_up_valid : std_logic; --Wake up appeared - signal tx_finished : std_logic; --Message stored in CAN Core was sucessfully transmitted - signal br_shifted : std_logic; --Bit Rate Was Shifted - - signal loger_finished : std_logic; --Event logging finsihed - --Prescaler <--> CAN Core - signal sync_edge : std_logic; --Edge for synchronisation - signal OP_State : oper_mode_type; --Protocol control state + -- Receive Buffer size + constant rx_buffer_size : natural range 4 to 512 := 128; - signal clk_tq_nbt : std_logic; --Time quantum clock - Nominal bit time - signal clk_tq_dbt : std_logic; --bit time - Nominal bit time + -- Transcieve buffer size should be synthetised as FD Size (640 bits) + -- or normal CAN (128 bits) + constant useFDSize : boolean := true; - signal sample_nbt : std_logic; --Sample signal for nominal bit time - signal sample_dbt : std_logic; --Sample signal of data bit time - signal sample_nbt_del_1 : std_logic; - signal sample_dbt_del_1 : std_logic; - signal sample_nbt_del_2 : std_logic; - signal sample_dbt_del_2 : std_logic; + -- Whenever internal synchroniser chain should be used for incoming bus + -- signals. Dont turn off unless external synchronisation chain is put on + -- input of FPGA by synthetiser + constant use_sync : boolean := true; - signal sync_nbt : std_logic; - signal sync_dbt : std_logic; - signal sync_nbt_del_1 : std_logic; - signal sync_dbt_del_1 : std_logic; - - signal sp_control : std_logic_vector(1 downto 0); - signal sync_control : std_logic_vector(1 downto 0); - - signal bt_FSM_out : bit_time_type; - - signal hard_sync_edge_valid : std_logic; --Validated hard synchronisation edge to start Protocol control FSM - --Note: Sync edge from busSync.vhd cant be used! If it comes during sample nbt, sequence it causes - -- errors! It needs to be strictly before or strictly after this sequence!!! - - --Bus Synchroniser - signal data_tx : std_logic; --Transcieve data value - signal data_rx : std_logic; --Recieved data value - signal ssp_reset : std_logic; --Clear the Shift register at the beginning of Data Phase!!! - signal trv_delay_calib : std_logic; --Calibration command for transciever delay compenstation (counter) - signal bit_Error_sec_sam : std_logic; --Bit error with secondary sampling transciever! + -- ID (bits 19-16 of adress) + constant ID : natural range 0 to 15 := 1; - signal sample_sec : std_logic; --Secondary sample signal - signal sample_sec_del_1 : std_logic; --Bit destuffing trigger for secondary sample point - signal sample_sec_del_2 : std_logic; --Rec trig for secondary sample point + -- Optional synthesis of received message filters + -- By default the behaviour is as if all the filters are present + constant sup_filtA : boolean := true; + constant sup_filtB : boolean := true; + constant sup_filtC : boolean := true; + constant sup_range : boolean := true; + constant logger_size : natural range 0 to 512 := 8 + ); + port( + -------------------------- + -- System clock and reset + -------------------------- + signal clk_sys : in std_logic; + signal res_n : in std_logic; + + --------------------- + -- Memory interface + --------------------- + signal data_in : in std_logic_vector(31 downto 0); + signal data_out : out std_logic_vector(31 downto 0); + signal adress : in std_logic_vector(23 downto 0); + signal scs : in std_logic; --Chip select + signal srd : in std_logic; --Serial read + signal swr : in std_logic; --Serial write + --Note: This bus is Avalon compatible! + + -------------------- + -- Interrupt output + -------------------- + signal int : out std_logic; + + ------------------- + -- CAN Bus output + ------------------- + signal CAN_tx : out std_logic; + signal CAN_rx : in std_logic; + + --------------------------- + -- Synchronisation signals + --------------------------- + --Time Quantum clocks possible to be used for synchronisation + signal time_quanta_clk : out std_logic; + + ------------------------------------------- + -- Timestamp value for time based messages + ------------------------------------------- + signal timestamp : in std_logic_vector(63 downto 0) + ); + + + + ------------------------------------------------------------------------------ + ------------------------------------------------------------------------------ + ---- Internal signals + ------------------------------------------------------------------------------ + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + -- Common control signals + ------------------------------------------------------------------------------ + + -- Overal reset (External+Reset by memory access) + signal res_n_int : std_logic; + + signal res_n_sync : std_logic; -- Synchronised reset + signal drv_bus : std_logic_vector(1023 downto 0); + signal stat_bus : std_logic_vector(511 downto 0); + + --Interrupt vector (Interrupt register of SJA1000) + signal int_vector : std_logic_vector(10 downto 0); + + ------------------------------------------------------------------------------ + -- Registers <--> RX Buffer Interface + ------------------------------------------------------------------------------ + + --Actually loaded data for reading + signal rx_read_buff : std_logic_vector(31 downto 0); + + --Actual size of synthetised message buffer (in 32 bit words) + signal rx_buf_size : std_logic_vector(7 downto 0); + + --Signal whenever buffer is full + signal rx_full : std_logic; + + --Signal whenever buffer is empty + signal rx_empty : std_logic; + + --Number of messaged stored in recieve buffer + signal rx_message_count : std_logic_vector(7 downto 0); + + --Number of free 32 bit wide ''windows'' + signal rx_mem_free : std_logic_vector(7 downto 0); + + --Position of read pointer + signal rx_read_pointer_pos : std_logic_vector(7 downto 0); + + --Position of write pointer + signal rx_write_pointer_pos : std_logic_vector(7 downto 0); + + --Message was discarded since Memory is full + signal rx_message_disc : std_logic; + + --Some data were discarded, register + signal rx_data_overrun : std_logic; + + + ------------------------------------------------------------------------------ + -- Registers <--> TX Buffer, TXT Buffer + ------------------------------------------------------------------------------ + + --Transcieve data (Common for TX Buffer and TXT Buffer) + signal tran_data_in : std_logic_vector(639 downto 0); + + --Info that message store into buffer from driving registers failed + --because buffer is full + signal txt1_disc : std_logic; + + --Info that message store into buffer from driving registers failed + --because buffer is full + signal txt2_disc : std_logic; + + --Data into the RAM of TXT Buffer + signal tran_data : std_logic_vector(31 downto 0); + + --Address in the RAM of TXT buffer + signal tran_addr : std_logic_vector(4 downto 0); + + + ------------------------------------------------------------------------------ + -- Registers <--> event logger + ------------------------------------------------------------------------------ + + signal loger_act_data : std_logic_vector(63 downto 0); + signal log_write_pointer : std_logic_vector(7 downto 0); + signal log_read_pointer : std_logic_vector(7 downto 0); + signal log_size : std_logic_vector(7 downto 0); + signal log_state_out : logger_state_type; + + + ------------------------------------------------------------------------------ + --TX Arbitrator <--> TX Buffer, TXT Buffer + ------------------------------------------------------------------------------ + + --Time buffer acknowledge that message can be erased + signal txt1_buffer_ack : std_logic; + + --No message in Time TX Buffer + signal txt1_buffer_empty : std_logic; + + --Time buffer acknowledge that message can be erased + signal txt2_buffer_ack : std_logic; + + --No message in Time TX Buffer + signal txt2_buffer_empty : std_logic; + + signal txt1_data_word : std_logic_vector(31 downto 0); + signal txt1_frame_info : std_logic_vector(127 downto 0); + signal txt2_data_word : std_logic_vector(31 downto 0); + signal txt2_frame_info : std_logic_vector(127 downto 0); + + + ------------------------------------------------------------------------------ + -- TX Arbitrator <--> CAN Core + ------------------------------------------------------------------------------ + + --TX Message data + signal tran_data_out : std_logic_vector(31 downto 0); + + --TX Identifier + signal tran_ident_out : std_logic_vector(28 downto 0); + + --TX Data length code + signal tran_dlc_out : std_logic_vector(3 downto 0); + + --TX is remote frame + signal tran_is_rtr : std_logic; + + --TX Identifier type (0-Basic,1-Extended); + signal tran_ident_type_out : std_logic; + + --TX Frame type + signal tran_frame_type_out : std_logic; + + --Bit rate shift for CAN FD frames + signal tran_brs_out : std_logic; + + --Signal for CAN Core that frame on the output is valid and can be + --stored for transmitting + signal tran_frame_valid_out : std_logic; + + --Acknowledge from CAN core that acutal message was stored into internal + --buffer for transmitting + signal tran_data_ack : std_logic; + + --Pointer to TXT buffer memory + signal txt_buf_ptr : natural range 0 to 15; + + + ------------------------------------------------------------------------------ + --RX Buffer <--> CAN Core + ------------------------------------------------------------------------------ + + --Message Identifier + signal rec_ident_in : std_logic_vector(28 downto 0); + + --Message Data (up to 64 bytes); + signal rec_data_in : std_logic_vector(511 downto 0); + + --Data length code + signal rec_dlc_in : std_logic_vector(3 downto 0); + + --Recieved identifier type (0-BASE Format, 1-Extended Format); + signal rec_ident_type_in : std_logic; + + --Recieved frame type (0-Normal CAN, 1- CAN FD) + signal rec_frame_type_in : std_logic; + + --Recieved frame is RTR Frame(0-No, 1-Yes) + signal rec_is_rtr : std_logic; + + --Frame is received properly + signal rec_message_valid : std_logic; + + --Whenever frame was recieved with BIT Rate shift + signal rec_brs : std_logic; + + --Acknowledge for CAN Core about accepted data + signal rec_message_ack : std_logic; - signal trv_delay_out : std_logic_vector(15 downto 0); - + -- Received Error state indicator + signal rec_esi : std_logic; + + -- Pointer to RX Ram in CAN Core and output word with the received data + signal rec_dram_word : std_logic_vector(31 downto 0); + signal rec_dram_addr : natural range 0 to 15; + + + ------------------------------------------------------------------------------ + -- RX Buffer <--> Message filters + ------------------------------------------------------------------------------ + + --Signal whenever identifier matches the filter identifiers + signal out_ident_valid : std_logic; + + + ------------------------------------------------------------------------------ + -- Interrupt manager <--> CAN Core + ------------------------------------------------------------------------------ + + --Valid Error appeared for interrupt + signal error_valid : std_logic; + + --Error pasive /Error acitve functionality changed + signal error_passive_changed : std_logic; + + --Error warning limit reached + signal error_warning_limit : std_logic; + + --Arbitration was lost input + signal arbitration_lost : std_logic; + + --Wake up appeared + signal wake_up_valid : std_logic; + + --Message stored in CAN Core was sucessfully transmitted + signal tx_finished : std_logic; + + --Bit Rate Was Shifted + signal br_shifted : std_logic; + + --Event logging finsihed + signal loger_finished : std_logic; + + + ------------------------------------------------------------------------------ + -- Prescaler <--> CAN Core + ------------------------------------------------------------------------------ + + --Edge for synchronisation + signal sync_edge : std_logic; + + --Protocol control state + signal OP_State : oper_mode_type; + + --Time quantum clock - Nominal bit time + signal clk_tq_nbt : std_logic; + + --Bit time - Nominal bit time + signal clk_tq_dbt : std_logic; + + --Sample signal for nominal bit time + signal sample_nbt : std_logic; + + --Sample signal of data bit time + signal sample_dbt : std_logic; + + --Delay sample signals by 1 or 2 clock cycle + signal sample_nbt_del_1 : std_logic; + signal sample_dbt_del_1 : std_logic; + signal sample_nbt_del_2 : std_logic; + signal sample_dbt_del_2 : std_logic; + + -- Transmitt signals and delayed transmitt signals by 1 clock cycle + signal sync_nbt : std_logic; + signal sync_dbt : std_logic; + signal sync_nbt_del_1 : std_logic; + signal sync_dbt_del_1 : std_logic; + + signal sp_control : std_logic_vector(1 downto 0); + signal sync_control : std_logic_vector(1 downto 0); + + signal bt_FSM_out : bit_time_type; + + --Validated hard synchronisation edge to start Protocol control FSM + signal hard_sync_edge_valid : std_logic; + --Note: Sync edge from busSync.vhd cant be used! If it comes during sample + -- nbt, sequence it causes errors! It needs to be strictly before or + -- strictly after this sequence!!! + + + ------------------------------------------------------------------------------ + -- Bus Synchroniser Interface + ------------------------------------------------------------------------------ + + --Transcieve data value + signal data_tx : std_logic; + + --Recieved data value + signal data_rx : std_logic; + + --Clear the Shift register at the beginning of Data Phase!!! + signal ssp_reset : std_logic; + + --Calibration command for transciever delay compenstation (counter) + signal trv_delay_calib : std_logic; + + --Bit error with secondary sampling transciever! + signal bit_Error_sec_sam : std_logic; + + --Secondary sample signal + signal sample_sec : std_logic; + + --Bit destuffing trigger for secondary sample point + signal sample_sec_del_1 : std_logic; + + --Rec trig for secondary sample point + signal sample_sec_del_2 : std_logic; + + -- Transceiver delay output + signal trv_delay_out : std_logic_vector(15 downto 0); + end entity CAN_top_level; - + architecture rtl of CAN_top_level is ---------------------------------------------------- - --Defining explicit architectures for used entites + -- Defining explicit architectures for used entites ---------------------------------------------------- - for reg_comp : registers use entity work.registers(rtl); - for rx_buf_comp : rxBuffer use entity work.rxBuffer(rtl); - for txt1_buf_comp : txtBuffer use entity work.txtBuffer(rtl); - for txt2_buf_comp : txtBuffer use entity work.txtBuffer(rtl); - for tx_arb_comp : txArbitrator use entity work.txArbitrator(rtl); - for mes_filt_comp : messageFilter use entity work.messageFilter(rtl); - for int_man_comp : intManager use entity work.intManager(rtl); - for core_top_comp : core_top use entity work.core_top(rtl); - for prescaler_comp : prescaler_v3 use entity work.prescaler_v3(rtl); - for bus_sync_comp : busSync use entity work.busSync(rtl); - for rst_sync_comp : rst_sync use entity work.rst_sync(rtl); - --for log_comp : CAN_logger use entity work.CAN_logger(rtl); + for reg_comp : registers use entity work.registers(rtl); + for rx_buf_comp : rxBuffer use entity work.rxBuffer(rtl); + for txt1_buf_comp : txtBuffer use entity work.txtBuffer(rtl); + for txt2_buf_comp : txtBuffer use entity work.txtBuffer(rtl); + for tx_arb_comp : txArbitrator use entity work.txArbitrator(rtl); + for mes_filt_comp : messageFilter use entity work.messageFilter(rtl); + for int_man_comp : intManager use entity work.intManager(rtl); + for core_top_comp : core_top use entity work.core_top(rtl); + for prescaler_comp : prescaler_v3 use entity work.prescaler_v3(rtl); + for bus_sync_comp : busSync use entity work.busSync(rtl); + for rst_sync_comp : rst_sync use entity work.rst_sync(rtl); + --for log_comp : CAN_logger use entity work.CAN_logger(rtl); begin - - rst_sync_comp:rst_sync - port map( - clk => clk_sys, - arst_n => res_n, - rst_n => res_n_sync - ); - - reg_comp:registers - generic map( - compType => CAN_COMPONENT_TYPE, - use_logger => use_logger, - sup_filtA => sup_filtA, - sup_filtB => sup_filtB, - sup_filtC => sup_filtC, - sup_range => sup_range, - ID => ID - ) - port map( - clk_sys => clk_sys, - res_n => res_n_sync, - res_out => res_n_int, - data_in => data_in, - data_out => data_out, - adress => adress, - scs => scs, - srd => srd, - swr => swr, - drv_bus => drv_bus, - stat_bus => stat_bus, - rx_read_buff => rx_read_buff, - rx_buf_size => rx_buf_size, - rx_full => rx_full, - rx_empty => rx_empty, - rx_message_count => rx_message_count, - rx_mem_free => rx_mem_free, - rx_read_pointer_pos => rx_read_pointer_pos, - rx_write_pointer_pos => rx_write_pointer_pos, - rx_message_disc => rx_message_disc, - rx_data_overrun => rx_data_overrun, - tran_data_in => tran_data_in, - tran_data => tran_data, - tran_addr => tran_addr, - txt2_empty => txt2_buffer_empty, - txt2_disc => txt2_disc, - txt1_empty => txt1_buffer_empty, - txt1_disc => txt1_disc, - int_vector => int_vector, - trv_delay_out => trv_delay_out, - loger_act_data => loger_act_data, - log_write_pointer => log_write_pointer, - log_read_pointer => log_read_pointer, - log_size => log_size, - log_state_out => log_state_out - ); - - rx_buf_comp:rxBuffer - generic map( - buff_size => rx_buffer_size - ) - port map( - clk_sys => clk_sys, - res_n => res_n_int, - rec_ident_in => rec_ident_in, - rec_dlc_in => rec_dlc_in, - rec_ident_type_in => rec_ident_type_in, - rec_frame_type_in => rec_frame_type_in, - rec_is_rtr => rec_is_rtr, - rec_message_valid => out_ident_valid, --Note: This has to be confirmed from Message filters not CAN Core - rec_brs => rec_brs, - rec_esi => rec_esi, - rec_message_ack => rec_message_ack, - rec_dram_word => rec_dram_word, - rec_dram_addr => rec_dram_addr, - rx_buf_size => rx_buf_size, - rx_full => rx_full, - rx_empty => rx_empty, - rx_message_count => rx_message_count, - rx_mem_free => rx_mem_free, - rx_read_pointer_pos => rx_read_pointer_pos, - rx_write_pointer_pos => rx_write_pointer_pos, - rx_message_disc => rx_message_disc, - rx_data_overrun => rx_data_overrun, - rx_read_buff => rx_read_buff, - timestamp => timestamp, - drv_bus => drv_bus - ); - - txt1_buf_comp:txtBuffer + + rst_sync_comp : rst_sync + port map( + clk => clk_sys, + arst_n => res_n, + rst_n => res_n_sync + ); + + reg_comp : registers generic map( - ID => 1, - useFDsize => useFDsize - ) - PORT map( - clk_sys => clk_sys, - res_n => res_n_int, - drv_bus => drv_bus, - tran_data => tran_data, - tran_addr => tran_addr, - txt_empty => txt1_buffer_empty, - txt_data_ack => txt1_buffer_ack, - txt_data_word => txt1_data_word, - txt_data_addr => txt_buf_ptr, - txt_frame_info_out => txt1_frame_info - ); - - txt2_buf_comp:txtBuffer + compType => CAN_COMPONENT_TYPE, + use_logger => use_logger, + sup_filtA => sup_filtA, + sup_filtB => sup_filtB, + sup_filtC => sup_filtC, + sup_range => sup_range, + ID => ID + ) + port map( + clk_sys => clk_sys, + res_n => res_n_sync, + res_out => res_n_int, + data_in => data_in, + data_out => data_out, + adress => adress, + scs => scs, + srd => srd, + swr => swr, + drv_bus => drv_bus, + stat_bus => stat_bus, + rx_read_buff => rx_read_buff, + rx_buf_size => rx_buf_size, + rx_full => rx_full, + rx_empty => rx_empty, + rx_message_count => rx_message_count, + rx_mem_free => rx_mem_free, + rx_read_pointer_pos => rx_read_pointer_pos, + rx_write_pointer_pos => rx_write_pointer_pos, + rx_message_disc => rx_message_disc, + rx_data_overrun => rx_data_overrun, + tran_data_in => tran_data_in, + tran_data => tran_data, + tran_addr => tran_addr, + txt2_empty => txt2_buffer_empty, + txt2_disc => txt2_disc, + txt1_empty => txt1_buffer_empty, + txt1_disc => txt1_disc, + int_vector => int_vector, + trv_delay_out => trv_delay_out, + loger_act_data => loger_act_data, + log_write_pointer => log_write_pointer, + log_read_pointer => log_read_pointer, + log_size => log_size, + log_state_out => log_state_out + ); + + rx_buf_comp : rxBuffer generic map( - ID => 2, - useFDsize => useFDsize - ) - PORT map( - clk_sys => clk_sys, - res_n => res_n_int, - drv_bus => drv_bus, - tran_data => tran_data, - tran_addr => tran_addr, - txt_empty => txt2_buffer_empty, - txt_data_ack => txt2_buffer_ack, - txt_data_word => txt2_data_word, - txt_data_addr => txt_buf_ptr, - txt_frame_info_out => txt2_frame_info - ); - - tx_arb_comp:txArbitrator - port map( - clk_sys => clk_sys, - res_n => res_n, - - txt1buf_info_in => txt1_frame_info, - txt1buf_data_in => txt1_data_word, - txt1_buffer_ack => txt1_buffer_ack, - txt1_buffer_empty => txt1_buffer_empty, - - txt2buf_info_in => txt2_frame_info, - txt2buf_data_in => txt2_data_word, - txt2_buffer_empty => txt2_buffer_empty, - txt2_buffer_ack => txt2_buffer_ack, - - tran_data_word_out => tran_data_out, - tran_ident_out => tran_ident_out, - tran_dlc_out => tran_dlc_out, - tran_is_rtr => tran_is_rtr, - tran_ident_type_out => tran_ident_type_out, - tran_frame_type_out => tran_frame_type_out, - tran_brs_out => tran_brs_out, - tran_frame_valid_out => tran_frame_valid_out, - tran_data_ack => tran_data_ack, - tran_valid => tx_finished, - - drv_bus => drv_bus, - timestamp => timestamp - ); - - mes_filt_comp:messageFilter - generic map( - sup_filtA => sup_filtA, - sup_filtB => sup_filtB, - sup_filtC => sup_filtC, - sup_range => sup_range - ) - port map( - clk_sys => clk_sys, - res_n => res_n, - rec_ident_in => rec_ident_in, - ident_type => rec_ident_type_in, - frame_type => rec_frame_type_in, - rec_ident_valid => rec_message_valid, - drv_bus => drv_bus, - out_ident_valid => out_ident_valid - ); - - int_man_comp:intManager - generic map( - int_length => 7 - ) - port map( - clk_sys => clk_sys, - res_n => res_n_int, - error_valid => error_valid, - error_passive_changed=> error_passive_changed, - error_warning_limit => error_warning_limit, - arbitration_lost => arbitration_lost, - wake_up_valid => wake_up_valid, - tx_finished => tx_finished, - br_shifted => br_shifted, - rx_message_disc => rx_message_disc, - rec_message_valid => rec_message_valid, - rx_full => rx_full, - loger_finished => loger_finished, - drv_bus => drv_bus, - int_out => int, - int_vector => int_vector - ); - - core_top_comp: core_top - port map( - clk_sys => clk_sys, - res_n => res_n_int, - drv_bus => drv_bus, - stat_bus => stat_bus , - tran_data_in => tran_data_out, - tran_ident_in => tran_ident_out, - tran_dlc_in => tran_dlc_out, - tran_is_rtr_in => tran_is_rtr, - tran_ident_type_in => tran_ident_type_out, - tran_frame_type_in => tran_frame_type_out, - tran_brs_in => tran_brs_out, - tran_frame_valid_in => tran_frame_valid_out, - tran_data_ack_out => tran_data_ack, - txt_buf_ptr => txt_buf_ptr, - rec_ident_out => rec_ident_in, - rec_dlc_out => rec_dlc_in, - rec_ident_type_out => rec_ident_type_in, - rec_frame_type_out => rec_frame_type_in, - rec_is_rtr_out => rec_is_rtr, - rec_brs_out => rec_brs, - rec_esi_out => rec_esi, - rec_message_valid_out=> rec_message_valid, - rec_message_ack_out => rec_message_ack, - rec_dram_word_out => rec_dram_word, - rec_dram_addr_out => rec_dram_addr, - arbitration_lost_out => arbitration_lost, - wake_up_valid => wake_up_valid, - tx_finished => tx_finished, - br_shifted => br_shifted, - error_valid => error_valid, - error_passive_changed=> error_passive_changed, - error_warning_limit => error_warning_limit, - sample_nbt_del_2 => sample_nbt_del_2, - sample_dbt_del_2 => sample_dbt_del_2, - sample_nbt_del_1 => sample_nbt_del_1, - sample_dbt_del_1 => sample_dbt_del_1, - sync_nbt => sync_nbt, - sync_dbt => sync_dbt, - sync_nbt_del_1 => sync_nbt_del_1, - sync_dbt_del_1 => sync_dbt_del_1, - sample_sec => sample_sec, - sample_sec_del_1 => sample_sec_del_1, - sample_sec_del_2 => sample_sec_del_2 , - sync_control => sync_control, - data_rx => data_rx, - data_tx => data_tx, - timestamp => timestamp, - sp_control => sp_control, - ssp_reset => ssp_reset, - trv_delay_calib => trv_delay_calib, - hard_sync_edge => hard_sync_edge_valid, - bit_Error_sec_sam => bit_Error_sec_sam - ); - - prescaler_comp:prescaler_v3 - port map( - clk_sys => clk_sys, - res_n => res_n, - OP_State => OP_State, - sync_edge => sync_edge, - drv_bus => drv_bus , - clk_tq_nbt => clk_tq_nbt, - clk_tq_dbt => clk_tq_dbt , - sample_nbt => sample_nbt, - sample_dbt => sample_dbt, - bt_FSM_out => bt_FSM_out, - sample_nbt_del_1 => sample_nbt_del_1, - sample_dbt_del_1 => sample_dbt_del_1, - sample_nbt_del_2 => sample_nbt_del_2, - sample_dbt_del_2 => sample_dbt_del_2, - sync_nbt => sync_nbt, - sync_dbt => sync_dbt, - sync_nbt_del_1 => sync_nbt_del_1, - sync_dbt_del_1 => sync_dbt_del_1, - data_tx => data_tx, - hard_sync_edge_valid => hard_sync_edge_valid, - sp_control => sp_control, - sync_control => sync_control - ); - - bus_sync_comp:busSync - generic map ( - use_Sync => use_sync - ) - port map( - clk_sys => clk_sys, - res_n => res_n_int, - CAN_rx => CAN_rx, - CAN_tx => CAN_tx, - drv_bus => drv_bus, - sample_nbt => sample_nbt, - sample_dbt => sample_dbt, - sync_edge => sync_edge, - data_tx => data_tx, - data_rx => data_rx, - sp_control => sp_control, - ssp_reset => ssp_reset, - trv_delay_calib => trv_delay_calib, - bit_err_enable => '1', --Note: Bit Error detection enabled always. bit_Error signal from this block used only for secondary sample point bit error detection!! - sample_sec_out => sample_sec, - sample_sec_del_1_out => sample_sec_del_1, - sample_sec_del_2_out => sample_sec_del_2, - trv_delay_out => trv_delay_out, - bit_Error => bit_Error_sec_sam - ); - - - LOG_GEN:if(use_logger=true) generate - log_comp:CAN_logger - generic map( - memory_size => logger_size - ) - port map( - clk_sys => clk_sys, - res_n => res_n, - - drv_bus => drv_bus, - stat_bus => stat_bus, - sync_edge => sync_edge, - timestamp => timestamp, - - loger_finished => loger_finished, - loger_act_data => loger_act_data, - log_write_pointer => log_write_pointer, - log_read_pointer => log_read_pointer, - log_size => log_size, - log_state_out => log_state_out, - bt_FSM => bt_FSM_out, - data_overrun => rx_data_overrun - ); - end generate LOG_GEN; - - LOG_GEN2:if(use_logger=false)generate - loger_finished <= '0'; - loger_act_data <= (OTHERS =>'0'); - log_write_pointer <= (OTHERS =>'0'); - log_read_pointer <= (OTHERS =>'0'); - log_size <= (OTHERS =>'0'); - end generate LOG_GEN2; - + buff_size => rx_buffer_size + ) + port map( + clk_sys => clk_sys, + res_n => res_n_int, + rec_ident_in => rec_ident_in, + rec_dlc_in => rec_dlc_in, + rec_ident_type_in => rec_ident_type_in, + rec_frame_type_in => rec_frame_type_in, + rec_is_rtr => rec_is_rtr, + + --Note: This has to be confirmed from Message filters not CAN Core + rec_message_valid => out_ident_valid, + + rec_brs => rec_brs, + rec_esi => rec_esi, + rec_message_ack => rec_message_ack, + rec_dram_word => rec_dram_word, + rec_dram_addr => rec_dram_addr, + rx_buf_size => rx_buf_size, + rx_full => rx_full, + rx_empty => rx_empty, + rx_message_count => rx_message_count, + rx_mem_free => rx_mem_free, + rx_read_pointer_pos => rx_read_pointer_pos, + rx_write_pointer_pos => rx_write_pointer_pos, + rx_message_disc => rx_message_disc, + rx_data_overrun => rx_data_overrun, + rx_read_buff => rx_read_buff, + timestamp => timestamp, + drv_bus => drv_bus + ); + + txt1_buf_comp : txtBuffer + generic map( + ID => 1, + useFDsize => useFDsize + ) + port map( + clk_sys => clk_sys, + res_n => res_n_int, + drv_bus => drv_bus, + tran_data => tran_data, + tran_addr => tran_addr, + txt_empty => txt1_buffer_empty, + txt_data_ack => txt1_buffer_ack, + txt_data_word => txt1_data_word, + txt_data_addr => txt_buf_ptr, + txt_frame_info_out => txt1_frame_info + ); + + txt2_buf_comp : txtBuffer + generic map( + ID => 2, + useFDsize => useFDsize + ) + port map( + clk_sys => clk_sys, + res_n => res_n_int, + drv_bus => drv_bus, + tran_data => tran_data, + tran_addr => tran_addr, + txt_empty => txt2_buffer_empty, + txt_data_ack => txt2_buffer_ack, + txt_data_word => txt2_data_word, + txt_data_addr => txt_buf_ptr, + txt_frame_info_out => txt2_frame_info + ); + + tx_arb_comp : txArbitrator + port map( + clk_sys => clk_sys, + res_n => res_n, + + txt1buf_info_in => txt1_frame_info, + txt1buf_data_in => txt1_data_word, + txt1_buffer_ack => txt1_buffer_ack, + txt1_buffer_empty => txt1_buffer_empty, + + txt2buf_info_in => txt2_frame_info, + txt2buf_data_in => txt2_data_word, + txt2_buffer_empty => txt2_buffer_empty, + txt2_buffer_ack => txt2_buffer_ack, + + tran_data_word_out => tran_data_out, + tran_ident_out => tran_ident_out, + tran_dlc_out => tran_dlc_out, + tran_is_rtr => tran_is_rtr, + tran_ident_type_out => tran_ident_type_out, + tran_frame_type_out => tran_frame_type_out, + tran_brs_out => tran_brs_out, + tran_frame_valid_out => tran_frame_valid_out, + tran_data_ack => tran_data_ack, + tran_valid => tx_finished, + + drv_bus => drv_bus, + timestamp => timestamp + ); + + mes_filt_comp : messageFilter + generic map( + sup_filtA => sup_filtA, + sup_filtB => sup_filtB, + sup_filtC => sup_filtC, + sup_range => sup_range + ) + port map( + clk_sys => clk_sys, + res_n => res_n, + rec_ident_in => rec_ident_in, + ident_type => rec_ident_type_in, + frame_type => rec_frame_type_in, + rec_ident_valid => rec_message_valid, + drv_bus => drv_bus, + out_ident_valid => out_ident_valid + ); + + int_man_comp : intManager + generic map( + int_length => 7 + ) + port map( + clk_sys => clk_sys, + res_n => res_n_int, + error_valid => error_valid, + error_passive_changed => error_passive_changed, + error_warning_limit => error_warning_limit, + arbitration_lost => arbitration_lost, + wake_up_valid => wake_up_valid, + tx_finished => tx_finished, + br_shifted => br_shifted, + rx_message_disc => rx_message_disc, + rec_message_valid => rec_message_valid, + rx_full => rx_full, + loger_finished => loger_finished, + drv_bus => drv_bus, + int_out => int, + int_vector => int_vector + ); + + core_top_comp : core_top + port map( + clk_sys => clk_sys, + res_n => res_n_int, + drv_bus => drv_bus, + stat_bus => stat_bus, + tran_data_in => tran_data_out, + tran_ident_in => tran_ident_out, + tran_dlc_in => tran_dlc_out, + tran_is_rtr_in => tran_is_rtr, + tran_ident_type_in => tran_ident_type_out, + tran_frame_type_in => tran_frame_type_out, + tran_brs_in => tran_brs_out, + tran_frame_valid_in => tran_frame_valid_out, + tran_data_ack_out => tran_data_ack, + txt_buf_ptr => txt_buf_ptr, + rec_ident_out => rec_ident_in, + rec_dlc_out => rec_dlc_in, + rec_ident_type_out => rec_ident_type_in, + rec_frame_type_out => rec_frame_type_in, + rec_is_rtr_out => rec_is_rtr, + rec_brs_out => rec_brs, + rec_esi_out => rec_esi, + rec_message_valid_out => rec_message_valid, + rec_message_ack_out => rec_message_ack, + rec_dram_word_out => rec_dram_word, + rec_dram_addr_out => rec_dram_addr, + arbitration_lost_out => arbitration_lost, + wake_up_valid => wake_up_valid, + tx_finished => tx_finished, + br_shifted => br_shifted, + error_valid => error_valid, + error_passive_changed => error_passive_changed, + error_warning_limit => error_warning_limit, + sample_nbt_del_2 => sample_nbt_del_2, + sample_dbt_del_2 => sample_dbt_del_2, + sample_nbt_del_1 => sample_nbt_del_1, + sample_dbt_del_1 => sample_dbt_del_1, + sync_nbt => sync_nbt, + sync_dbt => sync_dbt, + sync_nbt_del_1 => sync_nbt_del_1, + sync_dbt_del_1 => sync_dbt_del_1, + sample_sec => sample_sec, + sample_sec_del_1 => sample_sec_del_1, + sample_sec_del_2 => sample_sec_del_2, + sync_control => sync_control, + data_rx => data_rx, + data_tx => data_tx, + timestamp => timestamp, + sp_control => sp_control, + ssp_reset => ssp_reset, + trv_delay_calib => trv_delay_calib, + hard_sync_edge => hard_sync_edge_valid, + bit_Error_sec_sam => bit_Error_sec_sam + ); + + prescaler_comp : prescaler_v3 + port map( + clk_sys => clk_sys, + res_n => res_n, + OP_State => OP_State, + sync_edge => sync_edge, + drv_bus => drv_bus, + clk_tq_nbt => clk_tq_nbt, + clk_tq_dbt => clk_tq_dbt, + sample_nbt => sample_nbt, + sample_dbt => sample_dbt, + bt_FSM_out => bt_FSM_out, + sample_nbt_del_1 => sample_nbt_del_1, + sample_dbt_del_1 => sample_dbt_del_1, + sample_nbt_del_2 => sample_nbt_del_2, + sample_dbt_del_2 => sample_dbt_del_2, + sync_nbt => sync_nbt, + sync_dbt => sync_dbt, + sync_nbt_del_1 => sync_nbt_del_1, + sync_dbt_del_1 => sync_dbt_del_1, + data_tx => data_tx, + hard_sync_edge_valid => hard_sync_edge_valid, + sp_control => sp_control, + sync_control => sync_control + ); + + bus_sync_comp : busSync + generic map ( + use_Sync => use_sync + ) + port map( + clk_sys => clk_sys, + res_n => res_n_int, + CAN_rx => CAN_rx, + CAN_tx => CAN_tx, + drv_bus => drv_bus, + sample_nbt => sample_nbt, + sample_dbt => sample_dbt, + sync_edge => sync_edge, + data_tx => data_tx, + data_rx => data_rx, + sp_control => sp_control, + ssp_reset => ssp_reset, + trv_delay_calib => trv_delay_calib, + + --Note: Bit Error detection enabled always. bit_Error signal from this + -- block used only for secondary sample point bit error detection!! + bit_err_enable => '1', + + sample_sec_out => sample_sec, + sample_sec_del_1_out => sample_sec_del_1, + sample_sec_del_2_out => sample_sec_del_2, + trv_delay_out => trv_delay_out, + bit_Error => bit_Error_sec_sam + ); + + + LOG_GEN : if(use_logger = true) generate + log_comp : CAN_logger + generic map( + memory_size => logger_size + ) + port map( + clk_sys => clk_sys, + res_n => res_n, + + drv_bus => drv_bus, + stat_bus => stat_bus, + sync_edge => sync_edge, + timestamp => timestamp, + + loger_finished => loger_finished, + loger_act_data => loger_act_data, + log_write_pointer => log_write_pointer, + log_read_pointer => log_read_pointer, + log_size => log_size, + log_state_out => log_state_out, + bt_FSM => bt_FSM_out, + data_overrun => rx_data_overrun + ); + end generate LOG_GEN; + + LOG_GEN2 : if(use_logger = false)generate + loger_finished <= '0'; + loger_act_data <= (others => '0'); + log_write_pointer <= (others => '0'); + log_read_pointer <= (others => '0'); + log_size <= (others => '0'); + end generate LOG_GEN2; + --Bit time clock output propagation - time_quanta_clk <= clk_tq_nbt when sp_control=NOMINAL_SAMPLE else clk_tq_dbt; + time_quanta_clk <= clk_tq_nbt when sp_control = NOMINAL_SAMPLE else + clk_tq_dbt; - - OP_State <= oper_mode_type'VAL(to_integer(unsigned(stat_bus(STAT_OP_STATE_HIGH downto STAT_OP_STATE_LOW)))); + OP_State <= oper_mode_type'val(to_integer(unsigned( + stat_bus(STAT_OP_STATE_HIGH downto STAT_OP_STATE_LOW)))); end architecture; diff --git a/src/CANcomponents.vhd b/src/CANcomponents.vhd index c6e8fcf8123c8622b866c60d83f3fa695f30f831..448f44a4cf78d1a6d1a3694a8c9cb9b961a44332 100644 --- a/src/CANcomponents.vhd +++ b/src/CANcomponents.vhd @@ -1,22 +1,22 @@ -Library ieee; -USE IEEE.std_logic_1164.all; -USE IEEE.numeric_std.ALL; -USE ieee.std_logic_unsigned.All; -USE WORK.CANconstants.ALL; +library ieee; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use ieee.std_logic_unsigned.all; +use WORK.CANconstants.all; -------------------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- -- -- CAN with Flexible Data-Rate IP Core -- -- Copyright (C) 2015 Ondrej Ille -- --- This program is free software; you can redistribute it and/or +-- This program is free software; -- modify it under the terms of the GNU General Public License --- as published by the Free Software Foundation; either version 2 +-- as published by the Free Software Foundation; -- of the License, or (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- but WITHOUT ANY WARRANTY; -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- @@ -30,794 +30,659 @@ USE WORK.CANconstants.ALL; -- -- 15.11.2017 Created file -- 27.11.2017 Added "rst_sync" asynchronous rest synchroniser circuit --- 29.11.2017 Removed "rec_data" between Protocol control and RX Buffer, replaced with rec_dram_word and +-- 29.11.2017 Removed "rec_data" between Protocol control and RX Buffer, +-- replaced with rec_dram_word and -- rec_dram_addr as part of resource optimization. -- 30.11.2017 Updated "txt_buffer" for direct access to buffer -------------------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- -- Purpose: --- Package for components declarations to avoid writing component declarations every time into --- architecture itself. ---------------------------------------------------------------------------------------------------------------- +-- Package for components declarations to avoid writing component declarations +-- every time into architecture itself. Do not use comments on signals in this +-- file, comment the signal in the entity declaration! +-------------------------------------------------------------------------------- package CANcomponents is - - -------------------------------------------------------------------------------- - -------------------------------------------------------------------------------- + + ------------------------------------------------------------------------------ + ------------------------------------------------------------------------------ ---- CAN FD Core top level entity - -------------------------------------------------------------------------------- - -------------------------------------------------------------------------------- + ------------------------------------------------------------------------------ + ------------------------------------------------------------------------------ component CAN_top_level is - generic( - constant use_logger :boolean :=true; --Whenever event logger should be synthetised (not yet implemented) - constant rx_buffer_size :natural :=128; --Transcieve Buffer size - constant useFDSize :boolean :=true; --Transcieve buffer size should be synthetised as FD Size (640 bits) or normal CAN (128 bits) - constant use_sync :boolean :=true; --Whenever internal synchroniser chain should be used for incoming bus signals - --Dont turn off unless external synchronisation chain is put on input of FPGA by - --synthetiser - constant ID :natural range 0 to 15:=1; --ID (bits 19-16 of adress) - constant sup_filtA :boolean := true; --Optional synthesis of received message filters - constant sup_filtB :boolean := true; -- By default the behaviour is as if all the filters are present - constant sup_filtC :boolean := true; - constant sup_range :boolean := true; - constant logger_size :natural --range 0 to 512:=8 - ); - port( - signal clk_sys:in std_logic; - signal res_n:in std_logic; - signal data_in:in std_logic_vector(31 downto 0); - signal data_out:out std_logic_vector(31 downto 0); - signal adress:in std_logic_vector(23 downto 0); - signal scs:in std_logic; --Chip select - signal srd:in std_logic; --Serial read - signal swr:in std_logic; --Serial write - signal int:out std_logic; - signal CAN_tx:out std_logic; - signal CAN_rx:in std_logic; - signal time_quanta_clk:out std_logic; --Time Quantum clocks possible to be used for synchronisation - signal timestamp:in std_logic_vector(63 downto 0) - ); + generic( + constant use_logger : boolean := true; + constant rx_buffer_size : natural := 128; + constant useFDSize : boolean := true; + constant use_sync : boolean := true; + constant ID : natural range 0 to 15 := 1; + constant sup_filtA : boolean := true; + constant sup_filtB : boolean := true; + constant sup_filtC : boolean := true; + constant sup_range : boolean := true; + constant logger_size : natural --range 0 to 512:=8 + ); + port( + signal clk_sys : in std_logic; + signal res_n : in std_logic; + signal data_in : in std_logic_vector(31 downto 0); + signal data_out : out std_logic_vector(31 downto 0); + signal adress : in std_logic_vector(23 downto 0); + signal scs : in std_logic; + signal srd : in std_logic; + signal swr : in std_logic; + signal int : out std_logic; + signal CAN_tx : out std_logic; + signal CAN_rx : in std_logic; + signal time_quanta_clk : out std_logic; + signal timestamp : in std_logic_vector(63 downto 0) + ); end component; - - -------------------------------------------------------------------------------- - -------------------------------------------------------------------------------- + + ------------------------------------------------------------------------------ + ------------------------------------------------------------------------------ ---- CAN Top level components - -------------------------------------------------------------------------------- - -------------------------------------------------------------------------------- + ------------------------------------------------------------------------------ + ------------------------------------------------------------------------------ - -------------- - --Registers -- - -------------- + ------------------------------------------------------------------------------ + -- Registers + ------------------------------------------------------------------------------ component registers is - generic( - constant compType : std_logic_vector(3 downto 0):= CAN_COMPONENT_TYPE; - constant use_logger : boolean := true; --Whenever event logger is present - constant sup_filtA : boolean := true; --Optional synthesis of received message filters - constant sup_filtB : boolean := true; -- By default the behaviour is as if all the filters are present - constant sup_filtC : boolean := true; - constant sup_range : boolean := true; - constant ID : natural --ID of the component - ); - port( - signal clk_sys :in std_logic; - signal res_n :in std_logic; - signal res_out :out std_logic; - - signal data_in :in std_logic_vector(31 downto 0); - signal data_out :out std_logic_vector(31 downto 0); - signal adress :in std_logic_vector(23 downto 0); - signal scs :in std_logic; - signal srd :in std_logic; - signal swr :in std_logic; - - signal drv_bus :out std_logic_vector(1023 downto 0); - signal stat_bus :in std_logic_vector(511 downto 0); - - signal rx_read_buff :in std_logic_vector(31 downto 0); --Actually loaded data for reading - signal rx_buf_size :in std_logic_vector(7 downto 0); --Actual size of synthetised message buffer (in 32 bit words) - signal rx_full :in std_logic; --Signal whenever buffer is full - signal rx_empty :in std_logic; --Signal whenever buffer is empty - signal rx_message_count :in std_logic_vector(7 downto 0); --Number of messaged stored in recieve buffer - signal rx_mem_free :in std_logic_vector(7 downto 0); --Number of free 32 bit wide ''windows'' - signal rx_read_pointer_pos :in std_logic_vector(7 downto 0); --Position of read pointer - signal rx_write_pointer_pos :in std_logic_vector(7 downto 0); --Position of write pointer - signal rx_message_disc :in std_logic; --Message was discarded since Memory is full - signal rx_data_overrun :in std_logic; --Some data were discarded, register - - signal tran_data_in :out std_logic_vector(639 downto 0); --Transcieve data (Common for TX Buffer and TXT Buffer) - - signal tran_data :out std_logic_vector(31 downto 0); --Data into the RAM of TXT Buffer - signal tran_addr :out std_logic_vector(4 downto 0); --Address in the RAM of TXT buffer - - signal txt1_empty :in std_logic; --Logic 1 signals empty TxTime buffer - signal txt1_disc :in std_logic; --Info that message store into buffer from driving registers failed because buffer is full - - signal txt2_empty :in std_logic; --Logic 1 signals empty TxTime buffer - signal txt2_disc :in std_logic; --Info that message store into buffer from driving registers failed because buffer is full - - signal trv_delay_out :in std_logic_vector(15 downto 0); - - signal int_vector :in std_logic_vector(10 downto 0); --Interrupt vector (Interrupt register of SJA1000) - - signal loger_act_data :in std_logic_vector(63 downto 0); - signal log_write_pointer :in std_logic_vector(7 downto 0); - signal log_read_pointer :in std_logic_vector(7 downto 0); - signal log_size :in std_logic_vector(7 downto 0); - signal log_state_out :in logger_state_type - ); + generic( + constant compType : std_logic_vector(3 downto 0) := CAN_COMPONENT_TYPE; + constant use_logger : boolean := true; + constant sup_filtA : boolean := true; + constant sup_filtB : boolean := true; + constant sup_filtC : boolean := true; + constant sup_range : boolean := true; + constant ID : natural + ); + port( + signal clk_sys : in std_logic; + signal res_n : in std_logic; + signal res_out : out std_logic; + signal data_in : in std_logic_vector(31 downto 0); + signal data_out : out std_logic_vector(31 downto 0); + signal adress : in std_logic_vector(23 downto 0); + signal scs : in std_logic; + signal srd : in std_logic; + signal swr : in std_logic; + signal drv_bus : out std_logic_vector(1023 downto 0); + signal stat_bus : in std_logic_vector(511 downto 0); + signal rx_read_buff : in std_logic_vector(31 downto 0); + signal rx_buf_size : in std_logic_vector(7 downto 0); + signal rx_full : in std_logic; + signal rx_empty : in std_logic; + signal rx_message_count : in std_logic_vector(7 downto 0); + signal rx_mem_free : in std_logic_vector(7 downto 0); + signal rx_read_pointer_pos : in std_logic_vector(7 downto 0); + signal rx_write_pointer_pos : in std_logic_vector(7 downto 0); + signal rx_message_disc : in std_logic; + signal rx_data_overrun : in std_logic; + signal tran_data_in : out std_logic_vector(639 downto 0); + signal tran_data : out std_logic_vector(31 downto 0); + signal tran_addr : out std_logic_vector(4 downto 0); + signal txt1_empty : in std_logic; + signal txt1_disc : in std_logic; + signal txt2_empty : in std_logic; + signal txt2_disc : in std_logic; + signal trv_delay_out : in std_logic_vector(15 downto 0); + signal int_vector : in std_logic_vector(10 downto 0); + signal loger_act_data : in std_logic_vector(63 downto 0); + signal log_write_pointer : in std_logic_vector(7 downto 0); + signal log_read_pointer : in std_logic_vector(7 downto 0); + signal log_size : in std_logic_vector(7 downto 0); + signal log_state_out : in logger_state_type + ); end component; - - --------------------- - --RX Buffer module -- - --------------------- + + ------------------------------------------------------------------------------ + -- RX Buffer module + ------------------------------------------------------------------------------ component rxBuffer is - generic( - buff_size : natural range 4 to 512 - ); - port( - signal clk_sys :in std_logic; --System clock - signal res_n :in std_logic; --Async. reset - - signal rec_ident_in :in std_logic_vector(28 downto 0); --Message Identifier - signal rec_dlc_in :in std_logic_vector(3 downto 0); --Data length code - signal rec_ident_type_in :in std_logic; --Recieved identifier type (0-BASE Format, 1-Extended Format); - signal rec_frame_type_in :in std_logic; --Recieved frame type (0-Normal CAN, 1- CAN FD) - signal rec_is_rtr :in std_logic; --Recieved frame is RTR Frame(0-No, 1-Yes) - signal rec_message_valid :in std_logic; --Output from acceptance filters (out_ident_valid) if message fits the filters - signal rec_brs :in std_logic; --Whenever frame was recieved with BIT Rate shift - signal rec_esi :in std_logic; --Recieved error state indicator - signal rec_message_ack :out std_logic; --Acknowledge for CAN Core about accepted data - - signal rec_dram_word :in std_logic_vector(31 downto 0); - signal rec_dram_addr :out natural range 0 to 15; - - signal rx_buf_size :out std_logic_vector(7 downto 0); --Actual size of synthetised message buffer (in 32 bit words) - signal rx_full :out std_logic; --Signal whenever buffer is full - signal rx_empty :out std_logic; --Signal whenever buffer is empty - signal rx_message_count :out std_logic_vector(7 downto 0); --Number of messaged stored in recieve buffer - signal rx_mem_free :out std_logic_vector(7 downto 0); --Number of free 32 bit wide ''windows'' - signal rx_read_pointer_pos :out std_logic_vector(7 downto 0); --Position of read pointer - signal rx_write_pointer_pos :out std_logic_vector(7 downto 0); --Position of write pointer - signal rx_message_disc :out std_logic; --Message was discarded since Memory is full - signal rx_data_overrun :out std_logic; --Some data were discarded, register - - signal timestamp :in std_logic_vector(63 downto 0); - - signal rx_read_buff :out std_logic_vector(31 downto 0); --Actually loaded data for reading - signal drv_bus :in std_logic_vector(1023 downto 0) --Driving bus from registers - - ); + generic( + buff_size : natural range 4 to 512 + ); + port( + signal clk_sys : in std_logic; + signal res_n : in std_logic; + signal rec_ident_in : in std_logic_vector(28 downto 0); + signal rec_dlc_in : in std_logic_vector(3 downto 0); + signal rec_ident_type_in : in std_logic; + signal rec_frame_type_in : in std_logic; + signal rec_is_rtr : in std_logic; + signal rec_message_valid : in std_logic; + signal rec_brs : in std_logic; + signal rec_esi : in std_logic; + signal rec_message_ack : out std_logic; + signal rec_dram_word : in std_logic_vector(31 downto 0); + signal rec_dram_addr : out natural range 0 to 15; + signal rx_buf_size : out std_logic_vector(7 downto 0); + signal rx_full : out std_logic; + signal rx_empty : out std_logic; + signal rx_message_count : out std_logic_vector(7 downto 0); + signal rx_mem_free : out std_logic_vector(7 downto 0); + signal rx_read_pointer_pos : out std_logic_vector(7 downto 0); + signal rx_write_pointer_pos : out std_logic_vector(7 downto 0); + signal rx_message_disc : out std_logic; + signal rx_data_overrun : out std_logic; + signal timestamp : in std_logic_vector(63 downto 0); + signal rx_read_buff : out std_logic_vector(31 downto 0); + signal drv_bus : in std_logic_vector(1023 downto 0) + ); end component; - - ---------------------- - --TX Buffer module -- - ---------------------- - component txBuffer is - GENERIC ( - buff_size : natural --Only powers of 2 allowed as buff_size!! (32,64,128,256) - ); - PORT( - signal clk_sys :in std_logic; --System clock - signal res_n :in std_logic; --Async Reset - - signal drv_bus :in std_logic_vector(1023 downto 0); --Driving bus from registers - signal tran_data_in :in std_logic_vector(639 downto 0); --Transcieve data - signal tx_buffer_out :out std_logic_vector(639 downto 0); --Output frame with TX buffer structure - signal tx_buffer_valid :out std_logic; --Valid data on the output of TX Buffer - signal tx_buffer_ack :in std_logic; --Acknowledge from TX Arbitrator that message was loaded into CAN Core and can be erased - - signal tx_buff_size :out std_logic_vector(7 downto 0); --Size of transcieve Buffer in 32 bit words - signal tx_full :out std_logic; --Trascieve buffer is full - signal tx_message_count :out std_logic_vector(7 downto 0); --Number of messages in the TX buffer - signal tx_empty :out std_logic; --Buffer empty; - signal tx_mem_free :out std_logic_vector (7 downto 0); --Number of free words in TX counter - signal tx_read_pointer_pos :out std_logic_vector(7 downto 0); --Read pointer value propagated - signal tx_write_pointer_pos :out std_logic_vector(7 downto 0); --Write pointer value propagated - signal tx_message_disc :out std_logic --Signal that acutal message was discarded and not stored for transcieving - ); + ------------------------------------------------------------------------------ + --TX Buffer module + ------------------------------------------------------------------------------ + component txBuffer is + generic ( + buff_size : natural + ); + port( + signal clk_sys : in std_logic; + signal res_n : in std_logic; + signal drv_bus : in std_logic_vector(1023 downto 0); + signal tran_data_in : in std_logic_vector(639 downto 0); + signal tx_buffer_out : out std_logic_vector(639 downto 0); + signal tx_buffer_valid : out std_logic; + signal tx_buffer_ack : in std_logic; + signal tx_buff_size : out std_logic_vector(7 downto 0); + signal tx_full : out std_logic; + signal tx_message_count : out std_logic_vector(7 downto 0); + signal tx_empty : out std_logic; + signal tx_mem_free : out std_logic_vector (7 downto 0); + signal tx_read_pointer_pos : out std_logic_vector(7 downto 0); + signal tx_write_pointer_pos : out std_logic_vector(7 downto 0); + signal tx_message_disc : out std_logic + ); end component; - - ---------------------- - --TXT Buffer module -- - ---------------------- + + ------------------------------------------------------------------------------ + -- TXT Buffer module + ------------------------------------------------------------------------------ component txtBuffer is generic( - constant ID :natural :=1; - constant useFDsize :boolean :=false - ); + constant ID : natural := 1; + constant useFDsize : boolean := false + ); + port( + signal clk_sys : in std_logic; + signal res_n : in std_logic; + signal drv_bus : in std_logic_vector(1023 downto 0); + signal tran_data : in std_logic_vector(31 downto 0); + signal tran_addr : in std_logic_vector(4 downto 0); + signal txt_empty : out std_logic; + signal txt_data_ack : in std_logic; + signal txt_data_word : out std_logic_vector(31 downto 0); + signal txt_data_addr : in natural range 0 to 15; + signal txt_frame_info_out : out std_logic_vector(127 downto 0) + ); + end component; + + ------------------------------------------------------------------------------ + -- TXT Arbitrator module + ------------------------------------------------------------------------------ + component txArbitrator is port( - signal clk_sys :in std_logic; - signal res_n :in std_logic; --Async reset - signal drv_bus :in std_logic_vector(1023 downto 0); --Driving bus - signal tran_data :in std_logic_vector(31 downto 0); --Data into the RAM of TXT Buffer - signal tran_addr :in std_logic_vector(4 downto 0); --Address in the RAM of TXT buffer - signal txt_empty :out std_logic; --Logic 1 signals empty TxTime buffer - signal txt_data_ack :in std_logic; - signal txt_data_word :out std_logic_vector(31 downto 0); - signal txt_data_addr :in natural range 0 to 15; - signal txt_frame_info_out :out std_logic_vector(127 downto 0) - ); - end component; - - ------------------------- - --TXT Arbitrator module-- - ------------------------- - component txArbitrator is - port( - ------------------------ - -- Clock and reset - ------------------------ - signal clk_sys :in std_logic; - signal res_n :in std_logic; - - ------------------------ - --TX Buffers interface-- - ------------------------ - --TXT Buffer 1 - signal txt1buf_info_in :in std_logic_vector(639 downto 512); --Time TX1 buffer input - signal txt1buf_data_in :in std_logic_vector(31 downto 0); --Time TX1 buffer input - signal txt1_buffer_empty :in std_logic; --No message in Time TX Buffer - signal txt1_buffer_ack :out std_logic; --Time buffer acknowledge that - -- message can be erased - - --TXT Buffer 2 - signal txt2buf_info_in :in std_logic_vector(639 downto 512); --Time TX2 buffer input - signal txt2buf_data_in :in std_logic_vector(31 downto 0); --Time TX2 buffer input - signal txt2_buffer_empty :in std_logic; --No message in Time TX Buffer - signal txt2_buffer_ack :out std_logic; --Time buffer acknowledge that - -- message can be erased - ----------------------- - --CAN Core Interface--- - ----------------------- - signal tran_data_word_out :out std_logic_vector(31 downto 0); --TX Message data - signal tran_ident_out :out std_logic_vector(28 downto 0); --TX Identifier - signal tran_dlc_out :out std_logic_vector(3 downto 0); --TX Data length code - signal tran_is_rtr :out std_logic; --TX is remote frame - signal tran_ident_type_out :out std_logic; --TX Identifier type (0-Basic,1-Extended); - signal tran_frame_type_out :out std_logic; --TX Frame type - signal tran_brs_out :out std_logic; --Bit rate shift for CAN FD frames - signal tran_frame_valid_out :out std_logic; --Signal for CAN Core that frame on the - -- output is valid and can be stored for transmitting - -- Acknowledge from CAN core that frame transmission started and - -- that frame informations were stored - signal tran_data_ack :in std_logic; - - -- Acknowledge that CAN core that frame was succesfully transmitted - -- and can be erased. - signal tran_valid :in std_logic; - - --------------------- - --Driving interface-- - --------------------- - signal drv_bus :in std_logic_vector(1023 downto 0); --Driving bus from registers - signal timestamp :in std_logic_vector(63 downto 0) --TimeStamp value - - ); + signal clk_sys : in std_logic; + signal res_n : in std_logic; + signal txt1buf_info_in : in std_logic_vector(639 downto 512); + signal txt1buf_data_in : in std_logic_vector(31 downto 0); + signal txt1_buffer_empty : in std_logic; + signal txt1_buffer_ack : out std_logic; + signal txt2buf_info_in : in std_logic_vector(639 downto 512); + signal txt2buf_data_in : in std_logic_vector(31 downto 0); + signal txt2_buffer_empty : in std_logic; + signal txt2_buffer_ack : out std_logic; + signal tran_data_word_out : out std_logic_vector(31 downto 0); + signal tran_ident_out : out std_logic_vector(28 downto 0); + signal tran_dlc_out : out std_logic_vector(3 downto 0); + signal tran_is_rtr : out std_logic; + signal tran_ident_type_out : out std_logic; + signal tran_frame_type_out : out std_logic; + signal tran_brs_out : out std_logic; + signal tran_frame_valid_out : out std_logic; + signal tran_data_ack : in std_logic; + signal tran_valid : in std_logic; + signal drv_bus : in std_logic_vector(1023 downto 0); + signal timestamp : in std_logic_vector(63 downto 0) + ); end component; - - ------------------------- - --Message filter module-- - ------------------------- + + ------------------------------------------------------------------------------ + -- Message filter module + ------------------------------------------------------------------------------ component messageFilter is - generic - ( - constant sup_filtA :boolean := true; --Optional synthesis of received message filters - constant sup_filtB :boolean := true; -- By default the behaviour is as if all the filters are present - constant sup_filtC :boolean := true; - constant sup_range :boolean := true - ); - PORT( - signal clk_sys :in std_logic; --System clock - signal res_n :in std_logic; --Async reset - - signal rec_ident_in :in std_logic_vector(28 downto 0);--Receieved identifier - signal ident_type :in std_logic; --Input message identifier type (0-BASE Format, 1-Extended Format); - signal frame_type :in std_logic; --Input frame type (0-Normal CAN, 1- CAN FD) - signal rec_ident_valid :in std_logic; --Identifier valid (active log 1) - - signal drv_bus :in std_logic_vector(1023 downto 0); - - signal out_ident_valid :out std_logic --Signal whenever identifier matches the filter identifiers - ); + generic + ( + constant sup_filtA : boolean := true; + constant sup_filtB : boolean := true; + constant sup_filtC : boolean := true; + constant sup_range : boolean := true + ); + port( + signal clk_sys : in std_logic; + signal res_n : in std_logic; + signal rec_ident_in : in std_logic_vector(28 downto 0); + signal ident_type : in std_logic; + signal frame_type : in std_logic; + signal rec_ident_valid : in std_logic; + signal drv_bus : in std_logic_vector(1023 downto 0); + signal out_ident_valid : out std_logic + ); end component; - - ---------------------------- - --Interrupt manager module-- - ---------------------------- - component intManager is - GENERIC( - constant int_length : natural range 0 to 10:=5 --Lenght in clock cycles how long will interrupt stay active - ); - PORT( - signal clk_sys :in std_logic; --System Clock - signal res_n :in std_logic; --Async Reset - - signal error_valid :in std_logic; --Valid Error appeared for interrupt - signal error_passive_changed:in std_logic; --Error pasive /Error acitve functionality changed - signal error_warning_limit :in std_logic; --Error warning limit reached - - signal arbitration_lost :in std_logic; --Arbitration was lost input - signal wake_up_valid :in std_logic; --Wake up appeared - signal tx_finished :in std_logic; --Message stored in CAN Core was sucessfully transmitted - signal br_shifted :in std_logic; --Bit Rate Was Shifted - - signal rx_message_disc :in std_logic; --Income message was discarded - signal rec_message_valid :in std_logic; --Message recieved! - --Note : use the "out_ident_valid" signal of messageFilters. Therefore only - --interrupt is started for signals which pass income filters - - signal rx_full :in std_logic; --RX Buffer is full (the last income message filled the remaining space) - --NOTE! rec_message_valid will be in logic one for two clock cycles - signal loger_finished :in std_logic; --Event logging finsihed - signal drv_bus :in std_logic_vector(1023 downto 0); - signal int_out :out std_logic; --Interrupt output - - signal int_vector :out std_logic_vector(10 downto 0) --Interrupt vector (Interrupt register of SJA1000) - ); - end component; - - -------------------- - --CAN Core module -- - -------------------- - component core_top is - PORT( - signal clk_sys :in std_logic; - signal res_n :in std_logic; - - signal drv_bus :in std_logic_vector(1023 downto 0); - signal stat_bus :out std_logic_vector(511 downto 0); - - signal tran_data_in :in std_logic_vector(31 downto 0); - signal tran_ident_in :in std_logic_vector(28 downto 0); - signal tran_dlc_in :in std_logic_vector(3 downto 0); - signal tran_is_rtr_in :in std_logic; - signal tran_ident_type_in :in std_logic; --TX Identifier type (0-Basic,1-Extended); - signal tran_frame_type_in :in std_logic; --TX Frame type (0-CAN Normal, 1-CAN FD) - signal tran_brs_in :in std_logic; --Frame should be transcieved with BRS value - signal tran_frame_valid_in :in std_logic; --Signal for CAN Core that frame on the output is valid and can be stored for transmitting - signal tran_data_ack_out :out std_logic; --Acknowledge from CAN core that acutal message was stored into internal buffer for transmitting - signal txt_buf_ptr :out natural range 0 to 15; --Pointer to TXT buffer memory - - signal rec_ident_out :out std_logic_vector(28 downto 0); --Message Identifier - signal rec_dlc_out :out std_logic_vector(3 downto 0); --Data length code - signal rec_ident_type_out :out std_logic; --Recieved identifier type (0-BASE Format, 1-Extended Format); - signal rec_frame_type_out :out std_logic; --Recieved frame type (0-Normal CAN, 1- CAN FD) - signal rec_is_rtr_out :out std_logic; --Recieved frame is RTR Frame(0-No, 1-Yes) - signal rec_brs_out :out std_logic; --Frame was recieved with Bit rate shift - signal rec_esi_out :out std_logic; --Error state indicator - signal rec_message_valid_out:out std_logic; - signal rec_message_ack_out :in std_logic; --Acknowledge for CAN Core about accepted data - signal rec_dram_word_out :out std_logic_vector(31 downto 0); - signal rec_dram_addr_out :in natural range 0 to 15; - - signal arbitration_lost_out :out std_logic; --Arbitration was lost input - signal wake_up_valid :out std_logic; --Wake up appeared - signal tx_finished :out std_logic; --Message stored in CAN Core was sucessfully transmitted - signal br_shifted :out std_logic; --Bit Rate Was Shifted - - signal error_valid :out std_logic; --At least one error appeared - signal error_passive_changed:out std_logic; --Error passive state changed - signal error_warning_limit :out std_logic; --Error warning limit was reached - - signal sample_nbt_del_2 :in std_logic; --Sampling signal 2 clk_sys delayed from sample_nbt - signal sample_dbt_del_2 :in std_logic; --Sampling signal 2 clk_sys delayed from sample_dbt - signal sample_nbt_del_1 :in std_logic; --Sampling signal of NBT for Bit destuffing - signal sample_dbt_del_1 :in std_logic; --Sampling signal of DBT for Bit destuffing - signal sync_nbt :in std_logic; --Beginning of Nominal bit time (transcieving next bit) - signal sync_dbt :in std_logic; --Beginning of Data bit time (transcieving next bit) - signal sync_nbt_del_1 :in std_logic; --Bit stuffing trigger NBT - signal sync_dbt_del_1 :in std_logic; --Bit Stuffing trigger DBT - - signal sample_sec :in std_logic; --Secondary sample signal - signal sample_sec_del_1 :in std_logic; --Bit destuffing trigger for secondary sample point - signal sample_sec_del_2 :in std_logic; --Rec trig for secondary sample point - - signal sync_control :out std_logic_vector(1 downto 0); --Synchronisation control signal (Hard sync, Re Sync) - - signal data_rx :in std_logic; --Recieved data input (valid with sample_nbt_del_1) - signal data_tx :out std_logic; --Data transcieved on CAN Bus (valid with sync_nbt_del_1) - - signal timestamp :in std_logic_vector(63 downto 0); - - signal sp_control :out std_logic_vector(1 downto 0); --Control signal for Sampling source - signal ssp_reset :out std_logic; --Secondary sample point reset - signal trv_delay_calib :out std_logic; --Enable calibration of transciever delay compenstation - signal bit_Error_sec_sam :in std_logic; --Bit error with secondary sampling transciever! - signal hard_sync_edge :in std_logic - ); + ------------------------------------------------------------------------------ + -- Interrupt manager module + ------------------------------------------------------------------------------ + component intManager is + generic( + constant int_length : natural range 0 to 10 := 5 + ); + port( + signal clk_sys : in std_logic; + signal res_n : in std_logic; + signal error_valid : in std_logic; + signal error_passive_changed : in std_logic; + signal error_warning_limit : in std_logic; + signal arbitration_lost : in std_logic; + signal wake_up_valid : in std_logic; + signal tx_finished : in std_logic; + signal br_shifted : in std_logic; + signal rx_message_disc : in std_logic; + signal rec_message_valid : in std_logic; + signal rx_full : in std_logic; + signal loger_finished : in std_logic; + signal drv_bus : in std_logic_vector(1023 downto 0); + signal int_out : out std_logic; + signal int_vector : out std_logic_vector(10 downto 0) + ); + end component; + + ------------------------------------------------------------------------------ + --CAN Core module -- + ------------------------------------------------------------------------------ + component core_top is + port( + signal clk_sys : in std_logic; + signal res_n : in std_logic; + signal drv_bus : in std_logic_vector(1023 downto 0); + signal stat_bus : out std_logic_vector(511 downto 0); + signal tran_data_in : in std_logic_vector(31 downto 0); + signal tran_ident_in : in std_logic_vector(28 downto 0); + signal tran_dlc_in : in std_logic_vector(3 downto 0); + signal tran_is_rtr_in : in std_logic; + signal tran_ident_type_in : in std_logic; + signal tran_frame_type_in : in std_logic; + signal tran_brs_in : in std_logic; + signal tran_frame_valid_in : in std_logic; + signal tran_data_ack_out : out std_logic; + signal txt_buf_ptr : out natural range 0 to 15; + signal rec_ident_out : out std_logic_vector(28 downto 0); + signal rec_dlc_out : out std_logic_vector(3 downto 0); + signal rec_ident_type_out : out std_logic; + signal rec_frame_type_out : out std_logic; + signal rec_is_rtr_out : out std_logic; + signal rec_brs_out : out std_logic; + signal rec_esi_out : out std_logic; + signal rec_message_valid_out : out std_logic; + signal rec_message_ack_out : in std_logic; + signal rec_dram_word_out : out std_logic_vector(31 downto 0); + signal rec_dram_addr_out : in natural range 0 to 15; + signal arbitration_lost_out : out std_logic; + signal wake_up_valid : out std_logic; + signal tx_finished : out std_logic; + signal br_shifted : out std_logic; + signal error_valid : out std_logic; + signal error_passive_changed : out std_logic; + signal error_warning_limit : out std_logic; + signal sample_nbt_del_2 : in std_logic; + signal sample_dbt_del_2 : in std_logic; + signal sample_nbt_del_1 : in std_logic; + signal sample_dbt_del_1 : in std_logic; + signal sync_nbt : in std_logic; + signal sync_dbt : in std_logic; + signal sync_nbt_del_1 : in std_logic; + signal sync_dbt_del_1 : in std_logic; + signal sample_sec : in std_logic; + signal sample_sec_del_1 : in std_logic; + signal sample_sec_del_2 : in std_logic; + signal sync_control : out std_logic_vector(1 downto 0); + signal data_rx : in std_logic; + signal data_tx : out std_logic; + signal timestamp : in std_logic_vector(63 downto 0); + signal sp_control : out std_logic_vector(1 downto 0); + signal ssp_reset : out std_logic; + signal trv_delay_calib : out std_logic; + signal bit_Error_sec_sam : in std_logic; + signal hard_sync_edge : in std_logic + ); end component; - - --------------------- - --Prescaler module -- - --------------------- + + ------------------------------------------------------------------------------ + -- Prescaler module + ------------------------------------------------------------------------------ component prescaler_v3 is - PORT( - signal clk_sys :in std_logic; --System clock - signal res_n :in std_logic; --Async reset - - signal sync_edge :in std_logic; --Edge for synchronisation - signal OP_State :in oper_mode_type; --Protocol control state - - signal drv_bus :in std_logic_vector(1023 downto 0); - - signal clk_tq_nbt :out std_logic; --Time quantum clock - Nominal bit time - signal clk_tq_dbt :out std_logic; --bit time - Nominal bit time - - signal sample_nbt :out std_logic; --Sample signal for nominal bit time - signal sample_dbt :out std_logic; --Sample signal of data bit time - signal sample_nbt_del_1 :out std_logic; - signal sample_dbt_del_1 :out std_logic; - signal sample_nbt_del_2 :out std_logic; - signal sample_dbt_del_2 :out std_logic; - - signal sync_nbt :out std_logic; - signal sync_dbt :out std_logic; - signal sync_nbt_del_1 :out std_logic; - signal sync_dbt_del_1 :out std_logic; - signal bt_FSM_out :out bit_time_type; - - signal data_tx :in std_logic; - - signal hard_sync_edge_valid :out std_logic; --Validated hard synchronisation edge to start Protocol control FSM - --Note: Sync edge from busSync.vhd cant be used! If it comes during sample nbt, sequence it causes - -- errors! It needs to be strictly before or strictly after this sequence!!! - - signal sp_control :in std_logic_vector(1 downto 0); - signal sync_control :in std_logic_vector(1 downto 0) - ); + port( + signal clk_sys : in std_logic; + signal res_n : in std_logic; + signal sync_edge : in std_logic; + signal OP_State : in oper_mode_type; + signal drv_bus : in std_logic_vector(1023 downto 0); + signal clk_tq_nbt : out std_logic; + signal clk_tq_dbt : out std_logic; + signal sample_nbt : out std_logic; + signal sample_dbt : out std_logic; + signal sample_nbt_del_1 : out std_logic; + signal sample_dbt_del_1 : out std_logic; + signal sample_nbt_del_2 : out std_logic; + signal sample_dbt_del_2 : out std_logic; + signal sync_nbt : out std_logic; + signal sync_dbt : out std_logic; + signal sync_nbt_del_1 : out std_logic; + signal sync_dbt_del_1 : out std_logic; + signal bt_FSM_out : out bit_time_type; + signal data_tx : in std_logic; + signal hard_sync_edge_valid : out std_logic; + signal sp_control : in std_logic_vector(1 downto 0); + signal sync_control : in std_logic_vector(1 downto 0) + ); + end component; + + ------------------------------------------------------------------------------ + -- Bus synchroniser module + ------------------------------------------------------------------------------ + component busSync is + generic ( + use_Sync : boolean + ); + port( + signal clk_sys : in std_logic; + signal res_n : in std_logic; + signal CAN_rx : in std_logic; + signal CAN_tx : out std_logic; + signal drv_bus : in std_logic_vector(1023 downto 0); + signal sample_nbt : in std_logic; + signal sample_dbt : in std_logic; + signal sync_edge : out std_logic; + signal data_tx : in std_logic; + signal data_rx : out std_logic; + signal sp_control : in std_logic_vector(1 downto 0); + signal ssp_reset : in std_logic; + signal trv_delay_calib : in std_logic; + signal bit_err_enable : in std_logic; + signal sample_sec_out : out std_logic; + signal sample_sec_del_1_out : out std_logic; + signal sample_sec_del_2_out : out std_logic; + signal trv_delay_out : out std_logic_vector(15 downto 0); + signal bit_Error : out std_logic + ); end component; - - ---------------------------- - --Bus synchroniser module-- - --------------------------- - component busSync is - GENERIC ( - use_Sync : boolean - --Whenever Synchronisation chain should be used for sampled data from the bus. - --Turn off only when Synthetizer puts synchronisation chain automatically on the - --output pins! Otherwise metastability issues will occur! - ); - PORT( - signal clk_sys :in std_logic; --System clock - signal res_n :in std_logic; --Async Reset - - signal CAN_rx :in std_logic; --CAN data input from transciever - signal CAN_tx :out std_logic; --CAN data output to transciever - - signal drv_bus :in std_logic_vector(1023 downto 0); --Driving bus - - signal sample_nbt :in std_logic; --Sample command for nominal bit time - signal sample_dbt :in std_logic; --Sample command for data bit tim - signal sync_edge :out std_logic; --Synchronisation edge appeared - - signal data_tx :in std_logic; --Transcieve data value - signal data_rx :out std_logic; --Recieved data value - - signal sp_control :in std_logic_vector(1 downto 0); --Control sequence for sampling - --00:sample_nbt used for sampling (Nominal bit time sampling, Transciever and Reciever) - --01:sample_dbt used for sampling (Data bit time sampling, only Reciever) - --10:Sampling with transciever delay compensation (Data bit time, transciever) - signal ssp_reset :in std_logic; --Clear the Shift register at the beginning of Data Phase!!! - signal trv_delay_calib :in std_logic; --Calibration command for transciever delay compenstation (counter) - - signal bit_err_enable :in std_logic; - - signal sample_sec_out :out std_logic; --Secondary sample signal - signal sample_sec_del_1_out :out std_logic; --Bit destuffing trigger for secondary sample point - signal sample_sec_del_2_out :out std_logic; --Rec trig for secondary sample point - - signal trv_delay_out :out std_logic_vector(15 downto 0); - - signal bit_Error :out std_logic --Bit Error appeared (monitored value different than transcieved value) - ); + + ------------------------------------------------------------------------------ + -- CAN Logger module + ------------------------------------------------------------------------------ + component CAN_logger is + generic( + constant memory_size : natural := 16 + ); + port( + signal clk_sys : in std_logic; + signal res_n : in std_logic; + signal drv_bus : in std_logic_vector(1023 downto 0); + signal stat_bus : in std_logic_vector(511 downto 0); + signal sync_edge : in std_logic; + signal data_overrun : in std_logic; + signal timestamp : in std_logic_vector(63 downto 0); + signal bt_FSM : in bit_time_type; + signal loger_finished : out std_logic; + signal loger_act_data : out std_logic_vector(63 downto 0); + signal log_write_pointer : out std_logic_vector(7 downto 0); + signal log_read_pointer : out std_logic_vector(7 downto 0); + signal log_size : out std_logic_vector(7 downto 0); + signal log_state_out : out logger_state_type + ); end component; - - component CAN_logger is - generic( - constant memory_size : natural:=16 --Only 2^k possible! - ); - port( - signal clk_sys :in std_logic; - signal res_n :in std_logic; - - signal drv_bus :in std_logic_vector(1023 downto 0); - signal stat_bus :in std_logic_vector(511 downto 0); - signal sync_edge :in std_logic; - signal data_overrun :in std_logic; - signal timestamp :in std_logic_vector(63 downto 0); - signal bt_FSM :in bit_time_type; - - signal loger_finished :out std_logic; --Logger finished interrrupt output - signal loger_act_data :out std_logic_vector(63 downto 0); - signal log_write_pointer :out std_logic_vector(7 downto 0); - signal log_read_pointer :out std_logic_vector(7 downto 0); - signal log_size :out std_logic_vector(7 downto 0); - signal log_state_out :out logger_state_type - - ); -end component; - - - -------------------------------------------------------------------------------- - -------------------------------------------------------------------------------- + + + ------------------------------------------------------------------------------ + ------------------------------------------------------------------------------ ---- CORE Top level components - -------------------------------------------------------------------------------- - -------------------------------------------------------------------------------- - - --------------- - --CRC module -- - --------------- + ------------------------------------------------------------------------------ + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + -- CRC module + ------------------------------------------------------------------------------ component canCRC is - generic( - constant crc15_pol : std_logic_vector(15 downto 0):=std_logic_vector'(X"C599"); - constant crc17_pol : std_logic_vector(19 downto 0):=std_logic_vector'(X"3685B"); - constant crc21_pol : std_logic_vector(23 downto 0):=std_logic_vector'(X"302899") - ); - port( - signal data_in :in std_logic; --Serial data input - signal clk_sys :in std_logic; --System clock input - - --Trigger to sample the input value . Note: Trigger generated by prescaler - --Note 2: trigger for CAN FD should be 1 clk_sys behind normal CAN since for CAN FD bit stuffing is made - --before CRC calculation - signal trig :in std_logic; - - --Asynchronous reset - signal res_n :in std_logic; - - --By transition from 0 to 1 on enable sampled on clk_sys rising edge (and with trig='1') - --operation is started. First bit of data already has to be on data_in input. - --Circuit works as long as enable=1. - signal enable :in std_logic; - signal drv_bus :in std_logic_vector(1023 downto 0); - - signal crc15 :out std_logic_vector(14 downto 0); - signal crc17 :out std_logic_vector(16 downto 0); - signal crc21 :out std_logic_vector(20 downto 0) - ); + generic( + constant crc15_pol : std_logic_vector(15 downto 0) := x"C599"; + constant crc17_pol : std_logic_vector(19 downto 0) := x"3685B"; + constant crc21_pol : std_logic_vector(23 downto 0) := x"302899" + ); + port( + signal data_in : in std_logic; + signal clk_sys : in std_logic; + signal trig : in std_logic; + signal res_n : in std_logic; + signal enable : in std_logic; + signal drv_bus : in std_logic_vector(1023 downto 0); + signal crc15 : out std_logic_vector(14 downto 0); + signal crc17 : out std_logic_vector(16 downto 0); + signal crc21 : out std_logic_vector(20 downto 0) + ); end component; - - --------------------- - --Transcieve buffer-- - --------------------- - component tranBuffer is - port( - signal clk_sys :in std_logic; --System clock - signal res_n :in std_logic; - - signal tran_ident_in :in std_logic_vector(28 downto 0); - signal tran_dlc_in :in std_logic_vector(3 downto 0); - signal tran_is_rtr_in :in std_logic; - signal tran_ident_type_in :in std_logic; --TX Identifier type (0-Basic,1-Extended); - signal tran_frame_type_in :in std_logic; --TX Frame type (0-CAN Normal, 1-CAN FD) - signal tran_brs_in :in std_logic; - - signal frame_store :in std_logic; --Store the data on input - - signal tran_ident :out std_logic_vector(28 downto 0); - signal tran_dlc :out std_logic_vector(3 downto 0); - signal tran_is_rtr :out std_logic; - signal tran_ident_type :out std_logic; - signal tran_frame_type :out std_logic; - signal tran_brs :out std_logic - ); + + ------------------------------------------------------------------------------ + -- Transcieve buffer + ------------------------------------------------------------------------------ + component tranBuffer is + port( + signal clk_sys : in std_logic; + signal res_n : in std_logic; + signal tran_ident_in : in std_logic_vector(28 downto 0); + signal tran_dlc_in : in std_logic_vector(3 downto 0); + signal tran_is_rtr_in : in std_logic; + signal tran_ident_type_in : in std_logic; + signal tran_frame_type_in : in std_logic; + signal tran_brs_in : in std_logic; + signal frame_store : in std_logic; + signal tran_ident : out std_logic_vector(28 downto 0); + signal tran_dlc : out std_logic_vector(3 downto 0); + signal tran_is_rtr : out std_logic; + signal tran_ident_type : out std_logic; + signal tran_frame_type : out std_logic; + signal tran_brs : out std_logic + ); end component; - ----------------- - --Bit Stuffing -- - ----------------- - component bitStuffing_v2 is - port( - signal clk_sys :in std_logic; - signal res_n :in std_logic; - signal tran_trig_1 :in std_logic; --Trigger signal for propagating the data (one clk_sys delayed behind beginning of bit time) - signal enable :in std_logic; --Enabling the operation of the circuit - signal data_in :in std_logic; --Data Input sampled - signal fixed_stuff :in std_logic; --Whenever fixed bit stuffing should be used (CAN FD Option) - signal data_halt :out std_logic; --Logic 1 signals stuffed bit for CAN Core. CAN Core has to halt the data sending for one bit-time - signal length :in std_logic_vector(2 downto 0); --Length of Bit Stuffing - signal bst_ctr :out natural range 0 to 7; --Bit stuffing counter - signal data_out :out std_logic --Data output - ); + ------------------------------------------------------------------------------ + -- Bit Stuffing + ------------------------------------------------------------------------------ + component bitStuffing_v2 is + port( + signal clk_sys : in std_logic; + signal res_n : in std_logic; + signal tran_trig_1 : in std_logic; + signal enable : in std_logic; + signal data_in : in std_logic; + signal fixed_stuff : in std_logic; + signal data_halt : out std_logic; + signal length : in std_logic_vector(2 downto 0); + signal bst_ctr : out natural range 0 to 7; + signal data_out : out std_logic + ); end component; - - ------------------ - --Bit Destuffing-- - ------------------ + + ------------------------------------------------------------------------------ + -- Bit Destuffing + ------------------------------------------------------------------------------ component bitDestuffing is - PORT( - signal clk_sys :in std_logic; --System clock - signal res_n :in std_logic; --Async Reset - signal data_in :in std_logic; --Sampled data from busSync.vhd - signal trig_spl_1 :in std_logic; --Triggering signal with one clk_sys delay behind the used sampling signal - signal stuff_Error :out std_logic; --Stuff Error - signal data_out :out std_logic; --Data output for CAN Core - signal destuffed :out std_logic; --Signal that data on output are not valid but it is a stuff bit - signal enable :in std_logic; --Enable of the circuit - signal stuff_Error_enable :in std_logic; --Enable stuff Error logging - signal fixed_stuff :in std_logic; --Whenever fixed bit Destuffing method is used - signal length :in std_logic_vector(2 downto 0); --Length of bit stuffing rule - signal dst_ctr :out natural range 0 to 7 --Bit destuffing length - ); + port( + signal clk_sys : in std_logic; + signal res_n : in std_logic; + signal data_in : in std_logic; + signal trig_spl_1 : in std_logic; + signal stuff_Error : out std_logic; + signal data_out : out std_logic; + signal destuffed : out std_logic; + signal enable : in std_logic; + signal stuff_Error_enable : in std_logic; + signal fixed_stuff : in std_logic; + signal length : in std_logic_vector(2 downto 0); + signal dst_ctr : out natural range 0 to 7 + ); end component; - - ------------------------- - --Operation control FSM-- - ------------------------- + + ------------------------------------------------------------------------------ + -- Operation control FSM + ------------------------------------------------------------------------------ component operationControl is - PORT( - signal clk_sys :in std_logic; - signal res_n :in std_logic; - signal drv_bus :in std_logic_vector(1023 downto 0); - signal arbitration_lost :in std_logic; - signal PC_State :in protocol_type; - signal tran_data_valid_in :in std_logic; - signal set_transciever :in std_logic; --Set OP_State FSM into transciever state (Used at SOF) - signal set_reciever :in std_logic; --Set OP_State FSM into reciever state - signal is_idle :in std_logic; --Unit is idle - signal tran_trig :in std_logic; - signal rec_trig :in std_logic; - signal data_rx : std_logic; - signal OP_State :out oper_mode_type - ); + port( + signal clk_sys : in std_logic; + signal res_n : in std_logic; + signal drv_bus : in std_logic_vector(1023 downto 0); + signal arbitration_lost : in std_logic; + signal PC_State : in protocol_type; + signal tran_data_valid_in : in std_logic; + signal set_transciever : in std_logic; + signal set_reciever : in std_logic; + signal is_idle : in std_logic; + signal tran_trig : in std_logic; + signal rec_trig : in std_logic; + signal data_rx : std_logic; + signal OP_State : out oper_mode_type + ); end component; - - ------------------------ - --Protocol Control FSM-- - ------------------------ + + ------------------------------------------------------------------------------ + -- Protocol Control FSM + ------------------------------------------------------------------------------ component protocolControl is - port( - signal clk_sys :in std_logic; --System clock - signal res_n :in std_logic; --Async reset - signal drv_bus :in std_logic_vector(1023 downto 0); --Driving bus signals - - signal int_loop_back_ena :out std_logic; --Internal loopBack enabled (for Bus monitoring mode) - signal PC_State_out :out protocol_type; - signal alc :out std_logic_vector(4 downto 0); - - signal tran_data :in std_logic_vector(31 downto 0); - signal tran_ident :in std_logic_vector(28 downto 0); - signal tran_dlc :in std_logic_vector(3 downto 0); - signal tran_is_rtr :in std_logic; - signal tran_ident_type :in std_logic; - signal tran_frame_type :in std_logic; - signal tran_brs :in std_logic; - signal txt_buf_ptr :out natural range 0 to 15; --Pointer to TXT buffer memory - - signal frame_store :out std_logic; --Store frame from TX Arbitrator to the Transcieve Buffer - signal tran_frame_valid_in :in std_logic; --Valid frame ready to be stored into Transcieeve Buffer - signal tran_data_ack :out std_logic; --Acknowledge that the frame was stored - signal br_shifted :out std_logic; --Bit Rate Was Shifted - - signal rec_ident :out std_logic_vector(28 downto 0); - signal rec_dlc :out std_logic_vector(3 downto 0); - signal rec_is_rtr :out std_logic; - signal rec_ident_type :out std_logic; - signal rec_frame_type :out std_logic; - signal rec_brs :out std_logic; - signal rec_crc :out std_logic_vector(20 downto 0); --Recieved CRC value - signal rec_esi :out std_logic; --Recieved Error state indicator - - --Added interface for aux SRAM - signal rec_dram_word :out std_logic_vector(31 downto 0); - signal rec_dram_addr :in natural range 0 to 15; - - signal OP_state :in oper_mode_type; --Operation mode state - signal arbitration_lost :out std_logic; --Signal for Operational mode state mahine about loosing arbitration - signal is_idle :out std_logic; --Signal to indicate transcieve or recieve finished and bus is idle - signal set_transciever :out std_logic; --Set OP_State FSM into transciever state (Used at SOF) - signal set_reciever :out std_logic; --Set OP_State FSM into reciever state - - signal ack_recieved_out :out std_logic; - - signal error_state :in error_state_type; --Fault confinement state - --Error signals for fault confinement - signal form_Error :out std_logic; --Form Error - signal CRC_Error :out std_logic; --CRC Error - signal ack_Error :out std_logic; --Acknowledge error - signal unknown_state_Error :out std_logic; --Some of the state machines, or signals reached unknown state!! Shouldnt happend!! - signal bit_stuff_Error_valid :in std_logic; --Error signal for PC control FSM from fault confinement unit (Bit error or Stuff Error appeared) - - --Note: New Interface for fault confinement incrementation - signal inc_one :out std_logic; - signal inc_eight :out std_logic; - signal dec_one :out std_logic; - - signal tran_valid :out std_logic; - signal rec_valid :out std_logic; - - signal tran_trig :in std_logic; --Transcieve triggerring signal (sync_nbt,sync_dbt) ->multiplexed in core_top (CAN Core) - signal rec_trig :in std_logic; --Recieve triggerring signal (sample_2_nbt,sample_2_dbt) ->multiplexed in core_top - - signal data_tx :out std_logic; --Transcieved data on CAN Bus - signal stuff_enable :out std_logic; - signal fixed_stuff :out std_logic; --Log 1 - Fixed Stuffing, Log 0 - Normal stuffing - signal stuff_length :out std_logic_vector(2 downto 0); --Stuffing length - signal data_rx :in std_logic; --Recieved data - signal destuff_enable :out std_logic; --Enabling destuffing - signal stuff_error_enable :out std_logic; --Enabling firing of destuffing error - signal fixed_destuff :out std_logic; --Fixed stuffing method (log. 1), Normal stuffing (log 0); - signal destuff_length :out std_logic_vector(2 downto 0); --Number of equal consequent bits before destuffed bit - signal dst_ctr :in natural range 0 to 7; --Number of stuffed bits modulo 8 - - signal crc_enable :out std_logic; --Transition from 0 to 1 erases the CRC and operation holds as long as enable=1 - signal crc15 :in std_logic_vector(14 downto 0); --CRC 15 - signal crc17 :in std_logic_vector(16 downto 0); --CRC 17 - signal crc21 :in std_logic_vector(20 downto 0); --CRC 21 - - signal sync_control :out std_logic_vector(1 downto 0); --00-no synchronisation, 10-Hard synchronisation, 11-Resynchronisation - - signal sp_control :out std_logic_vector(1 downto 0); --00 nominal, 01-data, 10 -secondary - signal ssp_reset :out std_logic; --Clear the Shift register at the beginning of Data Phase!!! - signal trv_delay_calib :out std_logic; --Calibration command for transciever delay compenstation (counter) - signal bit_err_enable :out std_logic; --Bit Error detection enable (Ex. disabled when recieving data) - signal hard_sync_edge :in std_logic - ); + port( + signal clk_sys : in std_logic; + signal res_n : in std_logic; + signal drv_bus : in std_logic_vector(1023 downto 0); + signal int_loop_back_ena : out std_logic; + signal PC_State_out : out protocol_type; + signal alc : out std_logic_vector(4 downto 0); + signal tran_data : in std_logic_vector(31 downto 0); + signal tran_ident : in std_logic_vector(28 downto 0); + signal tran_dlc : in std_logic_vector(3 downto 0); + signal tran_is_rtr : in std_logic; + signal tran_ident_type : in std_logic; + signal tran_frame_type : in std_logic; + signal tran_brs : in std_logic; + signal txt_buf_ptr : out natural range 0 to 15; + signal frame_store : out std_logic; + signal tran_frame_valid_in : in std_logic; + signal tran_data_ack : out std_logic; + signal br_shifted : out std_logic; + signal rec_ident : out std_logic_vector(28 downto 0); + signal rec_dlc : out std_logic_vector(3 downto 0); + signal rec_is_rtr : out std_logic; + signal rec_ident_type : out std_logic; + signal rec_frame_type : out std_logic; + signal rec_brs : out std_logic; + signal rec_crc : out std_logic_vector(20 downto 0); + signal rec_esi : out std_logic; + signal rec_dram_word : out std_logic_vector(31 downto 0); + signal rec_dram_addr : in natural range 0 to 15; + signal OP_state : in oper_mode_type; + signal arbitration_lost : out std_logic; + signal is_idle : out std_logic; + signal set_transciever : out std_logic; + signal set_reciever : out std_logic; + signal ack_recieved_out : out std_logic; + signal error_state : in error_state_type; + signal form_Error : out std_logic; + signal CRC_Error : out std_logic; + signal ack_Error : out std_logic; + signal unknown_state_Error : out std_logic; + signal bit_stuff_Error_valid : in std_logic; + signal inc_one : out std_logic; + signal inc_eight : out std_logic; + signal dec_one : out std_logic; + signal tran_valid : out std_logic; + signal rec_valid : out std_logic; + signal tran_trig : in std_logic; + signal rec_trig : in std_logic; + signal data_tx : out std_logic; + signal stuff_enable : out std_logic; + signal fixed_stuff : out std_logic; + signal stuff_length : out std_logic_vector(2 downto 0); + signal data_rx : in std_logic; + signal destuff_enable : out std_logic; + signal stuff_error_enable : out std_logic; + signal fixed_destuff : out std_logic; + signal destuff_length : out std_logic_vector(2 downto 0); + signal dst_ctr : in natural range 0 to 7; + signal crc_enable : out std_logic; + signal crc15 : in std_logic_vector(14 downto 0); + signal crc17 : in std_logic_vector(16 downto 0); + signal crc21 : in std_logic_vector(20 downto 0); + signal sync_control : out std_logic_vector(1 downto 0); + signal sp_control : out std_logic_vector(1 downto 0); + signal ssp_reset : out std_logic; + signal trv_delay_calib : out std_logic; + signal bit_err_enable : out std_logic; + signal hard_sync_edge : in std_logic + ); end component; - ------------------------ - --Fault confinement -- - ------------------------ - component faultConf is - PORT( - signal clk_sys :in std_logic; --System clock - signal res_n :in std_logic; --Async reset - signal drv_bus :in std_logic_vector(1023 downto 0); - - signal stuff_Error :in std_logic; --Stuffing Error from bit destuffing - - signal error_valid :out std_logic; --At least one error appeared - signal error_passive_changed :out std_logic; --Error passive state changed - signal error_warning_limit :out std_logic; --Error warning limit was reached - - signal OP_State :in oper_mode_type; - - signal data_rx :in std_logic; --Recieved data. Valid with the same signal as rec_trig in CAN Core - signal data_tx :in std_logic; --Transcieved data by CAN Core. Valid with one clk_sys delay from tran_trig! The same trigger signal as Bit-Stuffing! - signal rec_trig :in std_logic; --Recieve data trigger - signal tran_trig_1 :in std_logic; --Transcieve data trigger one clk_sys delayed behind the tran_trig - - signal PC_State :in protocol_type; - signal sp_control :in std_logic_vector(1 downto 0); - signal form_Error :in std_logic; --Form Error from PC State - signal CRC_Error :in std_logic; --CRC Error from PC State - signal ack_Error :in std_logic; --Acknowledge Error from PC State - signal unknown_state_Error :in std_logic; --Some of the state machines, or signals reached unknown state!! Shouldnt happend!! - signal bit_stuff_Error_valid :out std_logic; --Error signal for PC control FSM from fault confinement unit (Bit error or Stuff Error appeared) - - --Note: This new interface is used for error incrementation, decrementation!! - signal inc_one :in std_logic; - signal inc_eight :in std_logic; - signal dec_one :in std_logic; - - signal enable :in std_logic; --Enable for error counting - signal bit_Error_sec_sam :in std_logic; --Bit Error detected with secondary sampling point at busSync.vhd - signal bit_Error_out :out std_logic; - - signal tx_counter_out :out std_logic_vector(8 downto 0); - signal rx_counter_out :out std_logic_vector(8 downto 0); - signal err_counter_norm_out :out std_logic_vector(15 downto 0); - signal err_counter_fd_out :out std_logic_vector(15 downto 0); - - signal error_state_out :out error_state_type - ); - end component; + ------------------------------------------------------------------------------ + -- Fault confinement + ------------------------------------------------------------------------------ + component faultConf is + port( + signal clk_sys : in std_logic; + signal res_n : in std_logic; + signal drv_bus : in std_logic_vector(1023 downto 0); + signal stuff_Error : in std_logic; + signal error_valid : out std_logic; + signal error_passive_changed : out std_logic; + signal error_warning_limit : out std_logic; + signal OP_State : in oper_mode_type; + signal data_rx : in std_logic; + signal data_tx : in std_logic; + signal rec_trig : in std_logic; + signal tran_trig_1 : in std_logic; + signal PC_State : in protocol_type; + signal sp_control : in std_logic_vector(1 downto 0); + signal form_Error : in std_logic; + signal CRC_Error : in std_logic; + signal ack_Error : in std_logic; + signal unknown_state_Error : in std_logic; + signal bit_stuff_Error_valid : out std_logic; + signal inc_one : in std_logic; + signal inc_eight : in std_logic; + signal dec_one : in std_logic; + signal enable : in std_logic; + signal bit_Error_sec_sam : in std_logic; + signal bit_Error_out : out std_logic; + signal tx_counter_out : out std_logic_vector(8 downto 0); + signal rx_counter_out : out std_logic_vector(8 downto 0); + signal err_counter_norm_out : out std_logic_vector(15 downto 0); + signal err_counter_fd_out : out std_logic_vector(15 downto 0); + signal error_state_out : out error_state_type + ); + end component; - --------------------------------------- - --Asynchronous resset synchroniser -- - --------------------------------------- + ------------------------------------------------------------------------------ + -- Asynchronous resset synchroniser + ------------------------------------------------------------------------------ component rst_sync is port ( - signal clk : in std_logic; - signal arst_n : in std_logic; - signal rst_n : out std_logic - ); + signal clk : in std_logic; + signal arst_n : in std_logic; + signal rst_n : out std_logic + ); end component; - + end package; diff --git a/src/CANconstants.vhd b/src/CANconstants.vhd index 3c8a7e4f0529e7bff3c251f8e5376d89515f9552..9652394016da9c5d24d80ed741755d863ef3917d 100644 --- a/src/CANconstants.vhd +++ b/src/CANconstants.vhd @@ -1,7 +1,7 @@ Library ieee; use ieee.std_logic_1164.all; -------------------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- -- -- CAN with Flexible Data-Rate IP Core -- @@ -26,133 +26,137 @@ use ieee.std_logic_1164.all; -- Revision History: -- -- June 2015 Created file --- -------------------------------------------------------------------------------------------------------------- +-- 08.12.2017 Code formatting. Replaced hexadecimal values with shorter +-- notation +-------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- -- Purpose: --- Package with Constants, types and other defintions for CAN FD IP Core -------------------------------------------------------------------------------------------------------------- +-- Package with Constants, types and other defintions for CAN FD IP Core. +-------------------------------------------------------------------------------- package CANconstants is - + --Active value of asynchronous reset - constant ACT_RESET:std_logic:='0'; - + constant ACT_RESET : std_logic := '0'; + --Definition of basic logic levels for CAN bus - constant DOMINANT:std_logic:='0'; - constant RECESSIVE:std_logic:='1'; - - --Definition of frame types identifiers (Basic, Extended ), equal to IDE bit of Arbitration field - constant FRAME_BASIC:std_logic:='0'; - constant FRAME_EXTENDED:std_logic:='1'; - - constant INTEGRATING_DURATION:natural:=11; - constant TRAN_BUFF_SIZE:natural:=600; - - constant BASE_STUFF_LENGTH:natural:=5; - constant FD_STUFF_LENGTH:natural:=4; - - constant CAN_BASE_ID_LENGTH:natural:=11; - constant CAN_EXT_ID_LENGTH:natural:=18; --Length Identifier extension only - - constant BASE:std_logic:='0'; - constant EXTENDED:std_logic:='1'; - constant NORMAL_CAN:std_logic:='0'; - constant FD_CAN:std_logic:='1'; - - constant NO_SYNC:std_logic_vector:="00"; - constant HARD_SYNC:std_logic_vector:="01"; - constant RE_SYNC:std_logic_vector:="10"; - + constant DOMINANT : std_logic := '0'; + constant RECESSIVE : std_logic := '1'; + + --Definition of frame types identifiers (Basic, Extended ), + --equal to IDE bit of Arbitration field + constant FRAME_BASIC : std_logic := '0'; + constant FRAME_EXTENDED : std_logic := '1'; + + constant INTEGRATING_DURATION : natural := 11; + constant TRAN_BUFF_SIZE : natural := 600; + + constant BASE_STUFF_LENGTH : natural := 5; + constant FD_STUFF_LENGTH : natural := 4; + + constant CAN_BASE_ID_LENGTH : natural := 11; + constant CAN_EXT_ID_LENGTH : natural := 18; --Length Identifier extension only + + constant BASE : std_logic := '0'; + constant EXTENDED : std_logic := '1'; + constant NORMAL_CAN : std_logic := '0'; + constant FD_CAN : std_logic := '1'; + + constant NO_SYNC : std_logic_vector := "00"; + constant HARD_SYNC : std_logic_vector := "01"; + constant RE_SYNC : std_logic_vector := "10"; + --CRC sources - constant CRC_15_SRC:std_logic_vector:="00"; - constant CRC_17_SRC:std_logic_vector:="01"; - constant CRC_21_SRC:std_logic_vector:="10"; - + constant CRC_15_SRC : std_logic_vector := "00"; + constant CRC_17_SRC : std_logic_vector := "01"; + constant CRC_21_SRC : std_logic_vector := "10"; + --Sample point control constants - constant NOMINAL_SAMPLE:std_logic_vector(1 downto 0):="00"; - constant DATA_SAMPLE:std_logic_vector(1 downto 0):="01"; - constant SECONDARY_SAMPLE:std_logic_vector(1 downto 0):="10"; - + constant NOMINAL_SAMPLE : std_logic_vector(1 downto 0) := "00"; + constant DATA_SAMPLE : std_logic_vector(1 downto 0) := "01"; + constant SECONDARY_SAMPLE : std_logic_vector(1 downto 0) := "10"; + --Tuples definition for older compiler (less than 2008) - constant DOMINANT_DOMINANT:std_logic_vector:=DOMINANT&DOMINANT; - constant DOMINANT_RECESSIVE:std_logic_vector:=DOMINANT&RECESSIVE; - constant RECESSIVE_DOMINANT:std_logic_vector:=RECESSIVE&DOMINANT; - constant RECESSIVE_RECESSIVE:std_logic_vector:=RECESSIVE&RECESSIVE; - + constant DOMINANT_DOMINANT : std_logic_vector := DOMINANT&DOMINANT; + constant DOMINANT_RECESSIVE : std_logic_vector := DOMINANT&RECESSIVE; + constant RECESSIVE_DOMINANT : std_logic_vector := RECESSIVE&DOMINANT; + constant RECESSIVE_RECESSIVE : std_logic_vector := RECESSIVE&RECESSIVE; + --Error flag definitions - constant PASSIVE_ERR_FLAG:std_logic:=RECESSIVE; - constant ACTIVE_ERR_FLAG:std_logic:=DOMINANT; - - constant ERROR_FLAG_LENGTH:natural:=6; - - constant INC_ONE_CON:std_logic_vector(2 downto 0):="100"; - constant INC_EIGHT_CON:std_logic_vector(2 downto 0):="010"; - constant DEC_ONE_CON:std_logic_vector(2 downto 0):="001"; - + constant PASSIVE_ERR_FLAG : std_logic := RECESSIVE; + constant ACTIVE_ERR_FLAG : std_logic := DOMINANT; + + constant ERROR_FLAG_LENGTH : natural := 6; + + constant INC_ONE_CON : std_logic_vector(2 downto 0) := "100"; + constant INC_EIGHT_CON : std_logic_vector(2 downto 0) := "010"; + constant DEC_ONE_CON : std_logic_vector(2 downto 0) := "001"; + --Values for enabling of whole controller --and interrupts - constant ENABLED: std_logic:='1'; - constant DISABLED: std_logic:='0'; - + constant ENABLED : std_logic := '1'; + constant DISABLED : std_logic := '0'; + --Values for the type of FD frame type which whould be used - constant ISO_FD: std_logic:='0'; - constant NON_ISO_FD: std_logic:='1'; - + constant ISO_FD : std_logic := '0'; + constant NON_ISO_FD : std_logic := '1'; + --DLC Types type dlc_type is array (0 to 15) of std_logic_vector(3 downto 0); type length_type is array (0 to 15) of natural; - constant dlc_codes:dlc_type:=("0000","0001","0010","0011","0100","0101","0110","0111", - "1000","1001","1010","1011","1100","1101","1110","1111"); - constant dlc_length:length_type:=(0,1,2,3,4,5,6,7,8,12,16,20,24,32,48,64); + constant dlc_codes : dlc_type := ("0000", "0001", "0010", "0011", "0100", "0101", + "0110", "0111", "1000", "1001", "1010", "1011", + "1100", "1101", "1110", "1111"); + constant dlc_length : length_type := (0, 1, 2, 3, 4, 5, 6, 7, 8, + 12, 16, 20, 24, 32, 48, 64); - constant ZERO: std_logic := '0'; - constant NO_ACTION: std_logic := '0'; - - constant ACK_ALLOWED : std_logic := '0'; + constant ZERO : std_logic := '0'; + constant NO_ACTION : std_logic := '0'; + + constant ACK_ALLOWED : std_logic := '0'; constant ACK_FORBIDEN : std_logic := '1'; - + constant LOOPBACK_ENA : std_logic := '1'; constant LOOPBACK_DIS : std_logic := '0'; - - constant RETR_LIM_DIS : std_logic := '0'; - constant RETR_LIM_ENA : std_logic := '1'; - - constant SINGLE_SAMPLING : std_logic := '0'; - constant TRIPPLE_SAMPLING : std_logic := '1'; - - constant ALLOW_BUFFER : std_logic := '1'; - constant FORBID_BUFFER : std_logic := '0'; - + + constant RETR_LIM_DIS : std_logic := '0'; + constant RETR_LIM_ENA : std_logic := '1'; + + constant SINGLE_SAMPLING : std_logic := '0'; + constant TRIPPLE_SAMPLING : std_logic := '1'; + + constant ALLOW_BUFFER : std_logic := '1'; + constant FORBID_BUFFER : std_logic := '0'; + --Definition of register directions for TXT1 and TXT2 buffers - constant TXT1_DIR:std_logic:='0'; - constant TXT2_DIR:std_logic:='1'; - + constant TXT1_DIR : std_logic := '0'; + constant TXT2_DIR : std_logic := '1'; + --CRC polynomials - constant CRC15_POL : std_logic_vector(15 downto 0):=std_logic_vector'(X"C599"); - constant CRC17_POL : std_logic_vector(19 downto 0):=std_logic_vector'(X"3685B"); - constant CRC21_POL : std_logic_vector(23 downto 0):=std_logic_vector'(X"302899"); - - ----------------------- - --State Machine types-- - ----------------------- - + constant CRC15_POL : std_logic_vector(15 downto 0) := x"C599"; + constant CRC17_POL : std_logic_vector(19 downto 0) := x"3685B"; + constant CRC21_POL : std_logic_vector(23 downto 0) := x"302899"; + + ------------------------------------------------------------------------------ + -- State Machine types + ------------------------------------------------------------------------------ + --Error state of node type error_state_type is ( error_active, error_passive, bus_off - ); - + ); + --Operation mode of the Node type oper_mode_type is ( integrating, idle, transciever, reciever - ); - + ); + --Protocol control type protocol_type is ( sof, @@ -166,8 +170,8 @@ package CANconstants is overload, error, off - ); - + ); + --Note: two bits are two bits between Base and Extended identifier --Note: one bit is the last remaining bit after the identifier extension type arb_type is ( @@ -175,10 +179,11 @@ package CANconstants is two_bits, ext_id, one_bit - ); - + ); + --State machine type for sending control field bits - --Note: control_type is only for sending. For recieving frame type is unknown until EDL bit + --Note: control_type is only for sending. For recieving frame + -- type is unknown until EDL bit type control_type is ( r0, r1, @@ -186,33 +191,33 @@ package CANconstants is brs, esi, dlc - ); - + ); + --Within ISO CAN FD new field stuff count is needed! type crc_type is( stuff_count, real_crc - ); - + ); + --Intermission field sub-State type interm_spc_type is ( intermission, suspend, interm_idle - ); - + ); + --Error frame subtype type err_frame_type is ( err_flg_sup, err_delim - ); - - --Overload frame subtype + ); + + --Overload frame subtype type ovr_frame_type is ( ovr_flg_sup, ovr_delim - ); - + ); + type bit_time_type is ( sync, prop, @@ -220,560 +225,576 @@ package CANconstants is ph2, h_sync, reset - ); - + ); + --Logger state machine type type logger_state_type is ( config, ready, running - ); - + ); + -- TX arbitrator state type type tx_arb_state_type is ( arb_idle, arb_trans - ); - - ---------------------------- - --Driving bus signal ranges- - ---------------------------- + ); + + ------------------------------------------------------------------------------ + -- Driving bus signal ranges + ------------------------------------------------------------------------------ --Prescaler - constant DRV_TQ_NBT_LOW:natural:=0; - constant DRV_TQ_NBT_HIGH:natural:=5; - - constant DRV_TQ_DBT_LOW:natural:=6; - constant DRV_TQ_DBT_HIGH:natural:=11; - - constant DRV_PRS_NBT_LOW:natural:=12; - constant DRV_PRS_NBT_HIGH:natural:=17; - - constant DRV_PH1_NBT_LOW:natural:=18; - constant DRV_PH1_NBT_HIGH:natural:=23; - - constant DRV_PH2_NBT_LOW:natural:=24; - constant DRV_PH2_NBT_HIGH:natural:=29; + constant DRV_TQ_NBT_LOW : natural := 0; + constant DRV_TQ_NBT_HIGH : natural := 5; + + constant DRV_TQ_DBT_LOW : natural := 6; + constant DRV_TQ_DBT_HIGH : natural := 11; + + constant DRV_PRS_NBT_LOW : natural := 12; + constant DRV_PRS_NBT_HIGH : natural := 17; + + constant DRV_PH1_NBT_LOW : natural := 18; + constant DRV_PH1_NBT_HIGH : natural := 23; + + constant DRV_PH2_NBT_LOW : natural := 24; + constant DRV_PH2_NBT_HIGH : natural := 29; + + constant DRV_PRS_DBT_LOW : natural := 30; + constant DRV_PRS_DBT_HIGH : natural := 33; + + constant DRV_PH1_DBT_LOW : natural := 34; + constant DRV_PH1_DBT_HIGH : natural := 37; + + constant DRV_PH2_DBT_LOW : natural := 38; + constant DRV_PH2_DBT_HIGH : natural := 41; + + constant DRV_SJW_LOW : natural := 42; + constant DRV_SJW_HIGH : natural := 45; + + constant DRV_SJW_DBT_LOW : natural := 46; + constant DRV_SJW_DBT_HIGH : natural := 49; - constant DRV_PRS_DBT_LOW:natural:=30; - constant DRV_PRS_DBT_HIGH:natural:=33; - - constant DRV_PH1_DBT_LOW:natural:=34; - constant DRV_PH1_DBT_HIGH:natural:=37; - - constant DRV_PH2_DBT_LOW:natural:=38; - constant DRV_PH2_DBT_HIGH:natural:=41; - - constant DRV_SJW_LOW:natural:=42; - constant DRV_SJW_HIGH:natural:=45; - - constant DRV_SJW_DBT_LOW:natural:=46; - constant DRV_SJW_DBT_HIGH:natural:=49; - --TimeStampGen - constant DRV_TS_1_SRC_LOW:natural:=61; - constant DRV_TS_1_SRC_HIGH:natural:=63; - - constant DRV_TS_1_RST_INDEX:natural:=64; - - constant DRV_TS_1_MAKE_LOW:natural:=65; - constant DRV_TS_1_MAKE_HIGH:natural:=68; - - constant DRV_TS_2_SRC_LOW:natural:=69; - constant DRV_TS_2_SRC_HIGH:natural:=71; - - constant DRV_TS_2_RST_INDEX:natural:=72; - - constant DRV_TS_2_MAKE_LOW:natural:=73; - constant DRV_TS_2_MAKE_HIGH:natural:=76; - + constant DRV_TS_1_SRC_LOW : natural := 61; + constant DRV_TS_1_SRC_HIGH : natural := 63; + + constant DRV_TS_1_RST_INDEX : natural := 64; + + constant DRV_TS_1_MAKE_LOW : natural := 65; + constant DRV_TS_1_MAKE_HIGH : natural := 68; + + constant DRV_TS_2_SRC_LOW : natural := 69; + constant DRV_TS_2_SRC_HIGH : natural := 71; + + constant DRV_TS_2_RST_INDEX : natural := 72; + + constant DRV_TS_2_MAKE_LOW : natural := 73; + constant DRV_TS_2_MAKE_HIGH : natural := 76; + --Message Filter - constant DRV_FILTER_A_MASK_LOW:natural:=81; - constant DRV_FILTER_A_MASK_HIGH:natural:=109; - - constant DRV_FILTER_A_CTRL_LOW:natural:=110; - constant DRV_FILTER_A_CTRL_HIGH:natural:=113; - - constant DRV_FILTER_A_BITS_LOW:natural:=114; - constant DRV_FILTER_A_BITS_HIGH:natural:=142; - - constant DRV_FILTER_B_MASK_LOW:natural:=143; - constant DRV_FILTER_B_MASK_HIGH:natural:=171; - - constant DRV_FILTER_B_CTRL_LOW:natural:=172; - constant DRV_FILTER_B_CTRL_HIGH:natural:=175; - - constant DRV_FILTER_B_BITS_LOW:natural:=176; - constant DRV_FILTER_B_BITS_HIGH:natural:=204; - - constant DRV_FILTER_C_MASK_LOW:natural:=205; - constant DRV_FILTER_C_MASK_HIGH:natural:=233; - - constant DRV_FILTER_C_CTRL_LOW:natural:=234; - constant DRV_FILTER_C_CTRL_HIGH:natural:=237; - - constant DRV_FILTER_C_BITS_LOW:natural:=238; - constant DRV_FILTER_C_BITS_HIGH:natural:=266; - - constant DRV_FILTER_RAN_CTRL_LOW:natural:=267; - constant DRV_FILTER_RAN_CTRL_HIGH:natural:=270; - - constant DRV_FILTER_RAN_LO_TH_LOW:natural:=271; - constant DRV_FILTER_RAN_LO_TH_HIGH:natural:=299; - - constant DRV_FILTER_RAN_HI_TH_LOW:natural:=300; - constant DRV_FILTER_RAN_HI_TH_HIGH:natural:=328; - - constant DRV_FILTERS_ENA_INDEX:natural:=329; - + constant DRV_FILTER_A_MASK_LOW : natural := 81; + constant DRV_FILTER_A_MASK_HIGH : natural := 109; + + constant DRV_FILTER_A_CTRL_LOW : natural := 110; + constant DRV_FILTER_A_CTRL_HIGH : natural := 113; + + constant DRV_FILTER_A_BITS_LOW : natural := 114; + constant DRV_FILTER_A_BITS_HIGH : natural := 142; + + constant DRV_FILTER_B_MASK_LOW : natural := 143; + constant DRV_FILTER_B_MASK_HIGH : natural := 171; + + constant DRV_FILTER_B_CTRL_LOW : natural := 172; + constant DRV_FILTER_B_CTRL_HIGH : natural := 175; + + constant DRV_FILTER_B_BITS_LOW : natural := 176; + constant DRV_FILTER_B_BITS_HIGH : natural := 204; + + constant DRV_FILTER_C_MASK_LOW : natural := 205; + constant DRV_FILTER_C_MASK_HIGH : natural := 233; + + constant DRV_FILTER_C_CTRL_LOW : natural := 234; + constant DRV_FILTER_C_CTRL_HIGH : natural := 237; + + constant DRV_FILTER_C_BITS_LOW : natural := 238; + constant DRV_FILTER_C_BITS_HIGH : natural := 266; + + constant DRV_FILTER_RAN_CTRL_LOW : natural := 267; + constant DRV_FILTER_RAN_CTRL_HIGH : natural := 270; + + constant DRV_FILTER_RAN_LO_TH_LOW : natural := 271; + constant DRV_FILTER_RAN_LO_TH_HIGH : natural := 299; + + constant DRV_FILTER_RAN_HI_TH_LOW : natural := 300; + constant DRV_FILTER_RAN_HI_TH_HIGH : natural := 328; + + constant DRV_FILTERS_ENA_INDEX : natural := 329; + --RX Buffer - constant DRV_ERASE_RX_INDEX:natural:=350; - constant DRV_OVR_RX_INDEX:natural:=351; - constant DRV_READ_START_INDEX:natural:=352; - constant DRV_CLR_OVR_INDEX:natural:=353; - + constant DRV_ERASE_RX_INDEX : natural := 350; + constant DRV_OVR_RX_INDEX : natural := 351; + constant DRV_READ_START_INDEX : natural := 352; + constant DRV_CLR_OVR_INDEX : natural := 353; + --TXT Buffer - constant DRV_ERASE_TXT2_INDEX:natural:=356; - constant DRV_TXT1_WR:natural:=357; - + constant DRV_ERASE_TXT2_INDEX : natural := 356; + constant DRV_TXT1_WR : natural := 357; + --TX Buffer - constant DRV_ERASE_TXT1_INDEX:natural:=366; - constant DRV_TXT2_WR:natural:=367; - + constant DRV_ERASE_TXT1_INDEX : natural := 366; + constant DRV_TXT2_WR : natural := 367; + --TX Arbitrator - constant DRV_ALLOW_TXT1_INDEX:natural:=361; - constant DRV_ALLOW_TXT2_INDEX:natural:=362; + constant DRV_ALLOW_TXT1_INDEX : natural := 361; + constant DRV_ALLOW_TXT2_INDEX : natural := 362; --Interrupt manager indices - constant DRV_BUS_ERR_INT_ENA_INDEX:natural:=376; - constant DRV_ARB_LST_INT_ENA_INDEX:natural:=377; - constant DRV_ERR_PAS_INT_ENA_INDEX:natural:=378; - constant DRV_WAKE_INT_ENA_INDEX:natural:=379; - constant DRV_DOV_INT_ENA_INDEX:natural:=380; - constant DRV_ERR_WAR_INT_ENA_INDEX:natural:=381; - constant DRV_TX_INT_ENA_INDEX:natural:=382; - constant DRV_RX_INT_ENA_INDEX:natural:=383; - constant DRV_LOG_FIN_INT_ENA_INDEX:natural:=384; - constant DRV_RX_FULL_INT_ENA_INDEX:natural:=385; - constant DRV_BRS_INT_ENA_INDEX:natural:=386; - - constant DRV_INT_VECT_ERASE_INDEX:natural:=387; - - constant DRV_SAM_INDEX:natural:=372; - - ------------- - --CAN Core -- - ------------- - + constant DRV_BUS_ERR_INT_ENA_INDEX : natural := 376; + constant DRV_ARB_LST_INT_ENA_INDEX : natural := 377; + constant DRV_ERR_PAS_INT_ENA_INDEX : natural := 378; + constant DRV_WAKE_INT_ENA_INDEX : natural := 379; + constant DRV_DOV_INT_ENA_INDEX : natural := 380; + constant DRV_ERR_WAR_INT_ENA_INDEX : natural := 381; + constant DRV_TX_INT_ENA_INDEX : natural := 382; + constant DRV_RX_INT_ENA_INDEX : natural := 383; + constant DRV_LOG_FIN_INT_ENA_INDEX : natural := 384; + constant DRV_RX_FULL_INT_ENA_INDEX : natural := 385; + constant DRV_BRS_INT_ENA_INDEX : natural := 386; + + constant DRV_INT_VECT_ERASE_INDEX : natural := 387; + + constant DRV_SAM_INDEX : natural := 372; + + ------------------------------------------------------------------------------ + -- CAN Core + ------------------------------------------------------------------------------ + --Fault Confinement - constant DRV_EWL_LOW:natural:=400; - constant DRV_EWL_HIGH:natural:=407; - - constant DRV_ERP_LOW:natural:=408; - constant DRV_ERP_HIGH:natural:=415; - - constant DRV_CTR_VAL_LOW:natural:=416; - constant DRV_CTR_VAL_HIGH:natural:=424; - - constant DRV_CTR_SEL_LOW:natural:=425; - constant DRV_CTR_SEL_HIGH:natural:=428; - + constant DRV_EWL_LOW : natural := 400; + constant DRV_EWL_HIGH : natural := 407; + + constant DRV_ERP_LOW : natural := 408; + constant DRV_ERP_HIGH : natural := 415; + + constant DRV_CTR_VAL_LOW : natural := 416; + constant DRV_CTR_VAL_HIGH : natural := 424; + + constant DRV_CTR_SEL_LOW : natural := 425; + constant DRV_CTR_SEL_HIGH : natural := 428; + --Operation control FSM - constant DRV_CAN_FD_ENA_INDEX:natural:=460; - constant DRV_RTR_PREF_INDEX:natural:=461; - constant DRV_BUS_MON_ENA_INDEX:natural:=470; - constant DRV_SELF_TEST_ENA_INDEX:natural:=471; - - constant DRV_RETR_LIM_ENA_INDEX:natural:=465; - - constant DRV_RETR_TH_LOW:natural:=466; - constant DRV_RETR_TH_HIGH:natural:=469; - - constant DRV_ABORT_TRAN_INDEX:natural:=472; - - constant DRV_SET_RX_CTR_INDEX:natural:=473; - constant DRV_SET_TX_CTR_INDEX:natural:=474; - - constant DRV_SET_CTR_VAL_HIGH:natural:=506; - constant DRV_SET_CTR_VAL_LOW:natural:=475; - - constant DRV_ACK_FORB_INDEX:natural:=507; - constant DRV_INT_LOOBACK_ENA_INDEX:natural:=508; - - constant DRV_ENA_INDEX:natural:=509; - constant DRV_FD_TYPE_INDEX:natural:=510; - - ---------------- - --Event logger-- - ---------------- - constant DRV_TRIG_CONFIG_DATA_HIGH:natural:=551; - constant DRV_TRIG_CONFIG_DATA_LOW:natural:=520; - - constant DRV_TRIG_SOF_INDEX:natural:=552; - constant DRV_TRIG_ARB_LOST_INDEX:natural:=553; - constant DRV_TRIG_REC_VALID_INDEX:natural:=554; - constant DRV_TRIG_TRAN_VALID_INDEX:natural:=555; - constant DRV_TRIG_OVL_INDEX:natural:=556; - constant DRV_TRIG_ERROR_INDEX:natural:=557; - constant DRV_TRIG_BRS_INDEX:natural:=558; - constant DRV_TRIG_USER_WRITE_INDEX:natural:=559; - constant DRV_TRIG_ARB_START_INDEX:natural:=560; - constant DRV_TRIG_CONTR_START_INDEX:natural:=561; - constant DRV_TRIG_DATA_START_INDEX:natural:=562; - constant DRV_TRIG_CRC_START_INDEX:natural:=563; - constant DRV_TRIG_ACK_REC_INDEX:natural:=564; - constant DRV_TRIG_ACK_N_REC_INDEX:natural:=565; - constant DRV_TRIG_EWL_REACHED_INDEX:natural:=566; - constant DRV_TRIG_ERP_CHANGED_INDEX:natural:=567; - constant DRV_TRIG_TRAN_START_INDEX:natural:=568; - constant DRV_TRIG_REC_START_INDEX:natural:=569; - - constant DRV_CAP_SOF_INDEX:natural:=580; - constant DRV_CAP_ARB_LOST_INDEX:natural:=581; - constant DRV_CAP_REC_VALID_INDEX:natural:=582; - constant DRV_CAP_TRAN_VALID_INDEX:natural:=583; - constant DRV_CAP_OVL_INDEX:natural:=584; - constant DRV_CAP_ERROR_INDEX:natural:=585; - constant DRV_CAP_BRS_INDEX:natural:=586; - constant DRV_CAP_ARB_START_INDEX:natural:=587; - constant DRV_CAP_CONTR_START_INDEX:natural:=588; - constant DRV_CAP_DATA_START_INDEX:natural:=589; - constant DRV_CAP_CRC_START_INDEX:natural:=590; - constant DRV_CAP_ACK_REC_INDEX:natural:=591; - constant DRV_CAP_ACK_N_REC_INDEX:natural:=592; - constant DRC_CAP_EWL_REACHED_INDEX:natural:=593; - constant DRV_CAP_ERP_CHANGED_INDEX:natural:=594; - constant DRV_CAP_TRAN_START_INDEX:natural:=595; - constant DRV_CAP_REC_START_INDEX:natural:=596; - constant DRV_CAP_SYNC_EDGE_INDEX:natural:=597; - constant DRV_CAP_STUFFED_INDEX:natural:=598; - constant DRV_CAP_DESTUFFED_INDEX:natural:=599; - constant DRV_CAP_OVR_INDEX:natural:=600; - - constant DRV_LOG_CMD_STR_INDEX:natural:=610; - constant DRV_LOG_CMD_ABT_INDEX:natural:=611; - constant DRV_LOG_CMD_UP_INDEX:natural:=612; - constant DRV_LOG_CMD_DOWN_INDEX:natural:=613; - - ---------------------------------------------------- - --RX, TX and TXT Buffer frame format signal indexes- - ---------------------------------------------------- + constant DRV_CAN_FD_ENA_INDEX : natural := 460; + constant DRV_RTR_PREF_INDEX : natural := 461; + constant DRV_BUS_MON_ENA_INDEX : natural := 470; + constant DRV_SELF_TEST_ENA_INDEX : natural := 471; + + constant DRV_RETR_LIM_ENA_INDEX : natural := 465; + + constant DRV_RETR_TH_LOW : natural := 466; + constant DRV_RETR_TH_HIGH : natural := 469; + + constant DRV_ABORT_TRAN_INDEX : natural := 472; + + constant DRV_SET_RX_CTR_INDEX : natural := 473; + constant DRV_SET_TX_CTR_INDEX : natural := 474; + + constant DRV_SET_CTR_VAL_HIGH : natural := 506; + constant DRV_SET_CTR_VAL_LOW : natural := 475; + + constant DRV_ACK_FORB_INDEX : natural := 507; + constant DRV_INT_LOOBACK_ENA_INDEX : natural := 508; + + constant DRV_ENA_INDEX : natural := 509; + constant DRV_FD_TYPE_INDEX : natural := 510; + + ------------------------------------------------------------------------------ + -- Event logger + ------------------------------------------------------------------------------ + constant DRV_TRIG_CONFIG_DATA_HIGH : natural := 551; + constant DRV_TRIG_CONFIG_DATA_LOW : natural := 520; + + constant DRV_TRIG_SOF_INDEX : natural := 552; + constant DRV_TRIG_ARB_LOST_INDEX : natural := 553; + constant DRV_TRIG_REC_VALID_INDEX : natural := 554; + constant DRV_TRIG_TRAN_VALID_INDEX : natural := 555; + constant DRV_TRIG_OVL_INDEX : natural := 556; + constant DRV_TRIG_ERROR_INDEX : natural := 557; + constant DRV_TRIG_BRS_INDEX : natural := 558; + constant DRV_TRIG_USER_WRITE_INDEX : natural := 559; + constant DRV_TRIG_ARB_START_INDEX : natural := 560; + constant DRV_TRIG_CONTR_START_INDEX : natural := 561; + constant DRV_TRIG_DATA_START_INDEX : natural := 562; + constant DRV_TRIG_CRC_START_INDEX : natural := 563; + constant DRV_TRIG_ACK_REC_INDEX : natural := 564; + constant DRV_TRIG_ACK_N_REC_INDEX : natural := 565; + constant DRV_TRIG_EWL_REACHED_INDEX : natural := 566; + constant DRV_TRIG_ERP_CHANGED_INDEX : natural := 567; + constant DRV_TRIG_TRAN_START_INDEX : natural := 568; + constant DRV_TRIG_REC_START_INDEX : natural := 569; + + constant DRV_CAP_SOF_INDEX : natural := 580; + constant DRV_CAP_ARB_LOST_INDEX : natural := 581; + constant DRV_CAP_REC_VALID_INDEX : natural := 582; + constant DRV_CAP_TRAN_VALID_INDEX : natural := 583; + constant DRV_CAP_OVL_INDEX : natural := 584; + constant DRV_CAP_ERROR_INDEX : natural := 585; + constant DRV_CAP_BRS_INDEX : natural := 586; + constant DRV_CAP_ARB_START_INDEX : natural := 587; + constant DRV_CAP_CONTR_START_INDEX : natural := 588; + constant DRV_CAP_DATA_START_INDEX : natural := 589; + constant DRV_CAP_CRC_START_INDEX : natural := 590; + constant DRV_CAP_ACK_REC_INDEX : natural := 591; + constant DRV_CAP_ACK_N_REC_INDEX : natural := 592; + constant DRC_CAP_EWL_REACHED_INDEX : natural := 593; + constant DRV_CAP_ERP_CHANGED_INDEX : natural := 594; + constant DRV_CAP_TRAN_START_INDEX : natural := 595; + constant DRV_CAP_REC_START_INDEX : natural := 596; + constant DRV_CAP_SYNC_EDGE_INDEX : natural := 597; + constant DRV_CAP_STUFFED_INDEX : natural := 598; + constant DRV_CAP_DESTUFFED_INDEX : natural := 599; + constant DRV_CAP_OVR_INDEX : natural := 600; + + constant DRV_LOG_CMD_STR_INDEX : natural := 610; + constant DRV_LOG_CMD_ABT_INDEX : natural := 611; + constant DRV_LOG_CMD_UP_INDEX : natural := 612; + constant DRV_LOG_CMD_DOWN_INDEX : natural := 613; + + ------------------------------------------------------------------------------ + -- RX, TX and TXT Buffer frame format signal indexes + ------------------------------------------------------------------------------ --Tx Message format (Format A) - constant TX_FFW_HIGH:natural:=639; - constant TX_FFW_LOW:natural:=608; - - constant TX_IDW_HIGH:natural:=607; - constant TX_IDW_LOW:natural:=576; - - constant TX_DATAW_HIGH:natural:=575; --16 Data words for up to 64 bytes of data - constant TX_DATA1W_LOW:natural:=544; - constant TX_DATAW_LOW:natural:=64; - + constant TX_FFW_HIGH : natural := 639; + constant TX_FFW_LOW : natural := 608; + + constant TX_IDW_HIGH : natural := 607; + constant TX_IDW_LOW : natural := 576; + + --16 Data words for up to 64 bytes of data + constant TX_DATAW_HIGH : natural := 575; + constant TX_DATA1W_LOW : natural := 544; + constant TX_DATAW_LOW : natural := 64; + --Txt message format (Format B) - constant TXT_FFW_HIGH:natural:=639; - constant TXT_FFW_LOW:natural:=608; - - constant TXT_TSUPP_HIGH:natural:=607; - constant TXT_TSUPP_LOW:natural:=576; - - constant TXT_TSLOW_HIGH:natural:=575; - constant TXT_TSLOW_LOW:natural:=544; - - constant TXT_IDW_HIGH:natural:=543; - constant TXT_IDW_LOW:natural:=512; - - constant TXT_DATAW_HIGH:natural:=511; - constant TXT_DATAW_LOW:natural:=0; - - - ---------------------------- - --Interrupt vector indices-- - ---------------------------- - constant BUS_ERR_INT:natural:=7; - constant ARB_LST_INT:natural:=6; - constant ERR_PAS_INT:natural:=5; - constant WAKE_INT:natural:=4; - constant DOV_INT:natural:=3; - constant ERR_WAR_INT:natural:=2; - constant TX_INT:natural:=1; - constant RX_INT:natural:=0; - constant LOG_FIN_INT:natural:=8; - constant RX_FULL_INT:natural:=9; - constant BRS_INT:natural:=10; + constant TXT_FFW_HIGH : natural := 639; + constant TXT_FFW_LOW : natural := 608; + + constant TXT_TSUPP_HIGH : natural := 607; + constant TXT_TSUPP_LOW : natural := 576; + + constant TXT_TSLOW_HIGH : natural := 575; + constant TXT_TSLOW_LOW : natural := 544; + + constant TXT_IDW_HIGH : natural := 543; + constant TXT_IDW_LOW : natural := 512; + + constant TXT_DATAW_HIGH : natural := 511; + constant TXT_DATAW_LOW : natural := 0; + + + ------------------------------------------------------------------------------ + -- Interrupt vector indices + ------------------------------------------------------------------------------ + constant BUS_ERR_INT : natural := 7; + constant ARB_LST_INT : natural := 6; + constant ERR_PAS_INT : natural := 5; + constant WAKE_INT : natural := 4; + constant DOV_INT : natural := 3; + constant ERR_WAR_INT : natural := 2; + constant TX_INT : natural := 1; + constant RX_INT : natural := 0; + constant LOG_FIN_INT : natural := 8; + constant RX_FULL_INT : natural := 9; + constant BRS_INT : natural := 10; + + + ------------------------------------------------------------------------------ + -- Status bus Indices + ------------------------------------------------------------------------------ + constant STAT_OP_STATE_LOW : natural := 0; + constant STAT_OP_STATE_HIGH : natural := 1; + + constant STAT_PC_STATE_LOW : natural := 2; + constant STAT_PC_STATE_HIGH : natural := 5; + + constant STAT_ARB_LOST_INDEX : natural := 6; + + constant STAT_SET_TRANSC_INDEX : natural := 7; + constant STAT_SET_REC_INDEX : natural := 8; + constant STAT_IS_IDLE_INDEX : natural := 9; + + constant STAT_SP_CONTROL_HIGH : natural := 11; + constant STAT_SP_CONTROL_LOW : natural := 10; + + constant STAT_SSP_RESET_INDEX : natural := 12; + constant STAT_TRV_DELAY_CALIB_INDEX : natural := 13; + constant STAT_SYNC_CONTROL_HIGH : natural := 15; + constant STAT_SYNC_CONTROL_LOW : natural := 14; + + constant STAT_DATA_TX_INDEX : natural := 16; + constant STAT_DATA_RX_INDEX : natural := 17; + constant STAT_BS_ENABLE_INDEX : natural := 18; + constant STAT_FIXED_STUFF_INDEX : natural := 19; + constant STAT_DATA_HALT_INDEX : natural := 20; + constant STAT_BS_LENGTH_HIGH : natural := 23; + constant STAT_BS_LENGTH_LOW : natural := 21; - - ----------------------- - --STATUS BUS INDICES -- - ----------------------- - constant STAT_OP_STATE_LOW:natural:=0; - constant STAT_OP_STATE_HIGH:natural:=1; - - constant STAT_PC_STATE_LOW:natural:=2; - constant STAT_PC_STATE_HIGH:natural:=5; - - constant STAT_ARB_LOST_INDEX:natural:=6; - - constant STAT_SET_TRANSC_INDEX:natural:=7; - constant STAT_SET_REC_INDEX:natural:=8; - constant STAT_IS_IDLE_INDEX:natural:=9; - - constant STAT_SP_CONTROL_HIGH:natural:=11; - constant STAT_SP_CONTROL_LOW:natural:=10; - - constant STAT_SSP_RESET_INDEX:natural:=12; - constant STAT_TRV_DELAY_CALIB_INDEX:natural:=13; - constant STAT_SYNC_CONTROL_HIGH:natural:=15; - constant STAT_SYNC_CONTROL_LOW:natural:=14; - - constant STAT_DATA_TX_INDEX:natural:=16; - constant STAT_DATA_RX_INDEX:natural:=17; - constant STAT_BS_ENABLE_INDEX:natural:=18; - constant STAT_FIXED_STUFF_INDEX:natural:=19; - constant STAT_DATA_HALT_INDEX:natural:=20; - constant STAT_BS_LENGTH_HIGH:natural:=23; - constant STAT_BS_LENGTH_LOW:natural:=21; - --Error indices - constant STAT_STUFF_ERROR_INDEX:natural:=24; - constant STAT_DESTUFFED_INDEX:natural:=25; - constant STAT_BDS_ENA_INDEX:natural:=26; - constant STAT_STUFF_ERRROR_ENA_INDEX:natural:=27; - constant STAT_FIXED_DESTUFF_INDEX:natural:=28; - constant STAT_BDS_LENGTH_HIGH:natural:=31; - constant STAT_BDS_LENGTH_LOW:natural:=29; - + constant STAT_STUFF_ERROR_INDEX : natural := 24; + constant STAT_DESTUFFED_INDEX : natural := 25; + constant STAT_BDS_ENA_INDEX : natural := 26; + constant STAT_STUFF_ERRROR_ENA_INDEX : natural := 27; + constant STAT_FIXED_DESTUFF_INDEX : natural := 28; + constant STAT_BDS_LENGTH_HIGH : natural := 31; + constant STAT_BDS_LENGTH_LOW : natural := 29; + --Transcieve data - constant STAT_TRAN_IDENT_HIGH:natural:=60; - constant STAT_TRAN_IDENT_LOW:natural:=32; - - constant STAT_TRAN_DLC_HIGH:natural:=64; - constant STAT_TRAN_DLC_LOW:natural:=61; - - constant STAT_TRAN_IS_RTR_INDEX:natural:=65; - constant STAT_TRAN_IDENT_TYPE_INDEX:natural:=66; - constant STAT_TRAN_FRAME_TYPE_INDEX:natural:=67; - constant STAT_TRAN_DATA_ACK_INDEX:natural:=68; - constant STAT_TRAN_BRS_INDEX:natural:=69; - constant STAT_FRAME_STORE_INDEX:natural:=70; - + constant STAT_TRAN_IDENT_HIGH : natural := 60; + constant STAT_TRAN_IDENT_LOW : natural := 32; + + constant STAT_TRAN_DLC_HIGH : natural := 64; + constant STAT_TRAN_DLC_LOW : natural := 61; + + constant STAT_TRAN_IS_RTR_INDEX : natural := 65; + constant STAT_TRAN_IDENT_TYPE_INDEX : natural := 66; + constant STAT_TRAN_FRAME_TYPE_INDEX : natural := 67; + constant STAT_TRAN_DATA_ACK_INDEX : natural := 68; + constant STAT_TRAN_BRS_INDEX : natural := 69; + constant STAT_FRAME_STORE_INDEX : natural := 70; + --Error counters and error state - constant STAT_TX_COUNTER_HIGH:natural:=79; - constant STAT_TX_COUNTER_LOW:natural:=71; - constant STAT_RX_COUNTER_HIGH:natural:=89; - constant STAT_RX_COUNTER_LOW:natural:=81; - constant STAT_ERROR_COUNTER_NORM_HIGH:natural:=272; - constant STAT_ERROR_COUNTER_NORM_LOW:natural:=257; - constant STAT_ERROR_COUNTER_FD_HIGH:natural:=288; - constant STAT_ERROR_COUNTER_FD_LOW:natural:=273; - - constant STAT_ERROR_STATE_HIGH:natural:=109; - constant STAT_ERROR_STATE_LOW:natural:=108; - + constant STAT_TX_COUNTER_HIGH : natural := 79; + constant STAT_TX_COUNTER_LOW : natural := 71; + constant STAT_RX_COUNTER_HIGH : natural := 89; + constant STAT_RX_COUNTER_LOW : natural := 81; + constant STAT_ERROR_COUNTER_NORM_HIGH : natural := 272; + constant STAT_ERROR_COUNTER_NORM_LOW : natural := 257; + constant STAT_ERROR_COUNTER_FD_HIGH : natural := 288; + constant STAT_ERROR_COUNTER_FD_LOW : natural := 273; + + constant STAT_ERROR_STATE_HIGH : natural := 109; + constant STAT_ERROR_STATE_LOW : natural := 108; + --Error signals - constant STAT_FORM_ERROR_INDEX:natural:=110; - constant STAT_CRC_ERROR_INDEX:natural:=111; - constant STAT_ACK_ERROR_INDEX:natural:=112; - constant STAT_UNKNOWN_STATE_ERROR_INDEX:natural:=113; - constant STAT_BIT_STUFF_ERROR_INDEX:natural:=114; - constant STAT_FIRST_BIT_AFTER_INDEX:natural:=115; - constant STAT_REC_VALID_INDEX:natural:=116; - constant STAT_TRAN_VALID_INDEX:natural:=117; - constant STAT_CONST7_INDEX:natural:=118; - constant STAT_CONST14_INDEX:natural:=119; - constant STAT_TRANSM_ERROR_INDEX:natural:=120; - + constant STAT_FORM_ERROR_INDEX : natural := 110; + constant STAT_CRC_ERROR_INDEX : natural := 111; + constant STAT_ACK_ERROR_INDEX : natural := 112; + constant STAT_UNKNOWN_STATE_ERROR_INDEX : natural := 113; + constant STAT_BIT_STUFF_ERROR_INDEX : natural := 114; + constant STAT_FIRST_BIT_AFTER_INDEX : natural := 115; + constant STAT_REC_VALID_INDEX : natural := 116; + constant STAT_TRAN_VALID_INDEX : natural := 117; + constant STAT_CONST7_INDEX : natural := 118; + constant STAT_CONST14_INDEX : natural := 119; + constant STAT_TRANSM_ERROR_INDEX : natural := 120; + --Recieved data interface - constant STAT_REC_IDENT_HIGH:natural:=149; - constant STAT_REC_IDENT_LOW:natural:=121; - constant STAT_REC_DLC_HIGH:natural:=153; - constant STAT_REC_DLC_LOW:natural:=150; - constant STAT_REC_IS_RTR_INDEX:natural:=154; - constant STAT_REC_IDENT_TYPE_INDEX:natural:=155; - constant STAT_REC_FRAME_TYPE_INDEX:natural:=156; - constant STAT_REC_BRS_INDEX:natural:=157; - constant STAT_REC_CRC_HIGH:natural:=178; - constant STAT_REC_CRC_LOW:natural:=158; - constant STAT_REC_ESI_INDEX:natural:=179; - constant STAT_CRC_ENA_INDEX:natural:=180; - constant STAT_TRAN_TRIG:natural:=181; - constant STAT_REC_TRIG:natural:=182; - + constant STAT_REC_IDENT_HIGH : natural := 149; + constant STAT_REC_IDENT_LOW : natural := 121; + constant STAT_REC_DLC_HIGH : natural := 153; + constant STAT_REC_DLC_LOW : natural := 150; + constant STAT_REC_IS_RTR_INDEX : natural := 154; + constant STAT_REC_IDENT_TYPE_INDEX : natural := 155; + constant STAT_REC_FRAME_TYPE_INDEX : natural := 156; + constant STAT_REC_BRS_INDEX : natural := 157; + constant STAT_REC_CRC_HIGH : natural := 178; + constant STAT_REC_CRC_LOW : natural := 158; + constant STAT_REC_ESI_INDEX : natural := 179; + constant STAT_CRC_ENA_INDEX : natural := 180; + constant STAT_TRAN_TRIG : natural := 181; + constant STAT_REC_TRIG : natural := 182; + --Arbitration lost capture - constant STAT_ALC_HIGH:natural:=187; - constant STAT_ALC_LOW:natural:=183; - + constant STAT_ALC_HIGH : natural := 187; + constant STAT_ALC_LOW : natural := 183; + --Bus traffic registers - constant STAT_RX_CTR_HIGH:natural:=219; - constant STAT_RX_CTR_LOW:natural:=188; - - constant STAT_TX_CTR_HIGH:natural:=251; - constant STAT_TX_CTR_LOW:natural:=220; - - constant STAT_ERP_CHANGED_INDEX:natural:=252; - constant STAT_EWL_REACHED_INDEX:natural:=253; - constant STAT_ERROR_VALID_INDEX:natural:=254; - - constant STAT_ACK_RECIEVED_OUT_INDEX:natural:=255; - - constant STAT_BIT_ERROR_VALID_INDEX:natural:=256; - - constant STAT_BS_CTR_HIGH:natural:=302; - constant STAT_BS_CTR_LOW:natural:=300; - - constant STAT_BD_CTR_HIGH:natural:=305; - constant STAT_BD_CTR_LOW:natural:=303; - - constant STAT_TS_HIGH:natural:=369; - constant STAT_TS_LOW:natural:=306; - - ------------------ - --MEMORY Acesss -- - ------------------ - constant GPR_COMPONENT_TYPE:std_logic_vector(3 downto 0):=std_logic_vector'(X"1"); --General Purpose register - constant OUTMUX_COMPONENT_TYPE:std_logic_vector(3 downto 0):=std_logic_vector'(X"2"); --OutPut Multiplexor component type - constant FLEXRAY_COMPONENT_TYPE:std_logic_vector(3 downto 0):=std_logic_vector'(X"3"); --FlexRay Node - constant CAN_COMPONENT_TYPE:std_logic_vector(3 downto 0):=std_logic_vector'(X"4"); --CAN Node has 4. - constant LIN_COMPONENT_TYPE:std_logic_vector(3 downto 0):=std_logic_vector'(X"5"); --LIN Node - - constant ACT_CSC:std_logic:='1'; - constant ACT_SRD:std_logic:='1'; - constant ACT_SWR:std_logic:='1'; - + constant STAT_RX_CTR_HIGH : natural := 219; + constant STAT_RX_CTR_LOW : natural := 188; + + constant STAT_TX_CTR_HIGH : natural := 251; + constant STAT_TX_CTR_LOW : natural := 220; + + constant STAT_ERP_CHANGED_INDEX : natural := 252; + constant STAT_EWL_REACHED_INDEX : natural := 253; + constant STAT_ERROR_VALID_INDEX : natural := 254; + + constant STAT_ACK_RECIEVED_OUT_INDEX : natural := 255; + + constant STAT_BIT_ERROR_VALID_INDEX : natural := 256; + + constant STAT_BS_CTR_HIGH : natural := 302; + constant STAT_BS_CTR_LOW : natural := 300; + + constant STAT_BD_CTR_HIGH : natural := 305; + constant STAT_BD_CTR_LOW : natural := 303; + + constant STAT_TS_HIGH : natural := 369; + constant STAT_TS_LOW : natural := 306; + + ------------------------------------------------------------------------------ + -- Memory Access + ------------------------------------------------------------------------------ + --General Purpose register + constant GPR_COMPONENT_TYPE : std_logic_vector(3 downto 0) := x"1"; + + --OutPut Multiplexor component type + constant OUTMUX_COMPONENT_TYPE : std_logic_vector(3 downto 0) := x"2"; + + --FlexRay Node + constant FLEXRAY_COMPONENT_TYPE : std_logic_vector(3 downto 0) := x"3"; + + --CAN Node + constant CAN_COMPONENT_TYPE : std_logic_vector(3 downto 0) := x"4"; + + --LIN Node + constant LIN_COMPONENT_TYPE : std_logic_vector(3 downto 0) := x"5"; + + constant ACT_CSC : std_logic := '1'; + constant ACT_SRD : std_logic := '1'; + constant ACT_SWR : std_logic := '1'; + --Address ranges for component type and identifier - constant COMP_TYPE_ADRESS_HIGHER:natural:=23; - constant COMP_TYPE_ADRESS_LOWER:natural:=20; - constant ID_ADRESS_HIGHER:natural:=19; - constant ID_ADRESS_LOWER:natural:=16; - - constant CAN_DEVICE_ID:std_logic_vector(31 downto 0):=std_logic_vector'(X"0000CAFD"); - + constant COMP_TYPE_ADRESS_HIGHER : natural := 23; + constant COMP_TYPE_ADRESS_LOWER : natural := 20; + constant ID_ADRESS_HIGHER : natural := 19; + constant ID_ADRESS_LOWER : natural := 16; + + constant CAN_DEVICE_ID : std_logic_vector(31 downto 0) := x"0000CAFD"; + + ------------------------------------------------------------------------------ --Adress Offsets - --Note: It is considered that lowest two bits are cut!! Therefore every register is in processor mapped to 0x4 higher adress!! - --This is done to achieve the uniform acess, when someone acesses 0x0000,0x0001,0x0002,0x0003 adresses. This way lower bits will - --be cut and no adress alignment problems will appear. - --The real adress(in processor) offset is 4 times value of adress constant! - constant DEVICE_ID_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"000"); - constant MODE_REG_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"001"); - constant INTERRUPT_REG_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"002"); - constant TIMING_REG_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"003"); - constant ARB_ERROR_PRESC_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"004"); - constant ERROR_TH_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"005"); - constant ERROR_COUNTERS_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"006"); - constant ERROR_COUNTERS_SPEC_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"007"); - constant FILTER_A_VAL_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"008"); - constant FILTER_A_MASK_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"009"); - constant FILTER_B_VAL_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"00A"); - constant FILTER_B_MASK_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"00B"); - constant FILTER_C_VAL_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"00C"); - constant FILTER_C_MASK_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"00D"); - constant FILTER_RAN_LOW_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"00E"); --Mode, Status, Control Register - constant FILTER_RAN_HIGH_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"00F"); --Mode, Status, Control Register - constant FILTER_CONTROL_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"010"); --Mode, Status, Control Register - constant RX_INFO_1_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"011"); - constant RX_INFO_2_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"012"); - constant RX_DATA_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"013"); - constant TRV_DELAY_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"014"); - - constant TX_STATUS_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"015"); - constant TX_SETTINGS_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"016"); - - constant TX_DATA_1_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"017"); - constant TX_DATA_2_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"018"); - constant TX_DATA_3_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"019"); - constant TX_DATA_4_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"01A"); - constant TX_DATA_5_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"01B"); - constant TX_DATA_6_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"01C"); - constant TX_DATA_7_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"01D"); - constant TX_DATA_8_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"01E"); - constant TX_DATA_9_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"01F"); - constant TX_DATA_10_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"020"); - constant TX_DATA_11_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"021"); - constant TX_DATA_12_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"022"); - constant TX_DATA_13_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"023"); - constant TX_DATA_14_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"024"); - constant TX_DATA_15_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"025"); - constant TX_DATA_16_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"026"); - constant TX_DATA_17_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"027"); - constant TX_DATA_18_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"028"); - constant TX_DATA_19_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"029"); - constant TX_DATA_20_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"02A"); - - constant RX_COUNTER_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"02B"); - constant TX_COUNTER_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"02C"); - - constant LOG_TRIG_CONFIG_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"02E"); - constant LOG_TRIG_CONFIG_DATA_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"02F"); - constant LOG_CAPT_CONFIG_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"030"); - constant LOG_STATUS_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"031"); - constant LOG_CMD_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"032"); - constant LOG_CAPT_EVENT1_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"033"); - constant LOG_CAPT_EVENT2_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"034"); - - constant DEBUG_REG_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"035"); - constant YOLO_REG_ADR:std_logic_vector(11 downto 0):=std_logic_vector'(X"036"); - + ------------------------------------------------------------------------------ + --Note: It is considered that lowest two bits are cut!! Therefore every + --register is in processor mapped to 0x4 higher adress!! This is done to + --achieve the uniform acess, when someone acesses 0x0000,0x0001,0x0002,0x0003 + --adresses. This way lower bits will be cut and no adress alignment problems + --will appear. The real adress(in processor) offset is 4 times value of adress + --constant! + constant DEVICE_ID_ADR : std_logic_vector(11 downto 0) := x"000"; + constant MODE_REG_ADR : std_logic_vector(11 downto 0) := x"001"; + constant INTERRUPT_REG_ADR : std_logic_vector(11 downto 0) := x"002"; + constant TIMING_REG_ADR : std_logic_vector(11 downto 0) := x"003"; + constant ARB_ERROR_PRESC_ADR : std_logic_vector(11 downto 0) := x"004"; + constant ERROR_TH_ADR : std_logic_vector(11 downto 0) := x"005"; + constant ERROR_COUNTERS_ADR : std_logic_vector(11 downto 0) := x"006"; + constant ERROR_COUNTERS_SPEC_ADR : std_logic_vector(11 downto 0) := x"007"; + constant FILTER_A_VAL_ADR : std_logic_vector(11 downto 0) := x"008"; + constant FILTER_A_MASK_ADR : std_logic_vector(11 downto 0) := x"009"; + constant FILTER_B_VAL_ADR : std_logic_vector(11 downto 0) := x"00A"; + constant FILTER_B_MASK_ADR : std_logic_vector(11 downto 0) := x"00B"; + constant FILTER_C_VAL_ADR : std_logic_vector(11 downto 0) := x"00C"; + constant FILTER_C_MASK_ADR : std_logic_vector(11 downto 0) := x"00D"; + constant FILTER_RAN_LOW_ADR : std_logic_vector(11 downto 0) := x"00E"; + constant FILTER_RAN_HIGH_ADR : std_logic_vector(11 downto 0) := x"00F"; + constant FILTER_CONTROL_ADR : std_logic_vector(11 downto 0) := x"010"; + constant RX_INFO_1_ADR : std_logic_vector(11 downto 0) := x"011"; + constant RX_INFO_2_ADR : std_logic_vector(11 downto 0) := x"012"; + constant RX_DATA_ADR : std_logic_vector(11 downto 0) := x"013"; + constant TRV_DELAY_ADR : std_logic_vector(11 downto 0) := x"014"; + + constant TX_STATUS_ADR : std_logic_vector(11 downto 0) := x"015"; + constant TX_SETTINGS_ADR : std_logic_vector(11 downto 0) := x"016"; + + constant TX_DATA_1_ADR : std_logic_vector(11 downto 0) := x"017"; + constant TX_DATA_2_ADR : std_logic_vector(11 downto 0) := x"018"; + constant TX_DATA_3_ADR : std_logic_vector(11 downto 0) := x"019"; + constant TX_DATA_4_ADR : std_logic_vector(11 downto 0) := x"01A"; + constant TX_DATA_5_ADR : std_logic_vector(11 downto 0) := x"01B"; + constant TX_DATA_6_ADR : std_logic_vector(11 downto 0) := x"01C"; + constant TX_DATA_7_ADR : std_logic_vector(11 downto 0) := x"01D"; + constant TX_DATA_8_ADR : std_logic_vector(11 downto 0) := x"01E"; + constant TX_DATA_9_ADR : std_logic_vector(11 downto 0) := x"01F"; + constant TX_DATA_10_ADR : std_logic_vector(11 downto 0) := x"020"; + constant TX_DATA_11_ADR : std_logic_vector(11 downto 0) := x"021"; + constant TX_DATA_12_ADR : std_logic_vector(11 downto 0) := x"022"; + constant TX_DATA_13_ADR : std_logic_vector(11 downto 0) := x"023"; + constant TX_DATA_14_ADR : std_logic_vector(11 downto 0) := x"024"; + constant TX_DATA_15_ADR : std_logic_vector(11 downto 0) := x"025"; + constant TX_DATA_16_ADR : std_logic_vector(11 downto 0) := x"026"; + constant TX_DATA_17_ADR : std_logic_vector(11 downto 0) := x"027"; + constant TX_DATA_18_ADR : std_logic_vector(11 downto 0) := x"028"; + constant TX_DATA_19_ADR : std_logic_vector(11 downto 0) := x"029"; + constant TX_DATA_20_ADR : std_logic_vector(11 downto 0) := x"02A"; + + constant RX_COUNTER_ADR : std_logic_vector(11 downto 0) := x"02B"; + constant TX_COUNTER_ADR : std_logic_vector(11 downto 0) := x"02C"; + + constant LOG_TRIG_CONFIG_ADR : std_logic_vector(11 downto 0) := x"02E"; + constant LOG_TRIG_CONFIG_DATA_ADR : std_logic_vector(11 downto 0) := x"02F"; + constant LOG_CAPT_CONFIG_ADR : std_logic_vector(11 downto 0) := x"030"; + constant LOG_STATUS_ADR : std_logic_vector(11 downto 0) := x"031"; + constant LOG_CMD_ADR : std_logic_vector(11 downto 0) := x"032"; + constant LOG_CAPT_EVENT1_ADR : std_logic_vector(11 downto 0) := x"033"; + constant LOG_CAPT_EVENT2_ADR : std_logic_vector(11 downto 0) := x"034"; + + constant DEBUG_REG_ADR : std_logic_vector(11 downto 0) := x"035"; + constant YOLO_REG_ADR : std_logic_vector(11 downto 0) := x"036"; + ---------------- --Register Bits- ---------------- --Status register - constant BS_IND:natural:=7; --Bus status - constant ES_IND:natural:=6; --Error Status - constant TS_IND:natural:=5; --Transmit Status - constant RS_IND:natural:=4; --Recieve status - constant ET_IND:natural:=3; --Transmit Buffer Status - constant TBS_IND:natural:=2; --Transmit Buffer Status - constant DOS_IND:natural:=1; --Data OverRun Status - constant RBS_IND:natural:=0; -- Recieve Buffer Status - + constant BS_IND : natural := 7; -- Bus status + constant ES_IND : natural := 6; -- Error Status + constant TS_IND : natural := 5; -- Transmit Status + constant RS_IND : natural := 4; -- Recieve status + constant ET_IND : natural := 3; -- Transmit Buffer Status + constant TBS_IND : natural := 2; -- Transmit Buffer Status + constant DOS_IND : natural := 1; -- Data OverRun Status + constant RBS_IND : natural := 0; -- Recieve Buffer Status + --Mode register - constant FDE_IND:natural:=4; --Flexible datarate enable - constant RTR_PREF_IND:natural:=5; --RTR Preffered behaviour - constant AFM_IND:natural:=3; --Acceptance filters mode (acceptance filters enabled) - constant LOM_IND:natural:=1; - constant STM_IND:natural:=2; - constant TSM_IND:natural:=6; - constant RST_IND:natural:=0; - + constant FDE_IND : natural := 4; -- Flexible datarate enable + constant RTR_PREF_IND : natural := 5; -- RTR Preffered behaviour + constant AFM_IND : natural := 3; -- Acceptance filters mode (enabled) + constant LOM_IND : natural := 1; + constant STM_IND : natural := 2; + constant TSM_IND : natural := 6; + constant RST_IND : natural := 0; + --Interrupt enable indices - constant RI_IND:natural:=0; - constant TI_IND:natural:=1; - constant EI_IND:natural:=2; - constant DOI_IND:natural:=3; - constant EPI_IND:natural:=5; - constant ALI_IND:natural:=6; - constant BEI_IND:natural:=7; - constant LFI_IND:natural:=8; - constant RFI_IND:natural:=9; - constant BSI_IND:natural:=10; - - + constant RI_IND : natural := 0; + constant TI_IND : natural := 1; + constant EI_IND : natural := 2; + constant DOI_IND : natural := 3; + constant EPI_IND : natural := 5; + constant ALI_IND : natural := 6; + constant BEI_IND : natural := 7; + constant LFI_IND : natural := 8; + constant RFI_IND : natural := 9; + constant BSI_IND : natural := 10; + + ---------------------------------------------- --Logger event types ---------------------------------------------- - constant SOF_EVNT:std_logic_vector(7 downto 0) := std_logic_vector'(X"01"); - constant ALO_EVNT:std_logic_vector(7 downto 0) := std_logic_vector'(X"02"); - constant REC_EVNT:std_logic_vector(7 downto 0) := std_logic_vector'(X"03"); - constant TRAN_EVNT:std_logic_vector(7 downto 0) := std_logic_vector'(X"04"); - constant OVLD_EVNT:std_logic_vector(7 downto 0) := std_logic_vector'(X"05"); - constant ERR_EVNT:std_logic_vector(7 downto 0) := std_logic_vector'(X"06"); - constant BRS_EVNT:std_logic_vector(7 downto 0) := std_logic_vector'(X"07"); - constant ARB_EVNT:std_logic_vector(7 downto 0) := std_logic_vector'(X"08"); - constant CTRL_EVNT:std_logic_vector(7 downto 0) := std_logic_vector'(X"09"); - constant DATA_EVNT:std_logic_vector(7 downto 0) := std_logic_vector'(X"0A"); - constant CRC_EVNT:std_logic_vector(7 downto 0) := std_logic_vector'(X"0B"); - constant ACK_EVNT:std_logic_vector(7 downto 0) := std_logic_vector'(X"0C"); - constant NACK_EVNT:std_logic_vector(7 downto 0) := std_logic_vector'(X"0D"); - constant EWL_EVNT:std_logic_vector(7 downto 0) := std_logic_vector'(X"0E"); - constant ERP_EVNT:std_logic_vector(7 downto 0) := std_logic_vector'(X"0F"); - constant TXS_EVNT:std_logic_vector(7 downto 0) := std_logic_vector'(X"10"); - constant RXS_EVNT:std_logic_vector(7 downto 0) := std_logic_vector'(X"11"); - constant SYNC_EVNT:std_logic_vector(7 downto 0) := std_logic_vector'(X"12"); - constant STUF_EVNT:std_logic_vector(7 downto 0) := std_logic_vector'(X"13"); - constant DSTF_EVNT:std_logic_vector(7 downto 0) := std_logic_vector'(X"14"); - constant OVR_EVNT:std_logic_vector(7 downto 0) := std_logic_vector'(X"15"); + constant SOF_EVNT : std_logic_vector(7 downto 0) := x"01"; + constant ALO_EVNT : std_logic_vector(7 downto 0) := x"02"; + constant REC_EVNT : std_logic_vector(7 downto 0) := x"03"; + constant TRAN_EVNT : std_logic_vector(7 downto 0) := x"04"; + constant OVLD_EVNT : std_logic_vector(7 downto 0) := x"05"; + constant ERR_EVNT : std_logic_vector(7 downto 0) := x"06"; + constant BRS_EVNT : std_logic_vector(7 downto 0) := x"07"; + constant ARB_EVNT : std_logic_vector(7 downto 0) := x"08"; + constant CTRL_EVNT : std_logic_vector(7 downto 0) := x"09"; + constant DATA_EVNT : std_logic_vector(7 downto 0) := x"0A"; + constant CRC_EVNT : std_logic_vector(7 downto 0) := x"0B"; + constant ACK_EVNT : std_logic_vector(7 downto 0) := x"0C"; + constant NACK_EVNT : std_logic_vector(7 downto 0) := x"0D"; + constant EWL_EVNT : std_logic_vector(7 downto 0) := x"0E"; + constant ERP_EVNT : std_logic_vector(7 downto 0) := x"0F"; + constant TXS_EVNT : std_logic_vector(7 downto 0) := x"10"; + constant RXS_EVNT : std_logic_vector(7 downto 0) := x"11"; + constant SYNC_EVNT : std_logic_vector(7 downto 0) := x"12"; + constant STUF_EVNT : std_logic_vector(7 downto 0) := x"13"; + constant DSTF_EVNT : std_logic_vector(7 downto 0) := x"14"; + constant OVR_EVNT : std_logic_vector(7 downto 0) := x"15"; ----------------------------------------------------- - --constant ERR_EVNT:std_logic_vector(7 downto 0) := std_logic_vector'(X"01"); SO far pseudo random numbers for testing the data-- + --constant ERR_EVNT:std_logic_vector(7 downto 0) := x"01"; ----------------------------------------------------- - + + --SO far pseudo random numbers for testing the data-- + type rand_length is array (0 to 3809) of real; constant randData:rand_length:= (0.82197,0.63702,0.95391,0.94693,0.96661, @@ -1540,4 +1561,4 @@ package CANconstants is 0.64653,0.88287,0.51189,0.3762,0.88376); -end package; \ No newline at end of file +end package; diff --git a/src/ID_transfer.vhd b/src/ID_transfer.vhd index d609da8fdd97932f94f903cdc3ec6f4f456b2b72..fcb9ebaf784ae72b411b4a869ba200e5e8a145d1 100644 --- a/src/ID_transfer.vhd +++ b/src/ID_transfer.vhd @@ -3,7 +3,7 @@ USE IEEE.std_logic_1164.all; USE IEEE.numeric_std.ALL; USE ieee.std_logic_unsigned.All; -------------------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- -- -- CAN with Flexible Data-Rate IP Core -- @@ -28,50 +28,51 @@ USE ieee.std_logic_unsigned.All; -- Revision History: -- -- 17.1.2016 Created file -------------------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- -- Purpose: --- Package for converting between Register format of CAN Identifier and decimal format of Identifier. --- Needed by TX arbitrator and message filter when filtering data based on identifier decimal value. --- When acessing CAN Controller from software driver should take care of this conversion! ---------------------------------------------------------------------------------------------------------------- +-- Package for converting between Register format of CAN Identifier and decimal +-- format of Identifier. Needed by TX arbitrator and message filter when fil- +-- tering data based on identifier decimal value. When acessing CAN Controller +-- from software driver should take care of this conversion! +-------------------------------------------------------------------------------- package ID_transfer is ---Register value to decimal value -procedure ID_reg_to_decimal - (signal ID_reg:in std_logic_vector(28 downto 0); - signal ID_dec:out natural); - ---Decimal value to register value -procedure ID_decimal_to_reg - (signal ID_dec:in natural; - signal ID_reg:out std_logic_vector(28 downto 0)); - + --Register value to decimal value + procedure ID_reg_to_decimal + (signal ID_reg:in std_logic_vector(28 downto 0); + signal ID_dec : out natural); + + --Decimal value to register value + procedure ID_decimal_to_reg + (signal ID_dec : in natural; + signal ID_reg : out std_logic_vector(28 downto 0)); + end package ID_transfer; -package body ID_transfer is +package body ID_transfer is procedure ID_reg_to_decimal - (signal ID_reg:in std_logic_vector(28 downto 0); - signal ID_dec:out natural) is - variable base:std_logic_vector(10 downto 0); - variable ext:std_logic_vector(17 downto 0); - variable conc:std_logic_vector(28 downto 0); + (signal ID_reg : in std_logic_vector(28 downto 0); + signal ID_dec : out natural) is + variable base : std_logic_vector(10 downto 0); + variable ext : std_logic_vector(17 downto 0); + variable conc : std_logic_vector(28 downto 0); begin - base := ID_reg(10 downto 0); - ext := ID_reg(28 downto 11); - conc := base&ext; - ID_dec <= to_integer(unsigned(conc)); + base := ID_reg(10 downto 0); + ext := ID_reg(28 downto 11); + conc := base&ext; + ID_dec <= to_integer(unsigned(conc)); end procedure ID_reg_to_decimal; -procedure ID_decimal_to_reg - (signal ID_dec:in natural; - signal ID_reg:out std_logic_vector(28 downto 0)) is - variable vector:std_logic_vector(28 downto 0); + procedure ID_decimal_to_reg + (signal ID_dec : in natural; + signal ID_reg : out std_logic_vector(28 downto 0)) is + variable vector : std_logic_vector(28 downto 0); begin - vector := std_logic_vector(to_unsigned(ID_dec,29)); - ID_reg <= vector(18 downto 0)&vector(28 downto 19); + vector := std_logic_vector(to_unsigned(ID_dec, 29)); + ID_reg <= vector(18 downto 0)&vector(28 downto 19); end procedure ID_decimal_to_reg; - + end ID_transfer; diff --git a/src/rst_sync.vhd b/src/rst_sync.vhd index b765c07dc2ee92c748a7bf23c20a7c25c82f5826..6ba255465c72c4b302bef8114a0c672b558b6bdd 100644 --- a/src/rst_sync.vhd +++ b/src/rst_sync.vhd @@ -1,7 +1,7 @@ Library ieee; use ieee.std_logic_1164.all; -------------------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- -- -- CAN with Flexible Data-Rate IP Core -- @@ -27,12 +27,12 @@ use ieee.std_logic_1164.all; -- -- 27.11.2017 Created file -- -------------------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- -- Purpose: -- Asynchronouse reset synchroniser to avoid problems with Reset recovery time. -------------------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- entity rst_sync is port (