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CTU CAN FD IP Core
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canbus
CTU CAN FD IP Core
Commits
fec36762
Commit
fec36762
authored
Dec 08, 2017
by
Ille, Ondrej, Ing.
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Code formatting 1
parent
e54237d1
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src/CAN_top_level.vhd
src/CAN_top_level.vhd
+733
-536
src/CANcomponents.vhd
src/CANcomponents.vhd
+616
-751
src/CANconstants.vhd
src/CANconstants.vhd
+643
-622
src/ID_transfer.vhd
src/ID_transfer.vhd
+35
-34
src/rst_sync.vhd
src/rst_sync.vhd
+4
-4
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src/CAN_top_level.vhd
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fec36762
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src/CANcomponents.vhd
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src/CANconstants.vhd
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src/ID_transfer.vhd
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fec36762
...
...
@@ -3,7 +3,7 @@ USE IEEE.std_logic_1164.all;
USE
IEEE
.
numeric_std
.
ALL
;
USE
ieee
.
std_logic_unsigned
.
All
;
--------------------------------------------------------------------------------
-----------------------------
--------------------------------------------------------------------------------
--
-- CAN with Flexible Data-Rate IP Core
--
...
...
@@ -28,50 +28,51 @@ USE ieee.std_logic_unsigned.All;
-- Revision History:
--
-- 17.1.2016 Created file
--------------------------------------------------------------------------------
-----------------------------
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Package for converting between Register format of CAN Identifier and decimal format of Identifier.
-- Needed by TX arbitrator and message filter when filtering data based on identifier decimal value.
-- When acessing CAN Controller from software driver should take care of this conversion!
---------------------------------------------------------------------------------------------------------------
-- Package for converting between Register format of CAN Identifier and decimal
-- format of Identifier. Needed by TX arbitrator and message filter when fil-
-- tering data based on identifier decimal value. When acessing CAN Controller
-- from software driver should take care of this conversion!
--------------------------------------------------------------------------------
package
ID_transfer
is
--Register value to decimal value
procedure
ID_reg_to_decimal
(
signal
ID_reg
:
in
std_logic_vector
(
28
downto
0
);
signal
ID_dec
:
out
natural
);
--Decimal value to register value
procedure
ID_decimal_to_reg
(
signal
ID_dec
:
in
natural
;
signal
ID_reg
:
out
std_logic_vector
(
28
downto
0
));
--Register value to decimal value
procedure
ID_reg_to_decimal
(
signal
ID_reg
:
in
std_logic_vector
(
28
downto
0
);
signal
ID_dec
:
out
natural
);
--Decimal value to register value
procedure
ID_decimal_to_reg
(
signal
ID_dec
:
in
natural
;
signal
ID_reg
:
out
std_logic_vector
(
28
downto
0
));
end
package
ID_transfer
;
package
body
ID_transfer
is
package
body
ID_transfer
is
procedure
ID_reg_to_decimal
(
signal
ID_reg
:
in
std_logic_vector
(
28
downto
0
);
signal
ID_dec
:
out
natural
)
is
variable
base
:
std_logic_vector
(
10
downto
0
);
variable
ext
:
std_logic_vector
(
17
downto
0
);
variable
conc
:
std_logic_vector
(
28
downto
0
);
(
signal
ID_reg
:
in
std_logic_vector
(
28
downto
0
);
signal
ID_dec
:
out
natural
)
is
variable
base
:
std_logic_vector
(
10
downto
0
);
variable
ext
:
std_logic_vector
(
17
downto
0
);
variable
conc
:
std_logic_vector
(
28
downto
0
);
begin
base
:
=
ID_reg
(
10
downto
0
);
ext
:
=
ID_reg
(
28
downto
11
);
conc
:
=
base
&
ext
;
ID_dec
<=
to_integer
(
unsigned
(
conc
));
base
:
=
ID_reg
(
10
downto
0
);
ext
:
=
ID_reg
(
28
downto
11
);
conc
:
=
base
&
ext
;
ID_dec
<=
to_integer
(
unsigned
(
conc
));
end
procedure
ID_reg_to_decimal
;
procedure
ID_decimal_to_reg
(
signal
ID_dec
:
in
natural
;
signal
ID_reg
:
out
std_logic_vector
(
28
downto
0
))
is
variable
vector
:
std_logic_vector
(
28
downto
0
);
procedure
ID_decimal_to_reg
(
signal
ID_dec
:
in
natural
;
signal
ID_reg
:
out
std_logic_vector
(
28
downto
0
))
is
variable
vector
:
std_logic_vector
(
28
downto
0
);
begin
vector
:
=
std_logic_vector
(
to_unsigned
(
ID_dec
,
29
));
ID_reg
<=
vector
(
18
downto
0
)
&
vector
(
28
downto
19
);
vector
:
=
std_logic_vector
(
to_unsigned
(
ID_dec
,
29
));
ID_reg
<=
vector
(
18
downto
0
)
&
vector
(
28
downto
19
);
end
procedure
ID_decimal_to_reg
;
end
ID_transfer
;
src/rst_sync.vhd
View file @
fec36762
Library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
--------------------------------------------------------------------------------
-----------------------------
--------------------------------------------------------------------------------
--
-- CAN with Flexible Data-Rate IP Core
--
...
...
@@ -27,12 +27,12 @@ use ieee.std_logic_1164.all;
--
-- 27.11.2017 Created file
--
--------------------------------------------------------------------------------
-----------------------------
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-----------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Asynchronouse reset synchroniser to avoid problems with Reset recovery time.
--------------------------------------------------------------------------------
-----------------------------
--------------------------------------------------------------------------------
entity
rst_sync
is
port
(
...
...
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