Commit feb7366e authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

src: Fix combinational loop in segment end detector.

parent 76b3df9e
......@@ -873,7 +873,7 @@ package can_components is
signal sync_control : in std_logic_vector(1 downto 0);
signal sync_edge : in std_logic;
signal no_pos_resync : in std_logic;
signal segment_end : out std_logic;
signal segment_end : in std_logic;
signal is_tseg1 : in std_logic;
signal is_tseg2 : in std_logic;
signal resync_edge_valid : out std_logic;
......
......@@ -181,7 +181,7 @@ begin
-- Request is valid either when flag is captured or when combinational
-- request is valid!
segm_end_req_capt_dq(i) <= segm_end_req_capt_d(i) OR segm_end_req_capt_q(i);
segm_end_req_capt_dq(i) <= req_input(i) OR segm_end_req_capt_q(i);
end generate;
......
......@@ -94,7 +94,7 @@ entity synchronisation_checker is
signal no_pos_resync : in std_logic;
-- End of segment
signal segment_end : out std_logic;
signal segment_end : in std_logic;
-- Phase parts signalling
signal is_tseg1 : in std_logic;
......
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