Commit fe50e17d authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Fix of overload test. Error revealed by bug-fix of

integration finish during bus-start test.
parent 4e07d6b4
Pipeline #1979 passed with stages
in 5 minutes and 16 seconds
...@@ -93,6 +93,15 @@ package body overload_feature is ...@@ -93,6 +93,15 @@ package body overload_feature is
begin begin
o.outcome := true; o.outcome := true;
------------------------------------------------------------------------
-- Wait until unit comes out of integration. This is to make sure
-- that first frame will be transmitted and not that transition to
-- "interframe" will be from "off", directly after integration! This
-- transition goes directly to "interm_idle" and bit is correctly
-- interpreted as SOF and not Overload flag!
------------------------------------------------------------------------
wait_rand_cycles(rand_ctr, mem_bus(1).clk_sys, 2500, 3000);
------------------------------------------------------------------------ ------------------------------------------------------------------------
-- Generate CAN Frame and start transmission -- Generate CAN Frame and start transmission
------------------------------------------------------------------------ ------------------------------------------------------------------------
......
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