Commit fd223bc4 authored by Ondrej Ille's avatar Ondrej Ille
Browse files

driver: Re-generate regmap with latest master.

Adds up to 8 TXT buffers (number of TXT buffers now defined by generic from 2 - 8).
Adds TXTB_INFO which allows querying buffer count from HW.
Adds RETR_CTR which allows getting current value of retransmitt counter.
Adds MODE[TTTM] - Time triggered mode
Adds MODE[ROM] - Restricted operation mode
Adds MODE[RXBAM] - RX buffer automatic mode, side-effect +1 increment on RX buffer
                   read pointer by read from RX_DATA>
parent 75bb753b
Pipeline #38962 passed with stage
in 49 seconds
......@@ -74,8 +74,10 @@ enum ctu_can_fd_can_registers {
CTUCANFD_RX_DATA = 0x6c,
CTUCANFD_TX_STATUS = 0x70,
CTUCANFD_TX_COMMAND = 0x74,
CTUCANFD_TXTB_INFO = 0x76,
CTUCANFD_TX_PRIORITY = 0x78,
CTUCANFD_ERR_CAPT = 0x7c,
CTUCANFD_RETR_CTR = 0x7d,
CTUCANFD_ALC = 0x7e,
CTUCANFD_TRV_DELAY = 0x80,
CTUCANFD_SSP_CFG = 0x82,
......@@ -97,6 +99,22 @@ enum ctu_can_fd_can_registers {
CTUCANFD_TXTB4_DATA_1 = 0x400,
CTUCANFD_TXTB4_DATA_2 = 0x404,
CTUCANFD_TXTB4_DATA_20 = 0x44c,
CTUCANFD_TXTB5_DATA_1 = 0x500,
CTUCANFD_TXTB5_DATA_2 = 0x504,
CTUCANFD_TXTB5_DATA_20 = 0x54c,
CTUCANFD_TXTB6_DATA_1 = 0x600,
CTUCANFD_TXTB6_DATA_2 = 0x604,
CTUCANFD_TXTB6_DATA_20 = 0x64c,
CTUCANFD_TXTB7_DATA_1 = 0x700,
CTUCANFD_TXTB7_DATA_2 = 0x704,
CTUCANFD_TXTB7_DATA_20 = 0x74c,
CTUCANFD_TXTB8_DATA_1 = 0x800,
CTUCANFD_TXTB8_DATA_2 = 0x804,
CTUCANFD_TXTB8_DATA_20 = 0x84c,
CTUCANFD_TST_CONTROL = 0x900,
CTUCANFD_TST_DEST = 0x904,
CTUCANFD_TST_WDATA = 0x908,
CTUCANFD_TST_RDATA = 0x90c,
};
/* Control_registers memory region */
......@@ -111,10 +129,11 @@ enum ctu_can_fd_can_registers {
#define REG_MODE_STM BIT(2)
#define REG_MODE_AFM BIT(3)
#define REG_MODE_FDE BIT(4)
#define REG_MODE_TTTM BIT(5) /* From 2.3 core to be compatible with it */
#define REG_MODE_TTTM BIT(5)
#define REG_MODE_ROM BIT(6)
#define REG_MODE_ACF BIT(7)
#define REG_MODE_TSTM BIT(8)
#define REG_MODE_RXBAM BIT(9) /* From 2.3 core to be compatible with it */
#define REG_MODE_RXBAM BIT(9)
#define REG_MODE_RTRLE BIT(16)
#define REG_MODE_RTRTH GENMASK(20, 17)
#define REG_MODE_ILBP BIT(21)
......@@ -134,8 +153,11 @@ enum ctu_can_fd_can_registers {
#define REG_STATUS_EWL BIT(6)
#define REG_STATUS_IDLE BIT(7)
#define REG_STATUS_PEXS BIT(8)
#define REG_STATUS_STCNT BIT(16)
#define REG_STATUS_STRGS BIT(17)
/* COMMAND registers */
#define REG_COMMAND_RXRPMV BIT(1)
#define REG_COMMAND_RRB BIT(2)
#define REG_COMMAND_CDO BIT(3)
#define REG_COMMAND_ERCRST BIT(4)
......@@ -274,8 +296,12 @@ enum ctu_can_fd_can_registers {
#define REG_TX_STATUS_TX2S GENMASK(7, 4)
#define REG_TX_STATUS_TX3S GENMASK(11, 8)
#define REG_TX_STATUS_TX4S GENMASK(15, 12)
#define REG_TX_STATUS_TX5S GENMASK(19, 16)
#define REG_TX_STATUS_TX6S GENMASK(23, 20)
#define REG_TX_STATUS_TX7S GENMASK(27, 24)
#define REG_TX_STATUS_TX8S GENMASK(31, 28)
/* TX_COMMAND registers */
/* TX_COMMAND TXTB_INFO registers */
#define REG_TX_COMMAND_TXCE BIT(0)
#define REG_TX_COMMAND_TXCR BIT(1)
#define REG_TX_COMMAND_TXCA BIT(2)
......@@ -283,16 +309,26 @@ enum ctu_can_fd_can_registers {
#define REG_TX_COMMAND_TXB2 BIT(9)
#define REG_TX_COMMAND_TXB3 BIT(10)
#define REG_TX_COMMAND_TXB4 BIT(11)
#define REG_TX_COMMAND_TXB5 BIT(12)
#define REG_TX_COMMAND_TXB6 BIT(13)
#define REG_TX_COMMAND_TXB7 BIT(14)
#define REG_TX_COMMAND_TXB8 BIT(15)
#define REG_TX_COMMAND_TXT_BUFFER_COUNT GENMASK(19, 16)
/* TX_PRIORITY registers */
#define REG_TX_PRIORITY_TXT1P GENMASK(2, 0)
#define REG_TX_PRIORITY_TXT2P GENMASK(6, 4)
#define REG_TX_PRIORITY_TXT3P GENMASK(10, 8)
#define REG_TX_PRIORITY_TXT4P GENMASK(14, 12)
#define REG_TX_PRIORITY_TXT5P GENMASK(18, 16)
#define REG_TX_PRIORITY_TXT6P GENMASK(22, 20)
#define REG_TX_PRIORITY_TXT7P GENMASK(26, 24)
#define REG_TX_PRIORITY_TXT8P GENMASK(30, 28)
/* ERR_CAPT ALC registers */
/* ERR_CAPT RETR_CTR ALC registers */
#define REG_ERR_CAPT_ERR_POS GENMASK(4, 0)
#define REG_ERR_CAPT_ERR_TYPE GENMASK(7, 5)
#define REG_ERR_CAPT_RETR_CTR_VAL GENMASK(11, 8)
#define REG_ERR_CAPT_ALC_BIT GENMASK(20, 16)
#define REG_ERR_CAPT_ALC_ID_FIELD GENMASK(23, 21)
......
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