Commit f9bb7051 authored by Martin Jeřábek's avatar Martin Jeřábek

Merge branch 'testfw-layouts' into 'master'

Testfw layouts

See merge request !237
parents 5f6db7da 626ccb50
Pipeline #6777 failed with stages
in 40 minutes and 37 seconds
......@@ -44,7 +44,7 @@ global SILENT_SANITY
start_CAN_simulation "sanity_test_wrapper"
quietly set INST1 "can_inst_1"
quietly set CORE "core_top_comp"
quietly set CORE "can_core_comp"
################################################################################
# Adding the waves
......@@ -57,7 +57,7 @@ add_test_status_waves
# for AHDL simulation. Component path must be added to have correct path
# to internal signals
set WRCOMP $TCOMP
append WRCOMP "/i_st"
append WRCOMP "/t_sanity"
add wave $WRCOMP/error_ctr
add wave $WRCOMP/loop_ctr
......@@ -110,10 +110,10 @@ add wave -label "CAN Tx" -expand $WRCOMP/can_tx_v
add wave -label "CAN Rx" -expand $WRCOMP/can_rx_v
add wave -group "Protocol states" \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/core_top_comp/PC_State \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/core_top_comp/PC_State \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/core_top_comp/PC_State \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/core_top_comp/PC_State
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/can_core_comp/PC_State \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/can_core_comp/PC_State \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/can_core_comp/PC_State \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/can_core_comp/PC_State
if { $SILENT_SANITY == "false" } {
add wave -group "Bit time state" \
......@@ -123,16 +123,16 @@ add wave -group "Bit time state" \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/bt_FSM_out
add wave -group "Trancieve triggers" \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/core_top_comp/tran_trig \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/core_top_comp/tran_trig \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/core_top_comp/tran_trig \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/core_top_comp/tran_trig
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/can_core_comp/tran_trig \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/can_core_comp/tran_trig \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/can_core_comp/tran_trig \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/can_core_comp/tran_trig
add wave -group "Recieve triggers" \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/core_top_comp/rec_trig \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/core_top_comp/rec_trig \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/core_top_comp/rec_trig \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/core_top_comp/rec_trig
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/can_core_comp/rec_trig \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/can_core_comp/rec_trig \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/can_core_comp/rec_trig \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/can_core_comp/rec_trig
add wave -group "Hard sync edge" \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/hard_sync_edge_valid \
......@@ -141,16 +141,16 @@ add wave -group "Hard sync edge" \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/hard_sync_edge_valid
add wave -group "Synchronization type" \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/core_top_comp/sync_control \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/core_top_comp/sync_control \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/core_top_comp/sync_control \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/core_top_comp/sync_control
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/can_core_comp/sync_control \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/can_core_comp/sync_control \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/can_core_comp/sync_control \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/can_core_comp/sync_control
add wave -group "Sample control" \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/core_top_comp/sp_control \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/core_top_comp/sp_control \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/core_top_comp/sp_control \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/core_top_comp/sp_control
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/can_core_comp/sp_control \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/can_core_comp/sp_control \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/can_core_comp/sp_control \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/can_core_comp/sp_control
add wave -group "Time quantum start" \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/prescaler_comp/tq_edge \
......@@ -166,45 +166,45 @@ add wave -group "System clocks" \
}
add wave -group "Error states" \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/core_top_comp/error_state \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/core_top_comp/error_state \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/core_top_comp/error_state \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/core_top_comp/error_state
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/can_core_comp/error_state \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/can_core_comp/error_state \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/can_core_comp/error_state \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/can_core_comp/error_state
add wave -group "Operation states" \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/core_top_comp/OP_State \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/core_top_comp/OP_State \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/core_top_comp/OP_State \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/core_top_comp/OP_State
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/can_core_comp/OP_State \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/can_core_comp/OP_State \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/can_core_comp/OP_State \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/can_core_comp/OP_State
add wave -group "Identifier shift registers (Base part)" \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/core_top_comp/PC_State_comp/tran_ident_base_sr \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/core_top_comp/PC_State_comp/tran_ident_base_sr \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/core_top_comp/PC_State_comp/tran_ident_base_sr \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/core_top_comp/PC_State_comp/tran_ident_base_sr \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/can_core_comp/PC_State_comp/tran_ident_base_sr \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/can_core_comp/PC_State_comp/tran_ident_base_sr \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/can_core_comp/PC_State_comp/tran_ident_base_sr \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/can_core_comp/PC_State_comp/tran_ident_base_sr \
add wave -group "Identifiers shift registers (Extended part)" \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/core_top_comp/PC_State_comp/tran_ident_ext_sr \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/core_top_comp/PC_State_comp/tran_ident_ext_sr \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/core_top_comp/PC_State_comp/tran_ident_ext_sr \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/core_top_comp/PC_State_comp/tran_ident_ext_sr \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/can_core_comp/PC_State_comp/tran_ident_ext_sr \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/can_core_comp/PC_State_comp/tran_ident_ext_sr \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/can_core_comp/PC_State_comp/tran_ident_ext_sr \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/can_core_comp/PC_State_comp/tran_ident_ext_sr \
add wave -group "RTR flag" \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/core_top_comp/tran_is_rtr \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/core_top_comp/tran_is_rtr \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/core_top_comp/tran_is_rtr \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/core_top_comp/tran_is_rtr
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/can_core_comp/tran_is_rtr \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/can_core_comp/tran_is_rtr \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/can_core_comp/tran_is_rtr \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/can_core_comp/tran_is_rtr
add wave -group "Identifier type" \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/core_top_comp/tran_ident_type \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/core_top_comp/tran_ident_type \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/core_top_comp/tran_ident_type \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/core_top_comp/tran_ident_type
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/can_core_comp/tran_ident_type \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/can_core_comp/tran_ident_type \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/can_core_comp/tran_ident_type \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/can_core_comp/tran_ident_type
add wave -group "Frame type" \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/core_top_comp/tran_frame_type \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/core_top_comp/tran_frame_type \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/core_top_comp/tran_frame_type \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/core_top_comp/tran_frame_type
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/can_core_comp/tran_frame_type \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/can_core_comp/tran_frame_type \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/can_core_comp/tran_frame_type \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/can_core_comp/tran_frame_type
......@@ -74,8 +74,8 @@ def inject_types(h, ts):
inject_types(c, ts)
def find(h, fqn):
names = fqn.split('.')
def find_raw(h, fqn):
names = fqn.lower().split('.')
curr = h
def children(o):
return o.items if isinstance(o, types.t_record) else o.children
......@@ -112,7 +112,11 @@ def find(h, fqn):
else:
raise KeyError('{} (from {}) not found in {}'
.format(name, fqn, list(curr.children.keys())))
return curr
def find(h, fqn):
curr = find_raw(h, fqn)
if not isinstance(curr, types.t_base):
curr = curr.type
return curr
......
......@@ -74,7 +74,7 @@ def parse(s: str) -> dict:
curr_ws = 0
last = dict()
stack = [last]
for i, line in enumerate(lines[:4096]):
for i, line in enumerate(lines):
l = line.lstrip()
if not l:
continue
......
......@@ -4,6 +4,7 @@ from typing import List
import logging
import traceback
import functools
import re
from pathlib import Path
from . import ghw_parse
......@@ -47,11 +48,13 @@ class TclFuncs:
def sigtype(self, sig: str):
fqn = sig.replace('/', '.')
fqn = re.sub(r'__([0-9]+)', r'(\1)', fqn)
type = ghw_parse.find(self.hierarchy, fqn)
return type
def convsig(self, sig: str) -> str:
fqn = sig.replace('/', '.')
fqn = re.sub(r'__([0-9]+)', r'(\1)', fqn)
type = ghw_parse.find(self.hierarchy, fqn)
if ghw_parse.is_array(type):
ranges, type = ghw_parse.strip_array(type)
......@@ -60,7 +63,7 @@ class TclFuncs:
l, r = ranges[0].left, ranges[0].right
fqn += '({}:{})'.format(l, r)
fqn = 'top.' + fqn
return fqn.replace('(', '[').replace(')', ']')
return fqn.replace('(', '[').replace(')', ']').lower()
def _add_trace(self, signal, type, *, label: str, datafmt: str, expand: bool, **kwds):
if ghw_parse.is_record(type):
......@@ -78,11 +81,11 @@ class TclFuncs:
self.format = 'hex'
self.signal = None
self.isdivider = False
self.group = None
self.expand = False
self.color = None
def __init__(self):
self.group = None
self.reset()
@staticmethod
......@@ -142,8 +145,10 @@ class TclFuncs:
pass
elif a0 == '-group':
if o.group:
log.debug('Closing group {}'.format(o.group))
self.gtkw.end_group(o.group, closed=False)
o.group = args[i]
log.debug('Opening group {}'.format(o.group))
self.gtkw.begin_group(o.group, closed=False)
i += 1
elif a0[0] == '-':
......@@ -161,6 +166,7 @@ class TclFuncs:
self._add_trace(signal, type, label=o.label, datafmt=o.format, expand=o.expand, color=o.color)
o.reset()
if o.group:
log.debug('Closing group {}'.format(o.group))
self.gtkw.end_group(o.group)
......
global TCOMP
set TCOMP tb_bit_stuffing_unit_test/tb/i_test
# set TCOMP tb/i_test
proc start_CAN_simulation {test_wrapper} {
}
......
......@@ -28,6 +28,16 @@ class ReferenceTests(TestsBase):
default = self.config['default']
self.add_modelsim_gui_file(tb, default, 'sanity')
tcl = self.build / 'modelsim_init_reference.tcl'
with tcl.open('wt', encoding='utf-8') as f:
print(dedent('''\
global TCOMP
set TCOMP i_test
'''), file=f)
init_files = get_common_modelsim_init_files()
init_files += [str(tcl)]
for data_set,cfg in self.config['tests'].items():
dict_merge(cfg, default)
# bm = len_to_matrix(cfg['topology'], cfg['bus_len_v'])
......@@ -44,17 +54,8 @@ class ReferenceTests(TestsBase):
psl_opts = self.create_psl_cov_file_opt(data_set)
tb.add_config(data_set, generics=generics, sim_options=psl_opts)
else:
tb.add_config(data_set, generics=generics)
tcl = self.build / 'modelsim_init_{}.tcl'.format(data_set)
with tcl.open('wt', encoding='utf-8') as f:
print(dedent('''\
global TCOMP
set TCOMP i_test
'''), file=f)
init_files = get_common_modelsim_init_files()
init_files += [str(tcl)]
tb.add_config(data_set, generics=generics)
tb.set_sim_option("modelsim.init_files.after_load", init_files)
self.add_modelsim_gui_file(tb, cfg, data_set)
self.add_modelsim_gui_file(tb, cfg, data_set, init_files)
return True
import logging
from textwrap import dedent
from .test_common import TestsBase, add_sources, dict_merge, vhdl_serialize, \
get_seed
get_seed, get_common_modelsim_init_files
log = logging.getLogger(__name__)
......@@ -54,9 +55,19 @@ class SanityTests(TestsBase):
return {"ghdl.sim_flags" : [psl_flag]}
def configure(self):
# TODO: wave
tb = self.lib.get_test_benches('*tb_sanity')[0]
default = self.config['default']
tcl = self.build / 'modelsim_init_sanity.tcl'
with tcl.open('wt', encoding='utf-8') as f:
print(dedent('''\
global TCOMP
set TCOMP tb_sanity
'''), file=f)
init_files = get_common_modelsim_init_files()
init_files += [str(tcl)]
for name, cfg in self.config['tests'].items():
if 'wave' in cfg:
log.warn('"wave" in sanity test config {} is ignored' +
......@@ -91,5 +102,5 @@ class SanityTests(TestsBase):
else:
tb.add_config(name, generics=generics)
self.add_modelsim_gui_file(tb, default, 'sanity')
self.add_modelsim_gui_file(tb, default, 'sanity', init_files)
return True
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