Commit f96644e0 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

src: Remove explicit architectures

parent 0ec9c8ef
Pipeline #6792 passed with stages
in 13 minutes and 16 seconds
......@@ -520,26 +520,6 @@ architecture rtl of can_core is
-- Signals start of frame to rest of the design
signal sof_pulse_r : std_logic;
for operation_control_comp : operation_control
use entity work.operation_control(rtl);
for protocol_control_comp : protocol_control
use entity work.protocol_control(rtl);
for fault_confinement_comp : fault_confinement
use entity work.fault_confinement(rtl);
for crc_wrapper_comp : crc_wrapper
use entity work.crc_wrapper(rtl);
for bit_stuffing_comp : bit_stuffing
use entity work.bit_stuffing(rtl);
for bit_destuffing_comp : bit_destuffing
use entity work.bit_destuffing(rtl);
-- Internal signals to output propagation
......@@ -73,6 +73,7 @@
-- anymore.
-- 15.2.2018 Added generic amount of TXT Buffers and support for TXT
-- buffer FSM, HW commands and SW commands.
-- 18.3.2019 Remove explicit architecture assignments.
Library ieee;
......@@ -479,20 +480,6 @@ architecture rtl of CAN_top_level is
-- Transceiver delay output
signal trv_delay_out : std_logic_vector(15 downto 0);
-- Defining explicit architectures for used entites
for memory_registers_comp : memory_registers use entity work.memory_registers(rtl);
for rx_buffer_comp : rx_buffer use entity work.rx_buffer(rtl);
for tx_arbitrator_comp : tx_arbitrator use entity work.tx_arbitrator(rtl);
for frame_filters_comp : frame_filters use entity work.frame_filters(rtl);
for int_manager_comp : int_manager use entity work.int_manager(rtl);
for can_core_comp : can_core use entity work.can_core(rtl);
for prescaler_comp : prescaler use entity work.prescaler(rtl);
for bus_sampling_comp : bus_sampling use entity work.bus_sampling(rtl);
for rst_sync_comp : rst_sync use entity work.rst_sync(rtl);
-- synthesis translate_off
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