Commit f944cf98 authored by Martin Jeřábek's avatar Martin Jeřábek
Browse files

Merge branch '114-bring-the-whole-test-framework-to-ghdl' into 'master'

Fix CI pages job, optimize clock generation in tests

See merge request illeondr/CAN_FD_IP_Core!109
parents 55113fa1 7d6734f2
......@@ -54,7 +54,7 @@ test_ip_nightly:
artifacts:
when: always
paths:
- test/test_nightly.xml
- test/tests_nightly.xml
- test/xunit.xsl
pages:
......@@ -64,7 +64,7 @@ pages:
script:
- mkdir -p public
- cp test/xunit.xsl public/
- cp test/test_*.xml public/
- cp test/tests_*.xml public/
- mv test/code_html public/coverage || true
only:
- master
......
......@@ -220,16 +220,11 @@ begin
bus_level <= s_bus_level;
---------------------------------
--Clock generation
-- Clock & timestamp generation
---------------------------------
clock_gen:process
constant period : natural := f100_Mhz;
constant duty : natural := 50;
constant epsilon : natural := 0;
begin
generate_clock(period, duty, epsilon, p(i).clk_sys);
p(i).timestamp <= std_logic_vector(unsigned(p(i).timestamp)+1);
end process;
clock_gen_proc(period => f100_Mhz, duty => 50, epsilon_ppm => 0,
out_clk => p(i).clk_sys);
timestamp_gen_proc(p(i).clk_sys, p(i).timestamp);
end generate;
-- TODO: might get faster by constraining the sensitivity list
......
......@@ -65,6 +65,7 @@
-- 1.5.2018 1. Added HAL layer types and functions.
-- 2. Added Byte enable support to memory access functions.
-- 7.6.2018 Added "CAN_insert_TX_frame" procedure.
-- 18.6.2018 Added optimized clock_gen_proc, timestamp_gen_proc procedures.
--------------------------------------------------------------------------------
Library ieee;
......@@ -459,6 +460,14 @@ package CANtestLib is
----------------------------------------------------------------------------
type test_mem_type is array (0 to 255) of std_logic_vector(31 downto 0);
----------------------------------------------------------------------------
-- Clock params
----------------------------------------------------------------------------
type generate_clock_precomputed_t is record
low_time : time;
high_time : time;
end record;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
......@@ -499,13 +508,32 @@ package CANtestLib is
-- clock jitter.
--
-- Arguments:
-- par Precomputed parameters.
-- out_clk Generated clock.
----------------------------------------------------------------------------
procedure generate_clock(
constant par : in generate_clock_precomputed_t;
signal out_clk : out std_logic
);
-- deprecated compatibility wrapper (lower performance)
procedure generate_clock(
constant period : in natural;
constant duty : in natural;
constant epsilon_ppm : in natural;
signal out_clk : out std_logic
);
----------------------------------------------------------------------------
-- Combinatorial procedure, which infinitely generates clock signal.
--
-- Arguments:
-- period Period of generated clock in picoseconds.
-- duty Duty cycle of generated clock in percents.
-- epsilon_ppm Clock uncertainty (jitter) which is always added to the
-- default clock period.
-- out_clk Generated clock.
----------------------------------------------------------------------------
procedure generate_clock(
procedure clock_gen_proc(
constant period : in natural;
constant duty : in natural;
constant epsilon_ppm : in natural;
......@@ -513,6 +541,36 @@ package CANtestLib is
);
----------------------------------------------------------------------------
-- Combinatorial procedure, which infinitely generates timestamp.
--
-- Arguments:
-- clk Input clock.
-- timestamp Output timestamp counter.
----------------------------------------------------------------------------
procedure timestamp_gen_proc(
signal clk : in std_logic;
signal timestamp : out std_logic_vector(63 downto 0)
);
----------------------------------------------------------------------------
-- Precompute constants for clock signal generation for the test with
-- custom period, duty cycle and clock jitter.
--
-- Arguments:
-- period Period of generated clock in picoseconds.
-- duty Duty cycle of generated clock in percents.
-- epsilon_ppm Clock uncertainty (jitter) which is always added to the
-- default clock period.
-- Returns: precomputed params
----------------------------------------------------------------------------
function precompute_clock(
constant period : in natural;
constant duty : in natural;
constant epsilon_ppm : in natural
) return generate_clock_precomputed_t;
----------------------------------------------------------------------------
-- Reports message when severity level is lower or equal than severity
-- of message.
......@@ -1533,37 +1591,89 @@ package body CANtestLib is
end procedure;
procedure generate_clock(
function precompute_clock(
constant period : in natural;
constant duty : in natural;
constant epsilon_ppm : in natural;
signal out_clk : out std_logic
) is
constant epsilon_ppm : in natural
) return generate_clock_precomputed_t is
variable real_period : real;
variable rand_nr : real;
variable high_per : real;
variable low_per : real;
variable high_time : time;
variable low_time : time;
variable res : generate_clock_precomputed_t;
begin
-- If clock has uncertainty then it is constantly added to the clock!
-- This covers the worst case!!
-- If clock has uncertainty then it is constantly added to the clock.
-- This covers the worst case.
real_period := real(period) +
(real(period * epsilon_ppm)) / 1000000.0;
high_per := ((real(duty)) * real_period) / 100.0;
low_per := ((real(100-duty)) * real_period) / 100.0;
high_time := integer(high_per * 1000.0) * 1 ns;
high_time := high_time / 1000000;
low_time := integer(low_per * 1000.0) * 1 ns;
low_time := low_time / 1000000;
res.high_time := integer(high_per * 1000.0) * 1 ns;
res.high_time := res.high_time / 1000000;
res.low_time := integer(low_per * 1000.0) * 1 ns;
res.low_time := res.low_time / 1000000;
return res;
end function;
--Generate the clock itself
procedure generate_clock(
constant par : in generate_clock_precomputed_t;
signal out_clk : out std_logic
) is
begin
out_clk <= '1';
wait for high_time;
wait for par.high_time;
out_clk <= '0';
wait for low_time;
wait for par.low_time;
end procedure;
procedure generate_clock(
constant period : in natural;
constant duty : in natural;
constant epsilon_ppm : in natural;
signal out_clk : out std_logic
) is
constant par : generate_clock_precomputed_t := precompute_clock(period, duty, epsilon_ppm);
begin
generate_clock(par, out_clk);
end procedure;
procedure clock_gen_proc(
constant period : in natural;
constant duty : in natural;
constant epsilon_ppm : in natural;
signal out_clk : out std_logic
) is
constant par : generate_clock_precomputed_t := precompute_clock(period, duty, epsilon_ppm);
begin
loop
generate_clock(par, out_clk);
end loop;
end procedure;
procedure timestamp_gen_proc(
signal clk : in std_logic;
signal timestamp : out std_logic_vector(63 downto 0)
) is
variable ts_lo : natural := 0;
variable tmp : natural := 0;
variable ts_hi : natural := 0;
begin
loop
-- falling edge, because on rising edge, the value must stay stable
-- even after `wait for 0 ns`
wait until falling_edge(clk);
tmp := ts_lo + 1;
if tmp < ts_lo then
ts_hi := ts_hi + 1;
end if;
ts_lo := tmp;
timestamp <= std_logic_vector( to_unsigned(ts_hi, 32)
& to_unsigned(ts_lo, 32));
end loop;
end procedure;
......@@ -2133,6 +2243,7 @@ package body CANtestLib is
)is
variable data : std_logic_vector(31 downto 0) :=
(OTHERS => '0');
variable readback : std_logic_vector(31 downto 0);
begin
CAN_read(data, MODE_ADR, ID, mem_bus);
if turn_on then
......@@ -2141,6 +2252,8 @@ package body CANtestLib is
data(ENA_IND) := DISABLED;
end if;
CAN_write(data, MODE_ADR, ID, mem_bus);
CAN_read(readback, MODE_ADR, ID, mem_bus);
assert readback = data;
end procedure;
......
......@@ -129,11 +129,7 @@ begin
s_apb_pwrite => s_apb_pwrite
);
clk:process
begin
wait for 100 ns;
aclk <= not aclk;
end process;
aclk <= not aclk after 100 ns;
assert s_apb_pslverr = '0' or arstn = '0' or now = 0 fs report "Slave error!" severity error;
......
......@@ -651,13 +651,8 @@ begin
----------------------------------------------------------------------------
-- Clock generation
----------------------------------------------------------------------------
clock_gen : process
variable period :natural := f100_Mhz;
variable duty :natural := 50;
variable epsilon :natural := 0;
begin
generate_clock(period, duty, epsilon, clk_sys);
end process;
clock_gen_proc(period => f100_Mhz, duty => 50, epsilon_ppm => 0,
out_clk => clk_sys);
----------------------------------------------------------------------------
......
......@@ -185,13 +185,8 @@ begin
----------------------------------------------------------------------------
-- Clock generation
----------------------------------------------------------------------------
clock_gen : process
variable period : natural := f100_Mhz;
variable duty : natural := 50;
variable epsilon : natural := 0;
begin
generate_clock(period, duty, epsilon, clk_sys);
end process;
clock_gen_proc(period => f100_Mhz, duty => 50, epsilon_ppm => 0,
out_clk => clk_sys);
----------------------------------------------------------------------------
......
......@@ -282,13 +282,8 @@ begin
----------------------------------------------------------------------------
-- Clock generation
----------------------------------------------------------------------------
clock_gen : process
variable period :natural := f100_Mhz;
variable duty :natural := 50;
variable epsilon :natural := 0;
begin
generate_clock(period, duty, epsilon, clk_sys);
end process;
clock_gen_proc(period => f100_Mhz, duty => 50, epsilon_ppm => 0,
out_clk => clk_sys);
----------------------------------------------------------------------------
......
......@@ -298,15 +298,9 @@ begin
----------------------------------------------------------------------------
-- Clock generation
----------------------------------------------------------------------------
clock_gen : process
variable period : natural := f100_Mhz;
variable duty : natural := 50;
variable epsilon : natural := 0;
begin
generate_clock(period, duty, epsilon, clk_sys);
timestamp <= std_logic_vector(
to_unsigned(to_integer(unsigned(timestamp)) + 1, 64));
end process;
clock_gen_proc(period => f100_Mhz, duty => 50, epsilon_ppm => 0,
out_clk => clk_sys);
timestamp_gen_proc(clk_sys, timestamp);
----------------------------------------------------------------------------
......
......@@ -227,13 +227,8 @@ begin
----------------------------------------------------------------------------
-- Clock generation
----------------------------------------------------------------------------
clock_gen : process
variable period :natural := f100_Mhz;
variable duty :natural := 50;
variable epsilon :natural := 0;
begin
generate_clock(period, duty, epsilon, clk_sys);
end process;
clock_gen_proc(period => f100_Mhz, duty => 50, epsilon_ppm => 0,
out_clk => clk_sys);
----------------------------------------------------------------------------
......
......@@ -372,13 +372,8 @@ begin
----------------------------------------------------------------------------
-- Clock generation
----------------------------------------------------------------------------
clock_gen : process
variable period :natural := f100_Mhz;
variable duty :natural := 50;
variable epsilon :natural := 0;
begin
generate_clock(period, duty, epsilon, clk_sys);
end process;
clock_gen_proc(period => f100_Mhz, duty => 50, epsilon_ppm => 0,
out_clk => clk_sys);
----------------------------------------------------------------------------
......
......@@ -285,13 +285,8 @@ begin
----------------------------------------------------------------------------
-- Clock generation
----------------------------------------------------------------------------
clock_gen:process
variable period : natural := f100_Mhz;
variable duty : natural := 50;
variable epsilon : natural := 0;
begin
generate_clock(period,duty, epsilon, clk_sys);
end process;
clock_gen_proc(period => f100_Mhz, duty => 50, epsilon_ppm => 0,
out_clk => clk_sys);
-- Propagate driving bus to driving bus signals
drv_bus(DRV_FILTER_A_MASK_HIGH downto DRV_FILTER_A_MASK_LOW) <=
......
......@@ -482,12 +482,16 @@ begin
-- Clock generation
----------------------------------------------------------------------------
clock_gen : process
variable period : natural := f100_Mhz;
variable duty : natural := 50;
variable epsilon : natural := 0;
constant period : natural := f100_Mhz;
constant duty : natural := 50;
constant epsilon : natural := 0;
constant par : generate_clock_precomputed_t
:= precompute_clock(period, duty, epsilon);
begin
generate_clock(period, duty, epsilon, clk_sys);
clock_counter <= clock_counter + 1;
loop
generate_clock(par, clk_sys);
clock_counter <= clock_counter + 1;
end loop;
end process;
......
......@@ -1009,13 +1009,8 @@ begin
----------------------------------------------------------------------------
-- Clock generation
----------------------------------------------------------------------------
clock_gen : process
variable period :natural := f100_Mhz;
variable duty :natural := 50;
variable epsilon :natural := 0;
begin
generate_clock(period, duty, epsilon, clk_sys);
end process;
clock_gen_proc(period => f100_Mhz, duty => 50, epsilon_ppm => 0,
out_clk => clk_sys);
----------------------------------------------------------------------------
......
......@@ -548,14 +548,9 @@ begin
----------------------------------------------------------------------------
-- Clock and timestamp generation
----------------------------------------------------------------------------
clock_gen:process
variable period :natural := f100_Mhz;
variable duty :natural := 50;
variable epsilon :natural := 0;
begin
generate_clock(period, duty, epsilon, clk_sys);
timestamp <= std_logic_vector(unsigned(timestamp) + 1);
end process;
clock_gen_proc(period => f100_Mhz, duty => 50, epsilon_ppm => 0,
out_clk => clk_sys);
timestamp_gen_proc(clk_sys, timestamp);
-- Overall amount of errors is sum of errors from all processes
error_ctr <= stim_errs + read_errs + status_errs + cons_errs;
......
......@@ -568,14 +568,9 @@ begin
----------------------------------------------------------------------------
-- Clock and timestamp generation
----------------------------------------------------------------------------
clock_gen : process
variable period :natural := f100_Mhz;
variable duty :natural := 50;
variable epsilon :natural := 0;
begin
generate_clock(period, duty, epsilon, clk_sys);
timestamp <= std_logic_vector(unsigned(timestamp) + 1);
end process;
clock_gen_proc(period => f100_Mhz, duty => 50, epsilon_ppm => 0,
out_clk => clk_sys);
timestamp_gen_proc(clk_sys, timestamp);
errors <= error_ctr;
......
......@@ -233,13 +233,8 @@ begin
----------------------------------------------------------------------------
-- Clock generation
----------------------------------------------------------------------------
clock_gen : process
variable period : natural := f100_Mhz;
variable duty : natural := 50;
variable epsilon : natural := 0;
begin
generate_clock(period, duty, epsilon, clk_sys);
end process;
clock_gen_proc(period => f100_Mhz, duty => 50, epsilon_ppm => 0,
out_clk => clk_sys);
----------------------------------------------------------------------------
......
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