Commit f810dac7 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Added explicit warning to register descriptions. Some registers are

marked as "modify only when the core is off". This will hopefully
prevent users changing bit-rate during transmission :D
parent 4555b82c
Pipeline #5708 passed with stages
in 12 minutes and 14 seconds
......@@ -4892,7 +4892,7 @@ ENA Enable bit for the whole CAN FD Controller. When disabled, IP Core acts as i
0b1 - ENABLED - The CAN Core is enabled.
\end_layout
\begin_layout Description
NISOFD Selection between two possible CAN FD specifications.\begin_inset Newline newline\end_inset
NISOFD Selection between two possible CAN FD specifications. This bit should be modified only when SETTINGS[ENA]=0.\begin_inset Newline newline\end_inset
0b0 - ISO_FD - The CAN Controller conforms to ISO CAN FD specification.\begin_inset Newline newline\end_inset
0b1 - NON_ISO_FD - The CAN Controller conforms to NON ISO CAN FD specification.
\end_layout
......@@ -7528,7 +7528,7 @@ Address: 0x1C
Size: 4 bytes
\end_layout
\begin_layout Standard
Bit timing register for nominal bit-rate.
Bit timing register for nominal bit-rate. This register should be modified only when SETTINGS[ENA]=0.
\end_layout
\begin_layout Standard
\noindent
......@@ -8541,7 +8541,7 @@ Address: 0x20
Size: 4 bytes
\end_layout
\begin_layout Standard
Bit timing register for data bit-rate.
Bit timing register for data bit-rate. This register should be modified only when SETTINGS[ENA]=0.
\end_layout
\begin_layout Standard
\noindent
......@@ -9554,7 +9554,7 @@ Address: 0x24
Size: 1 byte
\end_layout
\begin_layout Standard
Error warning limit register.
Error warning limit register. This register should be modified only when SETTINGS[ENA]=0.
\end_layout
\begin_layout Standard
\noindent
......@@ -9826,7 +9826,7 @@ Address: 0x25
Size: 1 byte
\end_layout
\begin_layout Standard
Error passive limit register.
Error passive limit register. This register should be modified only when SETTINGS[ENA]=0.
\end_layout
\begin_layout Standard
\noindent
......@@ -10619,7 +10619,7 @@ Address: 0x28
Size: 2 bytes
\end_layout
\begin_layout Standard
Counter for received frames to enable bus traffic measurement.
Counter for received frames.
\end_layout
\begin_layout Standard
\noindent
......@@ -11134,7 +11134,7 @@ Address: 0x2A
Size: 2 bytes
\end_layout
\begin_layout Standard
Counter for transcieved frames to enable bus traffic measurement.
Counter for transcieved frames.
\end_layout
\begin_layout Standard
\noindent
......@@ -29235,7 +29235,7 @@ Reset value\end_layout
\end_layout
\begin_layout Description
TRV_DELAY_VALUE When sending CAN FD Frame with bit rate shift, transceiver delay is measured to apply secondary sampling point for bit error detection during transmission. After the measurement is done (after EDL bit) it can be read from this register. The value in this register is valid since first transmission of CAN FD frame with bit rate shift. After each next measurement the value is updated. This register can be used for transceiver TXD to RXD delay verifcation.
TRV_DELAY_VALUE When sending CAN FD Frame with bit rate shift, transceiver delay is measured. After the measurement (after EDL bit), it can be read out from this register. The value in this register is valid since first transmission of CAN FD frame with bit rate shift. After each next measurement the value is updated. This register can be used for transceiver TXD to RXD delay verifcation.
\end_layout
\begin_layout Standard
\begin_inset VSpace bigskip
......@@ -29261,7 +29261,7 @@ Address: 0x7A
Size: 2 bytes
\end_layout
\begin_layout Standard
Configuration of Secondary sampling point which is used for Transmitter in Data Bit-Rate.
Configuration of Secondary sampling point which is used for Transmitter in Data Bit-Rate. This register should be modified only when SETTINGS[ENA]=0.
\end_layout
\begin_layout Standard
\noindent
......
......@@ -548,7 +548,7 @@
<ipxact:field>
<ipxact:name>NISOFD</ipxact:name>
<ipxact:displayName>NISOFD</ipxact:displayName>
<ipxact:description>Selection between two possible CAN FD specifications.</ipxact:description>
<ipxact:description>Selection between two possible CAN FD specifications. This bit should be modified only when SETTINGS[ENA]=0.</ipxact:description>
<ipxact:bitOffset>7</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
......@@ -869,7 +869,7 @@
<ipxact:register>
<ipxact:name>BTR_FD</ipxact:name>
<ipxact:displayName>BTR_FD</ipxact:displayName>
<ipxact:description>Bit timing register for data bit-rate.</ipxact:description>
<ipxact:description>Bit timing register for data bit-rate. This register should be modified only when SETTINGS[ENA]=0.</ipxact:description>
<ipxact:dim>0</ipxact:dim>
<ipxact:addressOffset>'h20</ipxact:addressOffset>
<ipxact:size>32</ipxact:size>
......@@ -961,7 +961,7 @@
<ipxact:register>
<ipxact:name>BTR</ipxact:name>
<ipxact:displayName>BTR</ipxact:displayName>
<ipxact:description>Bit timing register for nominal bit-rate.</ipxact:description>
<ipxact:description>Bit timing register for nominal bit-rate. This register should be modified only when SETTINGS[ENA]=0.</ipxact:description>
<ipxact:dim>0</ipxact:dim>
<ipxact:addressOffset>'h1C</ipxact:addressOffset>
<ipxact:size>32</ipxact:size>
......@@ -1095,7 +1095,7 @@
<ipxact:register>
<ipxact:name>EWL</ipxact:name>
<ipxact:displayName>EWL</ipxact:displayName>
<ipxact:description>Error warning limit register.</ipxact:description>
<ipxact:description>Error warning limit register. This register should be modified only when SETTINGS[ENA]=0.</ipxact:description>
<ipxact:dim>0</ipxact:dim>
<ipxact:addressOffset>'h24</ipxact:addressOffset>
<ipxact:size>8</ipxact:size>
......@@ -1117,7 +1117,7 @@
<ipxact:register>
<ipxact:name>ERP</ipxact:name>
<ipxact:displayName>ERP</ipxact:displayName>
<ipxact:description>Error passive limit register.</ipxact:description>
<ipxact:description>Error passive limit register. This register should be modified only when SETTINGS[ENA]=0.</ipxact:description>
<ipxact:dim>0</ipxact:dim>
<ipxact:addressOffset>'h25</ipxact:addressOffset>
<ipxact:size>8</ipxact:size>
......@@ -1471,7 +1471,7 @@
</ipxact:register>
<ipxact:register>
<ipxact:name>SSP_CFG</ipxact:name>
<ipxact:description>Configuration of Secondary sampling point which is used for Transmitter in Data Bit-Rate.</ipxact:description>
<ipxact:description>Configuration of Secondary sampling point which is used for Transmitter in Data Bit-Rate. This register should be modified only when SETTINGS[ENA]=0.</ipxact:description>
<ipxact:dim>0</ipxact:dim>
<ipxact:addressOffset>'h7A</ipxact:addressOffset>
<ipxact:size>16</ipxact:size>
......@@ -1910,7 +1910,7 @@
<ipxact:field>
<ipxact:name>TRV_DELAY_VALUE</ipxact:name>
<ipxact:displayName>TRV_DELAY_VALUE</ipxact:displayName>
<ipxact:description>When sending CAN FD Frame with bit rate shift, transceiver delay is measured to apply secondary sampling point for bit error detection during transmission. After the measurement is done (after EDL bit) it can be read from this register. The value in this register is valid since first transmission of CAN FD frame with bit rate shift. After each next measurement the value is updated. This register can be used for transceiver TXD to RXD delay verifcation.</ipxact:description>
<ipxact:description>When sending CAN FD Frame with bit rate shift, transceiver delay is measured. After the measurement (after EDL bit), it can be read out from this register. The value in this register is valid since first transmission of CAN FD frame with bit rate shift. After each next measurement the value is updated. This register can be used for transceiver TXD to RXD delay verifcation.</ipxact:description>
<ipxact:bitOffset>0</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
......@@ -2530,7 +2530,7 @@
<ipxact:register>
<ipxact:name>TXC</ipxact:name>
<ipxact:displayName>TXC</ipxact:displayName>
<ipxact:description>Counter for transcieved frames to enable bus traffic measurement.</ipxact:description>
<ipxact:description>Counter for transcieved frames.</ipxact:description>
<ipxact:dim>0</ipxact:dim>
<ipxact:addressOffset>'h2A</ipxact:addressOffset>
<ipxact:size>16</ipxact:size>
......@@ -2551,7 +2551,7 @@
<ipxact:register>
<ipxact:name>RXC</ipxact:name>
<ipxact:displayName>RXC</ipxact:displayName>
<ipxact:description>Counter for received frames to enable bus traffic measurement.</ipxact:description>
<ipxact:description>Counter for received frames.</ipxact:description>
<ipxact:dim>0</ipxact:dim>
<ipxact:addressOffset>'h28</ipxact:addressOffset>
<ipxact:size>16</ipxact:size>
......
......@@ -420,7 +420,8 @@ package can_fd_register_map is
------------------------------------------------------------------------------
-- BTR register
--
-- Bit timing register for nominal bit-rate.
-- Bit timing register for nominal bit-rate. This register should be modified
-- only when SETTINGS[ENA]=0.
------------------------------------------------------------------------------
constant PROP_L : natural := 0;
constant PROP_H : natural := 6;
......@@ -443,7 +444,8 @@ package can_fd_register_map is
------------------------------------------------------------------------------
-- BTR_FD register
--
-- Bit timing register for data bit-rate.
-- Bit timing register for data bit-rate. This register should be modified onl
-- y when SETTINGS[ENA]=0.
------------------------------------------------------------------------------
constant PROP_FD_L : natural := 0;
constant PROP_FD_H : natural := 5;
......@@ -466,7 +468,8 @@ package can_fd_register_map is
------------------------------------------------------------------------------
-- EWL register
--
-- Error warning limit register.
-- Error warning limit register. This register should be modified only when SE
-- TTINGS[ENA]=0.
------------------------------------------------------------------------------
constant EW_LIMIT_L : natural := 0;
constant EW_LIMIT_H : natural := 7;
......@@ -477,7 +480,8 @@ package can_fd_register_map is
------------------------------------------------------------------------------
-- ERP register
--
-- Error passive limit register.
-- Error passive limit register. This register should be modified only when SE
-- TTINGS[ENA]=0.
------------------------------------------------------------------------------
constant ERP_LIMIT_L : natural := 8;
constant ERP_LIMIT_H : natural := 15;
......@@ -504,7 +508,7 @@ package can_fd_register_map is
------------------------------------------------------------------------------
-- RXC register
--
-- Counter for received frames to enable bus traffic measurement.
-- Counter for received frames.
------------------------------------------------------------------------------
constant RXC_VAL_L : natural := 0;
constant RXC_VAL_H : natural := 15;
......@@ -515,7 +519,7 @@ package can_fd_register_map is
------------------------------------------------------------------------------
-- TXC register
--
-- Counter for transcieved frames to enable bus traffic measurement.
-- Counter for transcieved frames.
------------------------------------------------------------------------------
constant TXC_VAL_L : natural := 16;
constant TXC_VAL_H : natural := 31;
......@@ -969,7 +973,7 @@ package can_fd_register_map is
-- SSP_CFG register
--
-- Configuration of Secondary sampling point which is used for Transmitter in
-- Data Bit-Rate.
-- Data Bit-Rate. This register should be modified only when SETTINGS[ENA]=0.
------------------------------------------------------------------------------
constant SSP_OFFSET_L : natural := 16;
constant SSP_OFFSET_H : natural := 22;
......
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