Commit f5d22838 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Added ACK generation to make sure that there are only

11 recessivve bits between two frames, not more.
parent 378b25b4
......@@ -42,9 +42,11 @@
--
-- Test sequence:
-- 1. Disable both Nodes.
-- 2. Configure Self-Test Mode on Node 1 (No ACK needed for sending)
-- 3. Generate CAN Frame with ID 10, and insert it to all 4 TXT buffers of
-- 2. Generate CAN Frame with ID 10, and insert it to all 4 TXT buffers of
-- Node 1.
-- 3. Generate ACK for Node 1 by forcing bus level to be dominant during
-- ACK Slot. This is necessary for 11 consecutive recessive bits:
-- ACK Delim + 7 EOF + 3 Interframe
-- 4. Enable Node 1, wait for some time until its integration ends.
-- 5. Now, Node 1 is transmitting. Generate CAN Frame with lower ID than
-- 10 (e.g. 9) and insert it to Node 2.
......@@ -110,12 +112,6 @@ package body bus_start_feature is
CAN_turn_controller(false, ID_1, mem_bus(1));
CAN_turn_controller(false, ID_2, mem_bus(2));
------------------------------------------------------------------------
-- Set STM in Node 1
------------------------------------------------------------------------
mode.self_test := true;
set_core_mode(mode, ID_1, mem_bus(1));
------------------------------------------------------------------------
-- Generate frame, hardcode ID to 10, Identifier type to 10
------------------------------------------------------------------------
......@@ -146,11 +142,31 @@ package body bus_start_feature is
-- Modify frame to have ID 9, and insert it to Node 2 for transmission.
-- Enable Node 2, so that it may start integration.
------------------------------------------------------------------------
wait_rand_cycles(rand_ctr, clk_sys, 10, 11);
wait_rand_cycles(rand_ctr, mem_bus(1).clk_sys, 10, 11);
CAN_frame.identifier := 9;
CAN_send_frame(CAN_frame, 1, ID_2, mem_bus(2), frame_sent);
CAN_turn_controller(true, ID_2, mem_bus(2));
------------------------------------------------------------------------
-- Generate ACK for Node 1, so that there will be for sure only 11
-- consecutive recessive bits.
------------------------------------------------------------------------
while (protocol_type'VAL(to_integer(unsigned(
iout(1).stat_bus(STAT_PC_STATE_HIGH downto STAT_PC_STATE_LOW))))
/= delim_ack)
loop
wait until rising_edge(mem_bus(1).clk_sys);
end loop;
-- Assuming default timing configuration -> 200 cycles per Bit
-- Wait through CRC Delimiter + little bit
wait_rand_cycles(rand_ctr, mem_bus(1).clk_sys, 210, 210);
so.bl_inject <= DOMINANT;
so.bl_force <= true;
wait_rand_cycles(rand_ctr, mem_bus(1).clk_sys, 200, 200);
so.bl_force <= false;
so.bl_inject <= RECESSIVE;
------------------------------------------------------------------------
-- Wait until bus is idle.
------------------------------------------------------------------------
......
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