Merge branch '359-prescaler-bug-fixes' into 'master'

Resolve "Prescaler bug-fixes"

Closes #359

See merge request !340

doc/core/ctu_can_fd_architecture.lyx

@@ -511,7 +511,7 @@ filename "version.tex"
 \noindent
 \align center
 \begin_inset Tabular
-<lyxtabular version="3" rows="8" columns="5">
+<lyxtabular version="3" rows="9" columns="5">
 <features tabularvalignment="middle">
 <column alignment="center" valignment="top" width="1.5cm">
 <column alignment="center" valignment="top" width="3cm">
@@ -858,7 +858,7 @@ Error delimiter too long
 </cell>
 </row>
 <row>
-<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
+<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
 \begin_inset Text
 
 \begin_layout Plain Layout
@@ -867,7 +867,7 @@ Error delimiter too long
 
 \end_inset
 </cell>
-<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
+<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
 \begin_inset Text
 
 \begin_layout Plain Layout
@@ -876,7 +876,7 @@ Error delimiter too long
 
 \end_inset
 </cell>
-<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
+<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
 \begin_inset Text
 
 \begin_layout Plain Layout
@@ -885,7 +885,7 @@ Ondrej Ille
 
 \end_inset
 </cell>
-<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
+<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
 \begin_inset Text
 
 \begin_layout Plain Layout
@@ -894,7 +894,7 @@ Ondrej Ille
 
 \end_inset
 </cell>
-<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
+<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
 \begin_inset Text
 
 \begin_layout Plain Layout
@@ -903,6 +903,53 @@ Add note about implementation types.
  Update Protocol control FSM to handle protocol exception.
 \end_layout
 
+\end_inset
+</cell>
+</row>
+<row>
+<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
+\begin_inset Text
+
+\begin_layout Plain Layout
+0.8
+\end_layout
+
+\end_inset
+</cell>
+<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
+\begin_inset Text
+
+\begin_layout Plain Layout
+2.3
+\end_layout
+
+\end_inset
+</cell>
+<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
+\begin_inset Text
+
+\begin_layout Plain Layout
+Ondre Ille
+\end_layout
+
+\end_inset
+</cell>
+<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
+\begin_inset Text
+
+\begin_layout Plain Layout
+18-05-2020
+\end_layout
+
+\end_inset
+</cell>
+<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
+\begin_inset Text
+
+\begin_layout Plain Layout
+Correct Expected segment lenght preload values for negative resynchronisation.
+\end_layout
+
 \end_inset
 </cell>
 </row>
@@ -32078,7 +32125,7 @@ status open
 \noindent
 \align center
 \begin_inset Tabular
-<lyxtabular version="3" rows="8" columns="3">
+<lyxtabular version="3" rows="9" columns="3">
 <features tabularvalignment="middle">
 <column alignment="left" valignment="top" width="36line%">
 <column alignment="left" valignment="top" width="30line%">
@@ -32178,7 +32225,7 @@ PH2
 \begin_inset Text
 
 \begin_layout Plain Layout
-
+Regular end of segment, no synchronisation.
 \end_layout
 
 \end_inset
@@ -32208,7 +32255,7 @@ SYNC + PROP + PH1
 \begin_inset Text
 
 \begin_layout Plain Layout
-
+Regular end of segment, no synchronisation.
 \end_layout
 
 \end_inset
@@ -32249,7 +32296,16 @@ Segment counter =
 \color red
 phase error
 \color inherit
- in this case.
+ in this case, therefore overall efect is as if TSEG1 was re-started with
+ SYNC completed as in 
+\begin_inset CommandInset citation
+LatexCommand cite
+key "key-1"
+literal "false"
+
+\end_inset
+
+.
 \end_layout
 
 \end_inset
@@ -32286,7 +32342,7 @@ SYNC + PROP + PH1 + SJW
 \begin_inset Text
 
 \begin_layout Plain Layout
-
+Lengthening of TSEG1 by SJW.
 \end_layout
 
 \end_inset
@@ -32314,7 +32370,7 @@ phase error
 \begin_inset Text
 
 \begin_layout Plain Layout
-SYNC + PROP + PH1
+SYNC + PROP + PH1 - 1
 \end_layout
 
 \end_inset
@@ -32325,7 +32381,7 @@ SYNC + PROP + PH1
 \begin_layout Plain Layout
 Immediate end of segment.
  TSEG2 ends, therefore Expected segment length register is preloaded with
- length of TSEG1.
+ length of TSEG1 - 1 (the same effect as hard synchronisation).
 \end_layout
 
 \end_inset
@@ -32337,6 +32393,45 @@ Immediate end of segment.
 
 \begin_layout Plain Layout
 
+\color red
+Negative resynchronisation
+\color inherit
+ with 
+\color red
+phase error =
+\color inherit
+ SJW + 1.
+\end_layout
+
+\end_inset
+</cell>
+<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
+\begin_inset Text
+
+\begin_layout Plain Layout
+SYNC + PROP + PH1
+\end_layout
+
+\end_inset
+</cell>
+<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
+\begin_inset Text
+
+\begin_layout Plain Layout
+Immediate end of segment.
+ TSEG2 ends since magnitude of phase error is equal to amount of SJW.
+ Length of enxt segment is preloaded.
+\end_layout
+
+\end_inset
+</cell>
+</row>
+<row>
+<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
+\begin_inset Text
+
+\begin_layout Plain Layout
+
 \color red
 Negative resynchronisation
 \color inherit
@@ -32362,7 +32457,7 @@ PH2 - SJW
 \begin_inset Text
 
 \begin_layout Plain Layout
-
+Shortening TSEG2 by SJW.
 \end_layout
 
 \end_inset

src/can_core/protocol_control_fsm.vhd

@@ -932,8 +932,8 @@ begin
         curr_state, drv_ena, err_frm_req, ctrl_ctr_zero, no_data_field,
         drv_fd_type, allow_2bit_crc_delim, allow_2bit_ack, is_receiver,
         is_bus_off, go_to_suspend, tx_frame_ready, drv_bus_off_reset_q,
-        reinteg_ctr_expired, rx_data_nbs, is_err_active, go_to_stuff_count
-        )
+        reinteg_ctr_expired, rx_data_nbs, is_err_active, go_to_stuff_count,
+        pex_on_fdf_enable, pex_on_res_enable)
     begin
         next_state <= curr_state;
 
@@ -1334,7 +1334,7 @@ begin
         go_to_suspend, frame_start, ctrl_ctr_one, drv_bus_off_reset_q,
         reinteg_ctr_expired, first_err_delim_q, go_to_stuff_count,
         crc_length_i, data_length_bits_c, ctrl_ctr_mem_index, is_bus_off,
-        block_txtb_unlock)
+        block_txtb_unlock, drv_pex)
     begin
 
         -----------------------------------------------------------------------

src/can_top_apb.vhd

@@ -136,7 +136,6 @@ begin
     apb_inst : apb_ifc
         port map (
             aclk           => aclk,
-            arstn          => arstn,
 
             reg_data_in_o  => reg_data_in,
             reg_data_out_i => reg_data_out,

src/interface/apb_ifc.vhd

@@ -71,7 +71,6 @@ entity apb_ifc is
     );
     port (
         aclk             : in  std_logic;
-        arstn            : in  std_logic;
 
         -----------------------------------------------------------------------
         -- CTU CAN FD Interface

src/lib/can_components.vhd

@@ -4448,8 +4448,7 @@ package can_components is
         );
         port (
             aclk             : in  std_logic;
-            arstn            : in  std_logic;
-
+            
             reg_data_in_o    : out std_logic_vector(31 downto 0);
             reg_data_out_i   : in  std_logic_vector(31 downto 0);
             reg_addr_o       : out std_logic_vector(15 downto 0);

src/prescaler/bit_segment_meter.vhd

@@ -301,6 +301,7 @@ architecture rtl of bit_segment_meter is
 
     -- Phase error higher than SJW
     signal phase_err_mt_sjw     : std_logic;
+    signal phase_err_eq_sjw     : std_logic;
     
     -- Exit PH2 immediately
     signal exit_ph2_immediate   : std_logic;
@@ -317,7 +318,15 @@ architecture rtl of bit_segment_meter is
     
     -- Choose basic segment length
     signal use_basic_segm_length   : std_logic;
-     
+    
+    -- Phase error = SJW + 1 -> Used for immediate segment end in case of
+    -- negative resync, since at point where edge is evaluated, bit time
+    -- should be ended!
+    signal phase_err_sjw_by_one    : std_logic;
+    
+    -- Shorten following Tseg1 by 1 due to negative resync with Phase err <= SJW
+    signal shorten_tseg1_after_tseg2 : std_logic;
+    
 begin
 
     ---------------------------------------------------------------------------
@@ -325,7 +334,8 @@ begin
     -- Re-synchronisation data-path
     ---------------------------------------------------------------------------
     ---------------------------------------------------------------------------
-    sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1') else
+    sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1' or
+                           shorten_tseg1_after_tseg2 = '1') else
                  '1' when (segm_end = '1' and is_tseg2 = '1') else
                  '1' when (segm_end = '0' and is_tseg1 = '1') else
                  '0';
@@ -335,7 +345,8 @@ begin
         resize(unsigned(tseg_2), C_BS_WIDTH);
 
     segm_extension <= 
-               to_unsigned(1, C_EXT_WIDTH) when (h_sync_valid = '1') else
+               to_unsigned(1, C_EXT_WIDTH) when (h_sync_valid = '1' or
+                                                 shorten_tseg1_after_tseg2 = '1') else
         resize(unsigned(sjw), C_EXT_WIDTH) when (phase_err_mt_sjw = '1') else
         resize(unsigned(segm_counter), C_EXT_WIDTH);
 
@@ -345,7 +356,8 @@ begin
     segm_ext_sub <= resize(basic_segm_length, C_EXP_WIDTH) -
                     resize(segm_extension, C_EXP_WIDTH);
 
-    sync_segm_length <= segm_ext_sub when (is_tseg2 = '1' or h_sync_valid = '1')
+    sync_segm_length <= segm_ext_sub when (is_tseg2 = '1' or h_sync_valid = '1' or
+                                           exit_ph2_immediate = '1')
                                      else
                         segm_ext_add;
 
@@ -354,12 +366,14 @@ begin
     --  1. Circuit start
     --  2. Segment end, but not due to hard-sync. When segment end due to hard
     --     sync occurs, we must take TSEG1 - 1 which is calculated in synced
-    --     segment length!
+    --     segment length! This also applies when there is negative resync.
+    --     due to Phase error <= SJW.
     ---------------------------------------------------------------------------
     use_basic_segm_length <= '1' when (start_edge = '1')
                                  else
                              '1' when (segm_end = '1' and
-                                       h_sync_valid = '0') 
+                                       h_sync_valid = '0' and
+                                       shorten_tseg1_after_tseg2 = '0') 
                                  else
                              '0';
     
@@ -395,6 +409,7 @@ begin
     -- Phase error calculation:
     --  1. For TSEG2: TSEG2 - Bit Time counter
     --  2. For TSEG1: Only Bit Time counter
+    --
     -- Note that subtraction in unsigned type is safe here since segm_counter
     -- is never higher than tseg_2 in tseg_2. If we are in tseg_1 neg_phase
     -- err underflows, but we don't care since we don't use it then!
@@ -410,17 +425,45 @@ begin
                             else
                         '0';
 
+    phase_err_eq_sjw <= '1' when (resize(phase_err, C_E_SJW_WIDTH) =
+                                  resize(unsigned(sjw), C_E_SJW_WIDTH))
+                            else
+                        '0'; 
+
+    phase_err_sjw_by_one <= '1' when (resize(phase_err, C_E_SJW_WIDTH) =
+                                      (resize(unsigned(sjw), C_E_SJW_WIDTH) +
+                                       to_unsigned(1, C_E_SJW_WIDTH)))
+                                else
+                            '0';
+
     sjw_mt_zero <= '1' when (unsigned(sjw) > 0) else
                    '0';
 
     ---------------------------------------------------------------------------
     -- Immediate exit occurs during PH2 when resync edge occurs.
+    -- This occurs in two cases:
+    --  1. Phase error <= SJW. Also, consecutive TSEG1 is shortened.
+    --  2. Phase error = SJW + 1. In this case immediate end also occurs,
+    --     because at the end of TQ we flip to Phase error of 5 and we must
+    --     shorten TSEG2 by SJW. In this case consecutive TSEG1 is NOT
+    --     shortened!
     ---------------------------------------------------------------------------
-    exit_ph2_immediate <= '1' when (phase_err_mt_sjw = '0' and is_tseg2 = '1' and
+    exit_ph2_immediate <= '1' when ((phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and
+                                    is_tseg2 = '1' and
                                     resync_edge_valid = '1')
                               else
                           '0';
 
+
+    ---------------------------------------------------------------------------
+    -- When negative resynchronisation occurs due to Phase error <= SJW,
+    -- we exit immediately! But we also exit immediately when Phase error
+    ---------------------------------------------------------------------------
+    shorten_tseg1_after_tseg2 <= '1' when (exit_ph2_immediate = '1' and
+                                           phase_err_sjw_by_one = '0')
+                                     else
+                                 '0';
+
     ---------------------------------------------------------------------------
     -- Regular end occurs when Bit time counter reaches expected length of
     -- segment.

src/prescaler/segment_end_detector.vhd

@@ -45,8 +45,8 @@
 --
 -- Purpose:
 --  Detects end of current segment (TSEG1 or TSEG2) as a result of Hard-sync.,
---  or request from Re-synchronisation. Provides signal for clearing Bit Time 
---  counters. Only requests from resynchronisation module which matches current
+--  or request from Bit segment meter. Provides signal for clearing Bit Time 
+--  counters. Only requests from Bit segment meter module which matches current
 --  Bit-rate is considered (Nominal resynchronisation is considered in Nominal
 --  Bit-rate, Data resynchronisation is considered in Data Bit-rate).
 --------------------------------------------------------------------------------

test/tests_fast.yml

@@ -25,8 +25,6 @@ unit:
             wave: unit/Int_Manager/intm_unit.tcl
         mess_filt:
             wave: unit/Message_filter/msft_unit.tcl
-        presc:
-            wave: unit/Prescaler/prsc_unit.tcl
         protocol_control:
             wave: unit/Protocol_Control/pctl_unit.tcl
             iterations: 100

test/unit/Prescaler/prsc_unit.gtkw

-*-27.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-@200
--Test details
-@22
-top.tb_presc_unit_test.tb.i_test.iterations
-top.tb_presc_unit_test.tb.i_test.log_level
-top.tb_presc_unit_test.tb.i_test.error_beh
-top.tb_presc_unit_test.tb.i_test.loop_ctr
-@200
--System
-@22
-top.tb_presc_unit_test.tb.i_test.res_n
-top.tb_presc_unit_test.tb.i_test.clk_sys
-@200
--DUT inputs (generated)
-@800200
--Bit time settings
-@24
-+{Time quanta (Nominal)} top.tb_presc_unit_test.tb.i_test.drv_tq_nbt[7:0]
-+{PROP_SEG (Nominal)} top.tb_presc_unit_test.tb.i_test.drv_prs_nbt[6:0]
-+{PH1_SEG (Nominal)} top.tb_presc_unit_test.tb.i_test.drv_ph1_nbt[5:0]
-+{PH2_SEG (Nominal)} top.tb_presc_unit_test.tb.i_test.drv_ph2_nbt[5:0]
-+{Synchron. jump width (Nominal)} top.tb_presc_unit_test.tb.i_test.drv_sjw_nbt[4:0]
-+{Time quanta (Data)} top.tb_presc_unit_test.tb.i_test.drv_tq_dbt[7:0]
-+{PROP_SEG (Data)} top.tb_presc_unit_test.tb.i_test.drv_prs_dbt[5:0]
-+{PH1_SEG (Data)} top.tb_presc_unit_test.tb.i_test.drv_ph1_dbt[4:0]
-+{PH2_SEG (Data)} top.tb_presc_unit_test.tb.i_test.drv_ph2_dbt[4:0]
-+{Synchron. jump width (Data)} top.tb_presc_unit_test.tb.i_test.drv_sjw_dbt[4:0]
-@1000200
--Bit time settings
-@22
-+{Synchronization edge} top.tb_presc_unit_test.tb.i_test.sync_edge
-@24
-+{Sample control} top.tb_presc_unit_test.tb.i_test.sp_control[1:0]
-+{Synchronization control} top.tb_presc_unit_test.tb.i_test.sync_control[1:0]
-@200
--DUT outputs
-@800200
--Triggerring signals
-@22
-+{SYNC (Nominal)} top.tb_presc_unit_test.tb.i_test.sync_nbt
-+{SYNC del.1 (Nominal)} top.tb_presc_unit_test.tb.i_test.sync_nbt_del_1
-+{SAMPLE (Nominal)} top.tb_presc_unit_test.tb.i_test.sample_nbt
-+{SAMPLE del.1 (Nominal)} top.tb_presc_unit_test.tb.i_test.sample_nbt_del_1
-+{SAMPLE del.2 (Nominal)} top.tb_presc_unit_test.tb.i_test.sample_nbt_del_2
-+{SYNC (Data)} top.tb_presc_unit_test.tb.i_test.sync_dbt
-+{SYNC del.1 (Data)} top.tb_presc_unit_test.tb.i_test.sync_dbt_del_1
-+{SAMPLE (Data)} top.tb_presc_unit_test.tb.i_test.sample_dbt
-+{SAMPLE del.1 (Data)} top.tb_presc_unit_test.tb.i_test.sample_dbt_del_1
-+{SAMPLE del.2 (Data)} top.tb_presc_unit_test.tb.i_test.sample_dbt_del_2
-@1000200
--Triggerring signals
-@22
-+{Bit time state} top.tb_presc_unit_test.tb.i_test.bt_fsm_out
-+{Hard sync appeared} top.tb_presc_unit_test.tb.i_test.hard_sync_edge_valid
-@200
--Testbench internals
-@24
-+{Expected bit time with resync} top.tb_presc_unit_test.tb.i_test.resync_bit_time_length
-@200
--Error counters
-@24
-+{Inform. proc. time corrupted} top.tb_presc_unit_test.tb.i_test.ipt_err_ctr
-+{Coherency checks failed} top.tb_presc_unit_test.tb.i_test.coh_err_ctr
-+{Sync signal missed} top.tb_presc_unit_test.tb.i_test.sync_seq_err_ctr
-+{Sample signal missed} top.tb_presc_unit_test.tb.i_test.sample_seq_err_ctr
-@200
--Internal DUT signals

test/unit/Prescaler/prsc_unit.tcl

-################################################################################
-## 
-## CAN with Flexible Data-Rate IP Core 
-## 
-## Copyright (C) 2017 Ondrej Ille <ondrej.ille@gmail.com>
-## 
-## Project advisor: Jiri Novak <jnovak@fel.cvut.cz>
-## Department of Measurement         (http://meas.fel.cvut.cz/)
-## Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-## Czech Technical University        (http://www.cvut.cz/)
-## 
-## Permission is hereby granted, free of charge, to any person obtaining a copy 
-## of this VHDL component and associated documentation files (the "Component"), 
-## to deal in the Component without restriction, including without limitation 
-## the rights to use, copy, modify, merge, publish, distribute, sublicense, 
-## and/or sell copies of the Component, and to permit persons to whom the 
-## Component is furnished to do so, subject to the following conditions:
-## 
-## The above copyright notice and this permission notice shall be included in 
-## all copies or substantial portions of the Component.
-## 
-## THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 
-## IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 
-## FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 
-## AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
-## LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-## FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS 
-## IN THE COMPONENT.
-## 
-## The CAN protocol is developed by Robert Bosch GmbH and protected by patents. 
-## Anybody who wants to implement this IP core on silicon has to obtain a CAN 
-## protocol license from Bosch.
-## 
-################################################################################
-
-################################################################################
-## Description:
-## 			Prescaler unit test handling script
-################################################################################
-global TCOMP
-
-start_CAN_simulation "presc_unit_test_wrapper"
-
-################################################################################
-# Adding the waves
-################################################################################
-
-#Add common waves for each test entity
-add_test_status_waves
-add_system_waves
-		
-#Add circuit specific signals
-add wave -noupdate -divider -height 20 "DUT inputs (generated)"	
-add wave -group "Bit time settings" \
-		   -label "Time quanta (Nominal)" -unsigned $TCOMP/drv_tq_nbt \
-		   -label "PROP_SEG (Nominal)" -unsigned $TCOMP/drv_prs_nbt \
-		   -label "PH1_SEG (Nominal)" -unsigned $TCOMP/drv_ph1_nbt \
-		   -label "PH2_SEG (Nominal)" -unsigned $TCOMP/drv_ph2_nbt \
-		   -label "Synchron. jump width (Nominal)" -unsigned $TCOMP/drv_sjw_nbt \
-		   -label "Time quanta (Data)" -unsigned $TCOMP/drv_tq_dbt \
-		   -label "PROP_SEG (Data)" -unsigned $TCOMP/drv_prs_dbt \
-		   -label "PH1_SEG (Data)" -unsigned $TCOMP/drv_ph1_dbt \
-		   -label "PH2_SEG (Data)" -unsigned $TCOMP/drv_ph2_dbt \
-		   -label "Synchron. jump width (Data)" -unsigned $TCOMP/drv_sjw_dbt
-		   
-add wave -label "Synchronization edge" $TCOMP/sync_edge
-add wave -label "Sample control" -unsigned $TCOMP/sp_control
-add wave -label "Synchronization control" -unsigned $TCOMP/sync_control
-
-add wave -noupdate -divider -height 20 "DUT outputs"
-add wave -group "Triggerring signals" \
-		        -label "SYNC (Nominal)" $TCOMP/sync_nbt \
-		        -label "SYNC del.1 (Nominal)" $TCOMP/sync_nbt_del_1 \
-				-label "SAMPLE (Nominal)" $TCOMP/sample_nbt \
-				-label "SAMPLE del.1 (Nominal)" $TCOMP/sample_nbt_del_1 \
-				-label "SAMPLE del.2 (Nominal)" $TCOMP/sample_nbt_del_2 \
-		        -label "SYNC (Data)" $TCOMP/sync_dbt \
-		        -label "SYNC del.1 (Data)" $TCOMP/sync_dbt_del_1 \
-				-label "SAMPLE (Data)" $TCOMP/sample_dbt \
-				-label "SAMPLE del.1 (Data)" $TCOMP/sample_dbt_del_1 \
-				-label "SAMPLE del.2 (Data)" $TCOMP/sample_dbt_del_2
-				
-add wave -label "Bit time state" $TCOMP/bt_fsm_out
-add wave -label "Hard sync appeared" $TCOMP/hard_sync_edge_valid
-
-add wave -noupdate -divider -height 20 "Testbench internals"
-add wave -label "Expected bit time with resync" -unsigned $TCOMP/resync_bit_time_length
-
-add wave -noupdate -divider -height 20 "Error counters"
-add wave -label "Inform. proc. time corrupted" \
-			-unsigned $TCOMP/ipt_err_ctr		
-				
-add wave -label "Coherency checks failed" -unsigned $TCOMP/coh_err_ctr
-add wave -label "Sync signal missed" -unsigned $TCOMP/sync_seq_err_ctr
-add wave -label "Sample signal missed" -unsigned $TCOMP/sample_seq_err_ctr
-				
-add wave -noupdate -divider -height 20 "Internal DUT signals"								
-add wave -label "FSM preset" $TCOMP/prescaler_comp/fsm_preset
-add wave -label "Time quantum start" $TCOMP/prescaler_comp/tq_edge
-add wave -label "Bit time counter" -unsigned $TCOMP/prescaler_comp/bt_counter
-add wave -label "PH1 (after sync.)" -unsigned $TCOMP/prescaler_comp/ph1_real
-add wave -label "PH2 (after sync.)" -unsigned $TCOMP/prescaler_comp/ph2_real
-								
-									 
-################################################################################
-# Execute the simulation, gather results
-################################################################################
-run_simulation
-get_test_results
-
-