Commit f2bd8951 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch '166-suspend-transmission-feature-test' into 'master'

Resolve "Suspend transmission feature test"

Closes #166

See merge request illeondr/CAN_FD_IP_Core!147
parents 0b6c0480 ca9da786
Pipeline #2017 failed with stages
in 24 minutes and 13 seconds
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com>
--
-- Project advisors and co-authors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
-- Martin Jerabek <jerabma7@fel.cvut.cz>
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Test of Suspend transmission field of Interframe space.
--
-- Test sequence:
-- 1. Set Node 1 to be error passive by configuring TX Error counter
-- to be 128. Set Node 2 to be error active by configuring both
-- Error counters to be 0.
-- 2. Read out error state of both nodes. Check that Node 1 is error
-- passive, and Node 2 is error active.
-- Loop (Forever):
-- 3. Set Error counter to 150 to force erro passive again!
-- 4. Insert frame to two TXT Buffers of Node 1. Insert frame to Node 2.
-- 5. Wait until Node 1 starts transmission.
-- 6. Insert frame to Node 2.
-- 7. Wait until frame is transmitted by Node 1 (end of EOF).
-- 8. Wait for 2 Bit times, to compensate for Intermission field! see
-- further explanation!
-- 9. Wait for N Bit times (suspend field).
-- 10. Give command to Node 2 to start Transmission.
-- 11. Check that Node 1 did become receiver, not transmitter although
-- it has frame for transmission available. It can become transmi-
-- tter only if we waited more than 7 bits (length of Suspend)!
-- Break out of loop in this case and check that N=8!
--
-- Just found out that Gedit supports insertion of emojis. Lets see how
-- this is gonna work... 🙄🤔😳🤤
--
--------------------------------------------------------------------------------
-- Revision History:
-- 2.9.2018 Created file
--------------------------------------------------------------------------------
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE ieee.math_real.ALL;
use work.CANconstants.all;
USE work.CANtestLib.All;
use work.CAN_FD_frame_format.all;
USE work.randomLib.All;
use work.pkg_feature_exec_dispath.all;
use work.CAN_FD_register_map.all;
package suspend_transmission_feature is
procedure suspend_transmission_feature_exec(
variable o : out feature_outputs_t;
signal so : out feature_signal_outputs_t;
signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE;
signal iout : in instance_outputs_arr_t;
signal mem_bus : inout mem_bus_arr_t;
signal bus_level : in std_logic
);
end package;
package body suspend_transmission_feature is
procedure suspend_transmission_feature_exec(
variable o : out feature_outputs_t;
signal so : out feature_signal_outputs_t;
signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE;
signal iout : in instance_outputs_arr_t;
signal mem_bus : inout mem_bus_arr_t;
signal bus_level : in std_logic
) is
variable ID_1 : natural := 1;
variable ID_2 : natural := 2;
variable CAN_frame : SW_CAN_frame_type;
variable frame_sent : boolean := false;
variable mode : SW_mode := (false, false, false,
false, true, false, false,
false, false, false);
variable rx_state : SW_RX_Buffer_info;
variable error_ctrs : SW_error_counters :=
(0, 0, 0, 0);
variable fault_state : SW_fault_state := fc_error_active;
variable n : integer := 0;
variable status : SW_status;
begin
o.outcome := true;
------------------------------------------------------------------------
-- Force Node 1 to error passive and Check it
------------------------------------------------------------------------
error_ctrs.rx_counter := 150;
set_error_counters(error_ctrs, ID_1, mem_bus(1));
wait for 30 ns;
get_fault_state(fault_state, ID_1, mem_bus(1));
if (fault_state /= fc_error_passive) then
-- LCOV_EXCL_START
o.outcome := false;
report "Node 1 not Error passive as expected!"
severity error;
-- LCOV_EXCL_STOP
end if;
------------------------------------------------------------------------
-- Force Node 2 to error Active and Check it!
------------------------------------------------------------------------
error_ctrs.rx_counter := 0;
set_error_counters(error_ctrs, ID_2, mem_bus(2));
wait for 30 ns;
get_fault_state(fault_state, ID_2, mem_bus(2));
if (fault_state /= fc_error_active) then
-- LCOV_EXCL_START
o.outcome := false;
report "Node 2 not Error Active as expected!"
severity error;
-- LCOV_EXCL_STOP
end if;
------------------------------------------------------------------------
-- Generate frame, hardcode ID to 514, Identifier type to BASE
------------------------------------------------------------------------
CAN_generate_frame(rand_ctr, CAN_frame);
CAN_frame.ident_type := BASE;
CAN_frame.identifier := 514;
while (true) loop
--------------------------------------------------------------------
-- Reset Error counters to 150 again.
--------------------------------------------------------------------
error_ctrs.rx_counter := 150;
set_error_counters(error_ctrs, ID_1, mem_bus(1));
--------------------------------------------------------------------
-- Send two frames from Node 1. First will start transmission.
-- Then Add the same frame to Node 2.
--------------------------------------------------------------------
CAN_send_frame(CAN_frame, 1, ID_1, mem_bus(1), frame_sent);
CAN_send_frame(CAN_frame, 2, ID_1, mem_bus(1), frame_sent);
report "Inserted 2 frames to Node 1";
wait for 500 ns;
CAN_insert_TX_frame(CAN_frame, 1, ID_2, mem_bus(2));
report "Inserted 1 frame to Node 2";
--------------------------------------------------------------------
-- Wait until the end of EOF field
--------------------------------------------------------------------
while (protocol_type'VAL(to_integer(unsigned(
iout(1).stat_bus(STAT_PC_STATE_HIGH downto
STAT_PC_STATE_LOW))))
/= eof)
loop
wait until rising_edge(mem_bus(1).clk_sys);
end loop;
while (protocol_type'VAL(to_integer(unsigned(
iout(1).stat_bus(STAT_PC_STATE_HIGH downto
STAT_PC_STATE_LOW))))
= eof)
loop
wait until rising_edge(mem_bus(1).clk_sys);
end loop;
report "End of EOF field";
wait for 20 ns;
--------------------------------------------------------------------
-- Wait for N + 2 Bit times. 3 is length of intermission. Thus if
-- we wait 2 bit times, we insert the frame in the last bit of
-- Intermission and Node 2 will start transmission right after
-- the end of Intermission.
-- If we wait for 3 bit times, we mark the frame as valid during
-- first bit of Idle, and start frame one bit after the end of
-- intermission.
-- Thisway when N equals to number of bits we waited after the
-- end of intermission.
--------------------------------------------------------------------
CAN_wait_n_bits(n + 2, true, ID_1, mem_bus(1));
report "Waited " & integer'image(n) & " bits";
-- Give command to the frame in Node 2 for transmission!
send_TXT_buf_cmd(buf_set_ready, 1, ID_2, mem_bus(2));
-- Wait until frame transmission starts on Node 1!
while (protocol_type'VAL(to_integer(unsigned(
iout(1).stat_bus(STAT_PC_STATE_HIGH downto
STAT_PC_STATE_LOW))))
/= sof)
loop
wait until rising_edge(mem_bus(1).clk_sys);
end loop;
report "Frame started";
wait for 20 ns;
-- Check Operational State of Node 1!
get_controller_status(status, ID_1, mem_bus(1));
if (status.receiver) then
if (n < 8) then
report "Unit turned receiver on bit: " & integer'image(n);
else
-- LCOV_EXCL_START
o.outcome := false;
report "Unit turned receiver after 8 bit Suspend"
severity error;
-- LCOV_EXCL_STOP
end if;
elsif (status.transmitter) then
if (n < 8) then
-- LCOV_EXCL_START
o.outcome := false;
report "Suspend transmission shorter than 8 bits!"
severity error;
-- LCOV_EXCL_STOP
else
report "Suspend transmission equal to 8 bits!";
exit;
end if;
else
-- LCOV_EXCL_START
o.outcome := false;
report "Unit in SOF, but not Transceiver nor Receiver!"
severity error;
-- LCOV_EXCL_STOP
end if;
n := n + 1;
-- Wait until unit frame is finished (Now should be by Node 2)!
CAN_wait_bus_idle(ID_1, mem_bus(1));
-- Node 1 still has one frame for transmission (the one which was
-- suspended)
CAN_wait_frame_sent(ID_1, mem_bus(1));
end loop;
------------------------------------------------------------------------
-- Now wait until Node 1 transmitts frame which lost the arbitration
-- so that we leave test environmnet withou pending frames in TXT
-- Buffers.
------------------------------------------------------------------------
CAN_wait_bus_idle(ID_1, mem_bus(1));
report "Last frame was sent!";
end procedure;
end package body;
......@@ -945,6 +945,22 @@ package CANtestLib is
signal mem_bus : inout Avalon_mem_type
);
----------------------------------------------------------------------------
-- Read Bus timing configuration from CTU CAN FD Core.
-- (duration of bit phases, synchronisation jump width, baud-rate prescaler)
--
-- Arguments:
-- bus_timing Bus timing structure that will be filled by timing
-- configuration.
-- ID Index of CTU CAN FD Core instance
-- mem_bus Avalon memory bus to execute the access on.
----------------------------------------------------------------------------
procedure CAN_read_timing_v(
variable bus_timing : out bit_time_config_type;
constant ID : in natural range 0 to 15;
signal mem_bus : inout Avalon_mem_type
);
----------------------------------------------------------------------------
-- Print Bus timing configuration of CTU CAN FD Core.
......@@ -1201,6 +1217,24 @@ package CANtestLib is
);
----------------------------------------------------------------------------
-- Reads bit timing parameters and waits for length of several bit times.
--
-- Arguments:
-- bits Number of Bit times to wait for
-- nominal "true" if Nominal Bit time should be used, "false" if
-- Data Bit Time should be used.
-- ID Index of CTU CAN FD Core instance
-- mem_bus Avalon memory bus to execute the access on.
----------------------------------------------------------------------------
procedure CAN_wait_n_bits(
constant bits : in natural;
constant nominal : in boolean;
constant ID : in natural range 0 to 15;
signal mem_bus : inout Avalon_mem_type
);
----------------------------------------------------------------------------
-- Calculate length of CAN Frame in bits (stuff bits not included).
--
......@@ -2367,6 +2401,38 @@ package body CANtestLib is
end procedure;
procedure CAN_read_timing_v(
variable bus_timing : out bit_time_config_type;
constant ID : in natural range 0 to 15;
signal mem_bus : inout Avalon_mem_type
)is
variable data : std_logic_vector(31 downto 0);
begin
-- Bit timing register - Nominal
CAN_read(data, BTR_ADR, ID, mem_bus);
bus_timing.tq_nbt := to_integer(unsigned(data(BRP_H downto BRP_L)));
bus_timing.prop_nbt := to_integer(unsigned(data(PROP_H downto PROP_L)));
bus_timing.ph1_nbt := to_integer(unsigned(data(PH1_H downto PH1_L)));
bus_timing.ph2_nbt := to_integer(unsigned(data(PH2_H downto PH2_L)));
bus_timing.sjw_nbt := to_integer(unsigned(data(SJW_H downto SJW_L)));
-- Bit timing register - Data
CAN_read(data, BTR_FD_ADR, ID, mem_bus);
bus_timing.tq_dbt := to_integer(unsigned(data(BRP_FD_H downto
BRP_FD_L)));
bus_timing.prop_dbt := to_integer(unsigned(data(PROP_FD_H downto
PROP_FD_L)));
bus_timing.ph1_dbt := to_integer(unsigned(data(PH1_FD_H downto
PH1_FD_L)));
bus_timing.ph2_dbt := to_integer(unsigned(data(PH2_FD_H downto
PH2_FD_L)));
bus_timing.sjw_dbt := to_integer(unsigned(data(SJW_FD_H downto
SJW_FD_L)));
end procedure;
procedure CAN_print_timing(
constant bus_timing : in bit_time_config_type
)is
......@@ -3008,7 +3074,6 @@ package body CANtestLib is
variable r_data : std_logic_vector(31 downto 0) :=
(OTHERS => '0');
begin
-- Wait until unit starts to transmitt or recieve
CAN_read(r_data, MODE_ADR, ID, mem_bus);
while (r_data(RS_IND) = '0' and r_data(TS_IND) = '0') loop
......@@ -3020,7 +3085,46 @@ package body CANtestLib is
while (r_data(ET_IND) = '0') loop
CAN_read(r_data, MODE_ADR, ID, mem_bus);
end loop;
end procedure;
procedure CAN_wait_n_bits(
constant bits : in natural;
constant nominal : in boolean;
constant ID : in natural range 0 to 15;
signal mem_bus : inout Avalon_mem_type
)is
variable bus_timing : bit_time_config_type;
variable wait_time : integer := 0;
begin
-- Read config of the node
CAN_read_timing_v(bus_timing, ID, mem_bus);
-- Calculate number of clock cycles to wait
if (nominal) then
wait_time := bus_timing.tq_nbt *
(bus_timing.prop_nbt + bus_timing.ph1_nbt +
bus_timing.ph2_nbt + 1);
else
wait_time := bus_timing.tq_dbt *
(bus_timing.prop_dbt + bus_timing.ph1_dbt +
bus_timing.ph2_dbt + 1);
end if;
-- Check Minimal Bit time
if (wait_time < 7) then
report "Calculated Bit Time shorter than minimal!" severity error;
end if;
-- Count number of bits to wait
-- Reading config took some time too, correct "wait_time" by 4 cycles
wait_time := wait_time * bits;
wait_time := wait_time - 4;
-- Wait for calculated amount of clock cycles!
for i in 0 to wait_time - 1 loop
wait until rising_edge(mem_bus.clk_sys);
end loop;
end procedure;
......
_default: &default
log_level: info
error_tolerance: 0
# seed: 0 # optional; use to reconstruct results from randomized runs
# randomize: false
feature:
default:
<<: *default
iterations: 1
timeout: 100 ms
wave: feature/feature_env_setup.tcl
tests:
suspend_transmission:
......@@ -63,6 +63,7 @@ feature:
rtr_pref:
data_length_code:
bus_start:
suspend_transmission:
reference:
default:
<<: *default
......
......@@ -92,6 +92,7 @@ feature:
rtr_pref:
data_length_code:
bus_start:
suspend_transmission:
sanity:
default:
<<: *default
......
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