Commit f29ca930 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Changed transceive Identifier to shift registers

from direct access.
parent 9cb8c51a
......@@ -226,7 +226,8 @@ entity core_top is
signal alc : std_logic_vector(4 downto 0);
--Transcieve buffer output
signal tran_ident : std_logic_vector(28 downto 0);
signal tran_ident_base : std_logic_vector(10 downto 0);
signal tran_ident_ext : std_logic_vector(17 downto 0);
signal tran_dlc : std_logic_vector(3 downto 0);
signal tran_is_rtr : std_logic;
signal tran_ident_type : std_logic;
......@@ -370,7 +371,9 @@ begin
tran_brs_in => tran_brs_in,
frame_store => frame_Store,
tran_ident => tran_ident,
tran_ident_base => tran_ident_base,
tran_ident_ext => tran_ident_ext,
tran_dlc => tran_dlc,
tran_is_rtr => tran_is_rtr,
tran_ident_type => tran_ident_type,
......@@ -406,7 +409,8 @@ begin
alc => alc,
tran_data => tran_data_in,
tran_ident => tran_ident,
tran_ident_base => tran_ident_base,
tran_ident_ext => tran_ident_ext,
tran_dlc => tran_dlc,
tran_is_rtr => tran_is_rtr,
tran_ident_type => tran_ident_type,
......@@ -659,11 +663,11 @@ begin
---------------------
--CRC Multiplexing --
---------------------
crc15<=crc15_wbs_tx when (OP_State = transciever and tran_frame_type = FD_CAN) else
crc15_nbs_tx when (OP_State = transciever and tran_frame_type = NORMAL_CAN) else
crc15_wbs_rx when (OP_State = reciever and rec_frame_type = FD_CAN) else
crc15_nbs_rx when (OP_State = reciever and rec_frame_type = NORMAL_CAN) else
"000000000000000";
crc15<=crc15_wbs_tx when (OP_State = transciever and tran_frame_type = FD_CAN) else
crc15_nbs_tx when (OP_State = transciever and tran_frame_type = NORMAL_CAN) else
crc15_wbs_rx when (OP_State = reciever and rec_frame_type = FD_CAN) else
crc15_nbs_rx when (OP_State = reciever and rec_frame_type = NORMAL_CAN) else
"000000000000000";
crc17<=crc17_wbs_tx when (OP_State = transciever and tran_frame_type = FD_CAN) else
crc17_nbs_tx when (OP_State = transciever and tran_frame_type = NORMAL_CAN) else
......@@ -834,7 +838,7 @@ begin
stat_bus(STAT_BDS_LENGTH_HIGH downto STAT_BDS_LENGTH_LOW) <= bds_length;
--Transcieve data interface
stat_bus(STAT_TRAN_IDENT_HIGH downto STAT_TRAN_IDENT_LOW) <= tran_ident;
stat_bus(STAT_TRAN_IDENT_HIGH downto STAT_TRAN_IDENT_LOW) <= tran_ident_ext&tran_ident_base;
stat_bus(STAT_TRAN_DLC_HIGH downto STAT_TRAN_DLC_LOW) <= tran_dlc;
stat_bus(STAT_TRAN_IS_RTR_INDEX) <= tran_is_rtr;
stat_bus(STAT_TRAN_IDENT_TYPE_INDEX) <= tran_ident_type;
......
......@@ -168,7 +168,8 @@ entity protocolControl is
--Transcieve buffer interface--
-------------------------------
signal tran_data :in std_logic_vector(31 downto 0);
signal tran_ident :in std_logic_vector(28 downto 0);
signal tran_ident_base :in std_logic_vector(10 downto 0);
signal tran_ident_ext :in std_logic_vector(17 downto 0);
signal tran_dlc :in std_logic_vector(3 downto 0);
signal tran_is_rtr :in std_logic;
signal tran_ident_type :in std_logic;
......@@ -501,6 +502,10 @@ entity protocolControl is
-- This is to fix lost of arbitration in last bit!!!
signal delay_control_trans : std_logic;
--Transceive identifier shift registers
signal tran_ident_base_sr : std_logic_vector(10 downto 0);
signal tran_ident_ext_sr : std_logic_vector(17 downto 0);
--------------------------
--Control field registers-
--------------------------
......@@ -799,6 +804,9 @@ begin
alc_r <= (OTHERS=>'0');
data_size <= 0;
tran_ident_base_sr <= (OTHERS => '0');
tran_ident_ext_sr <= (OTHERS => '0');
--Nulling recieve registers
rec_ident_base_sr <= (OTHERS=>'0');
rec_ident_ext_sr <= (OTHERS=>'0');
......@@ -813,7 +821,7 @@ begin
rec_data_sr <= (OTHERS => '0');
-- Pointer directly to TXT Buffer RAM
txt_buf_ptr_r <= 0;
txt_buf_ptr_r <= 0;
--Presetting the sampling point control
sp_control_r <= NOMINAL_SAMPLE;
......@@ -868,6 +876,9 @@ begin
arb_state <= arb_state;--Arbitration control state machine
arb_two_bits <= arb_two_bits;
tran_ident_base_sr <= tran_ident_base_sr;
tran_ident_ext_sr <= tran_ident_ext_sr;
--Stored value of bit behind Identifier extension (RTR,r1)
arb_one_bit <= arb_one_bit;
......@@ -1063,7 +1074,12 @@ begin
--The index in tran_ident in where MSB bit of the
--base ident is 10
tran_pointer <= 10;
tran_pointer <= 10;
--Load the Identifier transmission shift registers
tran_ident_base_sr <= tran_ident_base;
tran_ident_ext_sr <= tran_ident_ext;
arb_state <= base_id;
crc_enable_r <= '1';
......@@ -1163,7 +1179,11 @@ begin
when base_id =>
if(tran_trig='1')then
if(OP_state=transciever)then
data_tx_r <= tran_ident(tran_pointer);
--Direct addressing replaced by shift register
data_tx_r <= tran_ident_base_sr(10);
tran_ident_base_sr <= tran_ident_base_sr(9 downto 0)&'0';
--data_tx_r <= tran_ident(tran_pointer);
else
data_tx_r <= RECESSIVE;
end if;
......@@ -1263,7 +1283,12 @@ begin
when ext_id=>
if(tran_trig='1')then
if(OP_state=transciever)then
data_tx_r <= tran_ident(tran_pointer);
--Replaced direct access by shift register
data_tx_r <= tran_ident_ext_sr(17);
tran_ident_ext_sr <= tran_ident_ext_sr(16 downto 0)&'0';
--data_tx_r <= tran_ident(tran_pointer);
else
data_tx_r <= RECESSIVE;
end if;
......
......@@ -71,7 +71,8 @@ entity tranBuffer is
--------------------------------
--Stored data register outputs--
--------------------------------
signal tran_ident :out std_logic_vector(28 downto 0);
signal tran_ident_base :out std_logic_vector(10 downto 0);
signal tran_ident_ext :out std_logic_vector(17 downto 0);
signal tran_dlc :out std_logic_vector(3 downto 0);
signal tran_is_rtr :out std_logic;
signal tran_ident_type :out std_logic;
......@@ -83,7 +84,8 @@ entity tranBuffer is
----------------------
--Internal registers--
----------------------
signal tran_ident_reg: std_logic_vector(28 downto 0);
signal tran_ident_base_reg: std_logic_vector(10 downto 0);
signal tran_ident_ext_reg: std_logic_vector(17 downto 0);
signal tran_dlc_reg: std_logic_vector(3 downto 0);
signal tran_is_rtr_reg: std_logic;
signal tran_ident_type_reg: std_logic;
......@@ -95,7 +97,8 @@ end entity;
architecture rtl of tranBuffer is
begin
tran_ident <= tran_ident_reg;
tran_ident_base <= tran_ident_base_reg;
tran_ident_ext <= tran_ident_ext_reg;
tran_dlc <= tran_dlc_reg;
tran_is_rtr <= tran_is_rtr_reg;
tran_ident_type <= tran_ident_type_reg;
......@@ -105,7 +108,8 @@ begin
data_store:process(clk_sys,res_n)
begin
if res_n=ACT_RESET then
tran_ident_reg <= (OTHERS =>'0');
tran_ident_base_reg <= (OTHERS =>'0');
tran_ident_ext_reg <= (OTHERS =>'0');
tran_dlc_reg <= (OTHERS =>'0');
tran_is_rtr_reg <= '0';
tran_ident_type_reg <= '0';
......@@ -113,14 +117,16 @@ begin
tran_brs_reg <= '0';
elsif rising_edge(clk_sys)then
if(frame_store='1')then
tran_ident_reg <= tran_ident_in;
tran_ident_base_reg <= tran_ident_in(10 downto 0);
tran_ident_ext_reg <= tran_ident_in(28 downto 11);
tran_dlc_reg <= tran_dlc_in;
tran_is_rtr_reg <= tran_is_rtr_in;
tran_ident_type_reg <= tran_ident_type_in;
tran_frame_type_reg <= tran_frame_type_in;
tran_brs_reg <= tran_brs_in;
else
tran_ident_reg <= tran_ident_reg;
tran_ident_base_reg <= tran_ident_base_reg;
tran_ident_ext_reg <= tran_ident_ext_reg;
tran_dlc_reg <= tran_dlc_reg;
tran_is_rtr_reg <= tran_is_rtr_reg;
tran_ident_type_reg <= tran_ident_type_reg;
......
......@@ -491,7 +491,8 @@ package CANcomponents is
signal tran_frame_type_in : in std_logic;
signal tran_brs_in : in std_logic;
signal frame_store : in std_logic;
signal tran_ident : out std_logic_vector(28 downto 0);
signal tran_ident_base : out std_logic_vector(10 downto 0);
signal tran_ident_ext : out std_logic_vector(17 downto 0);
signal tran_dlc : out std_logic_vector(3 downto 0);
signal tran_is_rtr : out std_logic;
signal tran_ident_type : out std_logic;
......@@ -571,7 +572,8 @@ package CANcomponents is
signal PC_State_out : out protocol_type;
signal alc : out std_logic_vector(4 downto 0);
signal tran_data : in std_logic_vector(31 downto 0);
signal tran_ident : in std_logic_vector(28 downto 0);
signal tran_ident_base : in std_logic_vector(10 downto 0);
signal tran_ident_ext : in std_logic_vector(17 downto 0);
signal tran_dlc : in std_logic_vector(3 downto 0);
signal tran_is_rtr : in std_logic;
signal tran_ident_type : in std_logic;
......
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