Commit f0c8161c authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

test: Debug Error rules A feature test.

Test must not skip stuff bits. Otherwise if stuff bit is corrupted
randomly, then it will also remain forcing the bus value to opposite
value during first bit of Error flag, thus REC will increment more!
parent 1bd3f6aa
Pipeline #15821 passed with stage
in 17 seconds
......@@ -126,7 +126,7 @@ package body error_rules_a_feature is
wait until iout(2).can_tx = DOMINANT;
force_bus_level(RECESSIVE, so.bl_force, so.bl_inject);
CAN_wait_sample_point(iout(2).stat_bus);
CAN_wait_sample_point(iout(2).stat_bus, false);
wait for 20 ns;
get_controller_status(status, ID_2, mem_bus(2));
......
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