Commit eef57ebd authored by Martin Jeřábek's avatar Martin Jeřábek

remove trailing whitespace

parent 465f630d
--------------------------------------------------------------------------------
--
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com>
--
-- Project advisors and co-authors:
--
-- Project advisors and co-authors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
-- Martin Jerabek <jerabma7@fel.cvut.cz>
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Main environment for feature tests
--
-- Main environment for feature tests
--
--------------------------------------------------------------------------------
-- Revision History:
-- 20.6.2016 Created file
......@@ -58,7 +58,7 @@ use work.ID_transfer.all;
architecture feature_env_test of CAN_feature_test is
----------------------------------------------------------------------------
-- Controller 1 signals
-- Controller 1 signals
----------------------------------------------------------------------------
signal clk_sys_1 : std_logic := '0';
signal res_n_1 : std_logic := '0';
......@@ -81,7 +81,7 @@ architecture feature_env_test of CAN_feature_test is
----------------------------------------------------------------------------
-- Controller 2 signals
-- Controller 2 signals
----------------------------------------------------------------------------
signal clk_sys_2 : std_logic := '0';
signal res_n_2 : std_logic := '0';
......@@ -110,12 +110,12 @@ architecture feature_env_test of CAN_feature_test is
----------------------------------------------------------------------------
signal hw_reset_on_new_test : boolean := true;
signal iteration_done : boolean := false;
-- Test name to be loaded by the TCL script from TCL test FIFO
-- Note that string always have to have fixed length
signal test_name : string (1 to 20) :=
" overload";
-- CAN bus signals
signal bus_level : std_logic := RECESSIVE;
signal tr_del_1_sr : std_logic_vector(255 downto 0) :=
......@@ -124,10 +124,10 @@ architecture feature_env_test of CAN_feature_test is
(OTHERS => RECESSIVE);
signal tr_del_1 : natural := 20;
signal tr_del_2 : natural := 20;
begin
CAN_inst_1 : CAN_top_level
CAN_inst_1 : CAN_top_level
generic map(
use_logger => true,
rx_buffer_size => 64,
......@@ -199,8 +199,8 @@ begin
srd_2 <= mem_bus_2.srd;
sbe_2 <= mem_bus_2.sbe;
mem_bus_2.data_out <= data_out_2;
----------------------------------------------------------------------------
-- Transciever and CAN bus realization
----------------------------------------------------------------------------
......@@ -216,15 +216,15 @@ begin
tr_del_2_sr <= tr_del_2_sr(254 downto 0) & CAN_tx_2;
end process;
bus_level <= tr_del_1_sr(tr_del_1) and tr_del_2_sr(tr_del_2)
bus_level <= tr_del_1_sr(tr_del_1) and tr_del_2_sr(tr_del_2)
when (bl_force = false)
else
bl_inject;
CAN_rx_1 <= bus_level;
CAN_rx_2 <= bus_level;
----------------------------------------------------------------------------
-- Clock generation (1)
----------------------------------------------------------------------------
......@@ -248,9 +248,9 @@ begin
begin
generate_clock(period, duty, epsilon, clk_sys_2);
timestamp_2 <= std_logic_vector(unsigned(timestamp_2) + 1);
end process;
end process;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Test process listening to higher hierarchy wrapper!
......@@ -281,8 +281,8 @@ begin
loop
log("Starting loop nr " & integer'image(loop_ctr),
info_l, log_level);
-- Wait on signal from higher level wrapper to move to
-- Wait on signal from higher level wrapper to move to
-- next iteration.
wait until iteration_done = true;
......@@ -293,7 +293,7 @@ begin
wait until run = false;
wait until run = true;
end process;
end architecture;
Library ieee;
......@@ -322,10 +322,10 @@ use work.overload_feature.All;
--------------------------------------------------------------------------------
-- Test wrapper and control signals generator
-- Test wrapper and control signals generator
--------------------------------------------------------------------------------
architecture feature_env_test_wrapper of CAN_test_wrapper is
architecture feature_env_test_wrapper of CAN_test_wrapper is
-- Test component itself
component CAN_feature_test is
port (
......@@ -343,13 +343,13 @@ architecture feature_env_test_wrapper of CAN_test_wrapper is
);
end component;
for test_comp : CAN_feature_test use entity
for test_comp : CAN_feature_test use entity
work.CAN_feature_test(feature_env_test);
signal run : boolean;
signal status_int : test_status_type;
signal errors : natural;
signal mem_bus_1 : Avalon_mem_type := ('0', (OTHERS => '0'),
(OTHERS => '0'), (OTHERS => '0'), '0', '0', '0',
(OTHERS => '0'));
......@@ -384,7 +384,7 @@ architecture feature_env_test_wrapper of CAN_test_wrapper is
arbitration_feature_exec(outcome, rand_ctr, mem_bus_1, mem_bus_2,
bus_level, drv_bus_1, drv_bus_2,
stat_bus_1, stat_bus_2);
elsif (test_name = " rx_status") then
rx_status_feature_exec(outcome, rand_ctr, mem_bus_1, mem_bus_2,
bus_level, drv_bus_1, drv_bus_2, stat_bus_1,
......@@ -444,17 +444,17 @@ architecture feature_env_test_wrapper of CAN_test_wrapper is
retr_limit_feature_exec(outcome, rand_ctr, mem_bus_1, mem_bus_2,
bus_level, drv_bus_1, drv_bus_2, stat_bus_1,
stat_bus_2);
elsif (test_name = " overload") then
overload_feature_exec(outcome, rand_ctr, mem_bus_1, mem_bus_2,
bus_level, drv_bus_1, drv_bus_2, stat_bus_1,
stat_bus_2, bl_inject, bl_force);
stat_bus_2, bl_inject, bl_force);
end if;
end procedure;
----------------------------------------------------------------------------
-- Restarts memory buses for
-- Restarts memory buses for
----------------------------------------------------------------------------
procedure restart_mem_bus(
signal mem_bus_1 :out Avalon_mem_type;
......@@ -488,9 +488,9 @@ architecture feature_env_test_wrapper of CAN_test_wrapper is
signal bl_inject : std_logic := RECESSIVE;
signal bl_force : boolean := false;
begin
error_tol_int <= error_tol;
error_beh_int <= error_beh;
......@@ -510,7 +510,7 @@ begin
bl_inject => bl_inject,
bl_force => bl_force
);
----------------------------------------------------------------------------
----------------------------------------------------------------------------
......@@ -520,10 +520,10 @@ begin
test : process
variable outcome : boolean := false;
alias iteration_done is
alias iteration_done is
<<signal test_comp.iteration_done : boolean>>;
alias hw_reset is
alias hw_reset is
<<signal test_comp.hw_reset_on_new_test : boolean>>;
alias test_name is
......@@ -535,7 +535,7 @@ begin
alias hw_reset_2 is
<<signal test_comp.res_n_2 : std_logic>>;
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Internal signals of CAN controllers
------------------------------------------------------------------------
alias bus_level is
......@@ -565,20 +565,20 @@ begin
variable ID_1 : natural range 0 to 15 := 1;
variable ID_2 : natural range 0 to 15 := 2;
begin
-- Set the process to run and wait until it comes out of reset
iteration_done <= false;
hw_reset <= true;
run <= true;
error_ctr <= 0;
restart_mem_bus(mem_bus_1, mem_bus_2);
wait for 10 ns;
wait until hw_reset_1 = '1' and hw_reset_2 = '1';
wait for 10 ns;
status <= running;
-- Execute the controllers configuration
CAN_turn_controller(true, ID_1, mem_bus_1);
CAN_turn_controller(true, ID_2, mem_bus_2);
......@@ -589,7 +589,7 @@ begin
------------------------------------------------------------------------
CAN_enable_retr_limit(true, 0, ID_1, mem_bus_1);
CAN_enable_retr_limit(true, 0, ID_2, mem_bus_2);
------------------------------------------------------------------------
-- Main test loop
------------------------------------------------------------------------
......@@ -597,10 +597,10 @@ begin
iteration_done <=false;
exec_feature_test(test_name, outcome, rand_ctr, mem_bus_1,
mem_bus_2, int_1, int_2, bus_level, drv_bus_1,
mem_bus_2, int_1, int_2, bus_level, drv_bus_1,
drv_bus_2, stat_bus_1, stat_bus_2, bl_inject,
bl_force);
if (outcome = false) then
process_error(error_ctr, error_beh_int, exit_imm);
end if;
......@@ -610,9 +610,9 @@ begin
wait for 10 ns;
end loop;
run <= false;
run <= false;
evaluate_test(error_tol_int, error_ctr, status);
wait for 100 ns;
end process;
end;
--------------------------------------------------------------------------------
--
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com>
--
-- Project advisors and co-authors:
--
-- Project advisors and co-authors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
-- Martin Jerabek <jerabma7@fel.cvut.cz>
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Unit test for the RX Buffer circuit.
--
-- Following test instantiates RX Buffer. Stimuli generator generates input
-- frames as CAN_Core would do. Then it checks whether frame was stored into
-- Following test instantiates RX Buffer. Stimuli generator generates input
-- frames as CAN_Core would do. Then it checks whether frame was stored into
-- the buffer! Another process reads the data as user would do by memory access.
-- Both, data written into the buffer, and data read from the buffer are stored
-- into test memories (in_mem,out_mem). When test memory is full content of
-- into test memories (in_mem,out_mem). When test memory is full content of
-- both memories is compared! When mismatch occurs test fails. Each time memory
-- is filled test moves to the next iteration.
--
--------------------------------------------------------------------------------
-- Revision History:
-- 1.6.2016 Created file
-- 22.6.2016 Updated testbench to cover also the modified functionality of
-- RX Buffer. Now ESI bit is also stored and compared. Also RTR
-- frame of CAN normal frame does not store any data words into
-- 22.6.2016 Updated testbench to cover also the modified functionality of
-- RX Buffer. Now ESI bit is also stored and compared. Also RTR
-- frame of CAN normal frame does not store any data words into
-- the buffer.
--
--
--------------------------------------------------------------------------------
Library ieee;
......@@ -71,7 +71,7 @@ use work.CAN_FD_register_map.all;
use work.CAN_FD_frame_format.all;
architecture rx_buf_unit_test of CAN_test is
-- System clock and reset
signal clk_sys : std_logic := '0';
signal res_n : std_logic := '0';
......@@ -111,7 +111,7 @@ architecture rx_buf_unit_test of CAN_test is
signal rx_read_pointer_pos : std_logic_vector(11 downto 0);
signal rx_write_pointer_pos : std_logic_vector(11 downto 0);
signal rx_data_overrun : std_logic;
signal rx_read_buff : std_logic_vector(31 downto 0);
-- Driving bus aliases
......@@ -131,8 +131,8 @@ architecture rx_buf_unit_test of CAN_test is
-- Error counters
signal stim_errs : natural := 0;
signal read_errs : natural := 0;
signal status_errs : natural := 0;
signal cons_errs : natural := 0;
signal status_errs : natural := 0;
signal cons_errs : natural := 0;
-- Dummy signals
signal exit_imm_d : boolean := false;
......@@ -157,7 +157,7 @@ architecture rx_buf_unit_test of CAN_test is
signal in_pointer : natural := 0;
signal out_pointer : natural := 0;
signal mod_pointer : natural := 0;
constant buff_size : natural := 32;
......@@ -189,12 +189,12 @@ architecture rx_buf_unit_test of CAN_test is
memory(in_pointer + 1) <= "000" & hw_id;
-- TIMESTAMP_U_W and TIMESTAMP_L_W
-- TIMESTAMP_U_W and TIMESTAMP_L_W
memory(in_pointer + 2) <= frame.timestamp(31 downto 0);
-- Note that here we have to store timestamp increased by two, because
-- timestamp is in this test increasing by one every clock cycle!!
-- thus when timestamp is acutally stored into RX buffer it is two
-- timestamp is in this test increasing by one every clock cycle!!
-- thus when timestamp is acutally stored into RX buffer it is two
-- clock cycles later!!!
memory(in_pointer + 3) <= std_logic_vector(unsigned(
frame.timestamp(63 downto 32)));
......@@ -206,7 +206,7 @@ architecture rx_buf_unit_test of CAN_test is
if (frame.rtr = RTR_FRAME) then
length := 0;
else
decode_dlc_v(frame.dlc, length);
decode_dlc_v(frame.dlc, length);
end if;
-- Store the data
......@@ -259,7 +259,7 @@ architecture rx_buf_unit_test of CAN_test is
----------------------------------------------------------------------------
-- Executes following steps:
-- 1. Generates random CAN frame.
-- 2. Inserts the frame to RX Buffer as CAN Core. Randomized abort of
-- 2. Inserts the frame to RX Buffer as CAN Core. Randomized abort of
-- storing is generated (as if error frame was generated)!
-- 3. Checks for data overrun flag during storing. If overrun appeared, or
-- error frame was generated, data are not stored in test memory.
......@@ -301,14 +301,14 @@ architecture rx_buf_unit_test of CAN_test is
variable abort_present : boolean := false;
variable id_out : std_logic_vector(28 downto 0);
begin
CAN_generate_frame(rand_ctr, CAN_frame);
stored_ts := (OTHERS => '0');
------------------------------------------------------------------------
-- Initiate frame storing by clearing possible overrun from before.
-- It might have happened that Overrun was generated at the same time
-- as there was intent abort. In that case, the frame was aborted,
-- as there was intent abort. In that case, the frame was aborted,
-- overrun was not cleared and stayed till next frame. Storing of
-- next frame then evaluated overrun as present and did not store the
-- frame to input memory!
......@@ -323,7 +323,7 @@ architecture rx_buf_unit_test of CAN_test is
log("Overrun not cleared!", error_l, log_level);
end if;
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Initiate Frame by SOF pulse and store timestamp!
------------------------------------------------------------------------
sof_pulse <= '1';
......@@ -388,7 +388,7 @@ architecture rx_buf_unit_test of CAN_test is
CAN_frame.data((i * 4) + 1) &
CAN_frame.data((i * 4));
store_data <= '1';
store_data <= '1';
log("Storing data word", info_l, log_level);
wait until rising_edge(clk_sys);
store_data <= '0';
......@@ -447,7 +447,7 @@ architecture rx_buf_unit_test of CAN_test is
----------------------------------------------------------------------------
-- Read frame from the RX buffer and store it into the common model
-- Read frame from the RX buffer and store it into the common model
-- and output memory!
----------------------------------------------------------------------------
procedure read_frame(
......@@ -469,7 +469,7 @@ architecture rx_buf_unit_test of CAN_test is
for i in 0 to rwcnt loop
drv_read_start <= '1';
out_mem(out_pointer) <= buff_out;
-- Check that word is exactly matching the word in in_mem at the
-- same position
if (buff_out /= in_mem(out_pointer)) then
......@@ -503,11 +503,11 @@ architecture rx_buf_unit_test of CAN_test is
end if;
end loop;
end procedure;
for rx_Buffer_comp : rxBuffer use entity work.rxBuffer(rtl);
begin
----------------------------------------------------------------------------
-- Buffer component
----------------------------------------------------------------------------
......@@ -542,8 +542,8 @@ begin
rx_write_pointer_pos => rx_write_pointer_pos,
rx_data_overrun => rx_data_overrun,
rx_read_buff => rx_read_buff
);
);
----------------------------------------------------------------------------
-- Clock and timestamp generation
......@@ -558,13 +558,13 @@ begin
end process;
-- Overall amount of errors is sum of errors from all processes
error_ctr <= stim_errs + read_errs + status_errs + cons_errs;
error_ctr <= stim_errs + read_errs + status_errs + cons_errs;
-- Common input memory is not filled totally so that one iteration
-- of test won't take too long!
in_mem_full <= true when in_pointer + buff_size + 1 > 300 else
false;
out_mem_full <= true when out_pointer + buff_size + 1 > 300 else
false;
......@@ -662,7 +662,7 @@ begin
------------------------------------------------------------------------
while (out_mem_full = false) loop
if (rx_empty = '0') then
read_frame(rx_read_buff, drv_read_start, clk_sys, out_mem,
read_frame(rx_read_buff, drv_read_start, clk_sys, out_mem,
in_mem, out_pointer);
wait_rand_cycles(rand_ctr_3, clk_sys, 200, 250);
end if;
......@@ -683,7 +683,7 @@ begin
wait for 10 ns;
end process;
----------------------------------------------------------------------------
-- Data consistency checker
----------------------------------------------------------------------------
......@@ -706,7 +706,7 @@ begin
if (cons_res = false) then
process_error(cons_errs, error_beh, exit_imm_d_3);
log("Data consistency check failed !", error_l, log_level);
log("Data consistency check failed !", error_l, log_level);
end if;
-- Now we can tell to the other circuits that one iteration is over
......@@ -715,15 +715,15 @@ begin
end process;
errors <= error_ctr;
end architecture;
--------------------------------------------------------------------------------
-- Test wrapper and control signals generator
-- Test wrapper and control signals generator
--------------------------------------------------------------------------------
architecture rx_buf_unit_test_wrapper of CAN_test_wrapper is
-- Select architecture of the test
for test_comp : CAN_test use entity work.CAN_test(rx_buf_unit_test);
......@@ -732,22 +732,22 @@ architecture rx_buf_unit_test_wrapper of CAN_test_wrapper is
signal errors : natural;
begin
-- In this test wrapper generics are directly connected to the signals of
-- test entity
test_comp : CAN_test
port map(
run => run,
iterations => iterations,
iterations => iterations,
log_level => log_level,
error_beh => error_beh,
error_tol => error_tol,
error_tol => error_tol,
status => status_int,
errors => errors