Commit ebaab185 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

src: Enable time quanta counter only as controlled by PC FSM.

parent 33e5cf0e
Pipeline #17634 passed with stages
in 19 minutes and 9 seconds
......@@ -174,7 +174,7 @@ begin
if (res_n = G_RESET_POLARITY) then
tq_counter_q <= (OTHERS => '0');
elsif (rising_edge(clk_sys)) then
if (tq_counter_allow = '1') then
if (tq_counter_ce = '1') then
tq_counter_q <= tq_counter_d;
end if;
end if;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment