Commit eb2495a9 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch '180-fixup-broken-vhdl-2008-synthesis' into 'master'

Resolve "Fixup broken VHDL 2008 synthesis"

Closes #180

See merge request illeondr/CAN_FD_IP_Core!141
parents 3c12ddde 74c91851
......@@ -70,6 +70,7 @@ USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE WORK.CANconstants.ALL;
use work.CAN_FD_register_map.all;
use work.reduce_lib.all;
entity intManager is
generic(
......@@ -215,7 +216,7 @@ begin
int_input_active(RFI_IND) <= rx_full;
int_input_active(BSI_IND) <= br_shifted;
int_input_active(RBNEI_IND) <= not rx_empty;
int_input_active(TXBHCI_IND) <= or(txt_hw_cmd_int);
int_input_active(TXBHCI_IND) <= or_reduce(txt_hw_cmd_int);
int_proc : process(res_n, clk_sys)
begin
......
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com>
--
-- Project advisors and co-authors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
-- Martin Jerabek <jerabma7@fel.cvut.cz>
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Library with "reduce" functions to support generic OR between elements
-- of std_logic_vector. Unary logic operators are not well supported by
-- synthesis tools, thus this workaround is used!
--
--------------------------------------------------------------------------------
-- Revision History:
-- 31.8.2018 Created file
--------------------------------------------------------------------------------
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
package reduce_lib is
----------------------------------------------------------------------------
-- Performs OR operation between all elements of vector
--
-- Arguments:
-- period Period of generated clock in picoseconds.
-- Returns: OR of all elements of vector
----------------------------------------------------------------------------
function or_reduce(
constant input : in std_logic_vector
) return std_logic;
----------------------------------------------------------------------------
-- Performs AND operation between all elements of vector
--
-- Arguments:
-- period Period of generated clock in picoseconds.
-- Returns: AND of all elements of vector
----------------------------------------------------------------------------
function and_reduce(
constant input : in std_logic_vector
) return std_logic;
end package;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Library implementation
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
package body reduce_lib is
function or_reduce(
constant input : in std_logic_vector
) return std_logic is
variable tmp : std_logic := '0';
begin
for i in input'range loop
tmp := tmp or input(i);
end loop;
return tmp;
end function;
function and_reduce(
constant input : in std_logic_vector
) return std_logic is
variable tmp : std_logic := '1';
begin
for i in input'range loop
tmp := tmp and input(i);
end loop;
return tmp;
end function;
end package body;
......@@ -58,6 +58,7 @@ use work.CANconstants.all;
use work.CANcomponents.ALL;
USE work.CANtestLib.All;
USE work.randomLib.All;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
use work.ID_transfer.all;
......@@ -366,7 +367,7 @@ begin
int_input(RFI_IND) <= rx_full;
int_input(BSI_IND) <= br_shifted;
int_input(RBNEI_IND) <= not rx_empty;
int_input(TXBHCI_IND) <= or(txt_hw_cmd_int);
int_input(TXBHCI_IND) <= or_reduce(txt_hw_cmd_int);
----------------------------------------------------------------------------
......
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