Commit ea331edc authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Created generic instance of Bit Filter

and Range filter. Replaced hard-coded
implementation with generic filter
blocks.
Signed-off-by: Ille, Ondrej, Ing.'s avatarIlle, Ondrej, Ing <illeondr@fel.cvut.cz>
parent 7830a758
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018
--
-- Authors:
-- Ondrej Ille <ondrej.ille@gmail.com>
-- Martin Jerabek <martin.jerabek01@gmail.com>
--
-- Project advisors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
--
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Bit Filter for CAN identifiers. Output is valid if masked filter input
-- equals masked value to be compared. Output is combinational.
--------------------------------------------------------------------------------
-- Revision History:
-- 14.11.2018 Created file
--------------------------------------------------------------------------------
Library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;
use work.CANconstants.all;
use work.ID_transfer.all;
entity bitFilter is
generic(
-- Filter width
constant width : natural;
-- Filter presence
constant is_present : boolean
);
port(
-- Filter mask
signal filter_mask : in std_logic_vector(width - 1 downto 0);
-- Filter value
signal filter_value : in std_logic_vector(width - 1 downto 0);
-- Filter input
signal filter_input : in std_logic_vector(width - 1 downto 0);
-- Filter enable (output is stuck at zero when disabled)
signal enable : in std_logic;
-- Filter output
signal valid : out std_logic
);
end entity;
architecture rtl of bitFilter is
signal masked_input : std_logic_vector(width - 1 downto 0);
signal masked_value : std_logic_vector(width - 1 downto 0);
begin
masked_input <= filter_input and filter_mask;
masked_value <= filter_value and filter_mask;
-- Filter A input frame type filtering
gen_filt_pos : if (is_present = true) generate
valid <= '1' when (masked_input = masked_value)
AND
(enable = '1')
else
'0';
end generate;
gen_filt_neg : if (is_present = false) generate
valid <= '0';
end generate;
end architecture;
......@@ -65,6 +65,8 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;
use work.CANconstants.all;
use work.ID_transfer.all;
use work.CANcomponents.ALL;
use work.CAN_FD_frame_format.all;
entity messageFilter is
generic(
......@@ -172,13 +174,19 @@ entity messageFilter is
-- Concat of types of data on input
signal int_data_ctrl : std_logic_vector(1 downto 0);
-- Actual decimal value of recieved
signal rec_ident_dec : natural;
-- Decimal values of identifiers
signal id_1_dec : natural;
signal id_2_dec : natural;
-- Enable signal for filters
signal filter_A_enable : std_logic;
signal filter_B_enable : std_logic;
signal filter_C_enable : std_logic;
signal filter_range_enable : std_logic;
-- At least one filter output is valid
signal min_one_filt_valid : std_logic;
----------------------------------------------------------------------------
-- REGISTERS
----------------------------------------------------------------------------
......@@ -190,7 +198,10 @@ end entity;
architecture rtl of messageFilter is
begin
---------------------------------------------------------------------------
-- Driving signal aliases
---------------------------------------------------------------------------
drv_filter_A_mask <= drv_bus(DRV_FILTER_A_MASK_HIGH downto
DRV_FILTER_A_MASK_LOW);
drv_filter_A_ctrl <= drv_bus(DRV_FILTER_A_CTRL_HIGH downto
......@@ -217,6 +228,11 @@ begin
DRV_FILTER_RAN_HI_TH_LOW);
drv_filters_ena <= drv_bus(DRV_FILTERS_ENA_INDEX);
---------------------------------------------------------------------------
-- Decoding Filter enables based on accepted frame types by each filter
---------------------------------------------------------------------------
-- Input frame type internal signal
int_data_ctrl <= frame_type & ident_type;
......@@ -227,117 +243,107 @@ begin
"0100" when "10", --CAN FD Basic
"1000" when "11", --CAN Fd Extended
"0000" when others;
-- Filter is enabled when at least one Frame type/Identifier type is matching
-- the configured value
filter_A_enable <= '1' when ((drv_filter_A_ctrl and int_data_type) /= x"0")
else
'0';
filter_B_enable <= '1' when ((drv_filter_B_ctrl and int_data_type) /= x"0")
else
'0';
filter_C_enable <= '1' when ((drv_filter_C_ctrl and int_data_type) /= x"0")
else
'0';
filter_range_enable <= '1' when ((drv_filter_ran_ctrl and int_data_type) /= x"0")
else
'0';
---------------------------------------------------------------------------
-- Filter instances
---------------------------------------------------------------------------
filt_A_comp : bitFilter
generic map(
width => 29,
is_present => sup_filtA
)
port map(
filter_mask => drv_filter_A_mask,
filter_value => drv_filter_A_bits,
filter_input => rec_ident_in,
enable => filter_A_enable,
valid => int_filter_A_valid
);
filt_B_comp : bitFilter
generic map(
width => 29,
is_present => sup_filtB
)
port map(
filter_mask => drv_filter_B_mask,
filter_value => drv_filter_B_bits,
filter_input => rec_ident_in,
enable => filter_B_enable,
valid => int_filter_B_valid
);
filt_C_comp : bitFilter
generic map(
width => 29,
is_present => sup_filtC
)
port map(
filter_mask => drv_filter_C_mask,
filter_value => drv_filter_C_bits,
filter_input => rec_ident_in,
enable => filter_C_enable,
valid => int_filter_C_valid
);
-- Filter A input frame type filtering
gen_filtA_pos : if (sup_filtA = true) generate
int_filter_A_valid <= '1' when (( --Identifier matches the bits and mask
(rec_ident_in AND drv_filter_A_mask)
=
(drv_filter_A_bits AND drv_filter_A_mask)
)
AND
( --Frame type Matches defined frame type
not((drv_filter_A_ctrl AND int_data_type)
= "0000")
)
)
else '0';
end generate;
gen_filtA_neg : if (sup_filtA = false) generate
int_filter_A_valid <= '0';
end generate;
-- Filter B input frame type filtering
gen_filtB_pos : if (sup_filtB = true) generate
int_filter_B_valid <= '1' when (( --Identifier matches the bits and mask
(rec_ident_in AND drv_filter_B_mask)
=
(drv_filter_B_bits AND drv_filter_B_mask)
)
AND
( --Frame type Matches defined frame type
not((drv_filter_B_ctrl AND int_data_type)
= "0000")
)
)
else '0';
end generate;
gen_filtB_neg : if (sup_filtB = false) generate
int_filter_B_valid <= '0';
end generate;
--Filter C input frame type filtering
gen_filtC_pos : if (sup_filtC = true) generate
int_filter_C_valid <= '1' when (( --Identifier matches the bits and mask
(rec_ident_in AND drv_filter_C_mask)
=
(drv_filter_C_bits AND drv_filter_C_mask)
)
AND
( --Frame type Matches defined frame type
not((drv_filter_C_ctrl AND int_data_type)
= "0000")
)
)
else '0';
end generate;
gen_filtC_neg : if (sup_filtC = false) generate
int_filter_C_valid <= '0';
end generate;
--Range filter for identifiers
gen_filtRan_pos : if (sup_range = true) generate
ID_reg_to_decimal(rec_ident_in, rec_ident_dec);
int_filter_ran_valid <= '1' when (--Identifier matches the range set
(rec_ident_dec
<=
to_integer(unsigned(drv_filter_ran_hi_th)))
AND
(rec_ident_dec
>=
to_integer(unsigned(drv_filter_ran_lo_th)))
)
AND
( --Frame type Matches defined frame type
not((drv_filter_ran_ctrl AND int_data_type)
= "0000")
)
else '0';
end generate;
gen_filtRan_neg : if (sup_range = false) generate
int_filter_ran_valid <= '0';
end generate;
filt_range_comp : rangeFilter
generic map(
width => 29,
is_present => sup_range
)
port map(
filter_upp_th => drv_filter_ran_hi_th,
filter_low_th => drv_filter_ran_lo_th,
filter_input => rec_ident_in,
enable => filter_range_enable,
valid => int_filter_ran_valid
);
---------------------------------------------------------------------------
-- If no filter is supported then output should be determined just by
-- input, regardless of 'drv_filters_ena'! If Core is not synthesized,
-- turning filters on should not affect the acceptance! Everyhting should
-- be affected!
---------------------------------------------------------------------------
filt_sup_gen_false : if (sup_filtA = false and sup_filtB = false and
sup_filtC = false and sup_range = false) generate
valid_reg <= rec_ident_valid;
end generate;
filt_sup_gen_true : if (sup_filtA = true or sup_filtB = true or
sup_filtC = true or sup_range = true) generate
min_one_filt_valid <= int_filter_A_valid OR
int_filter_B_valid OR
int_filter_C_valid OR
int_filter_ran_valid;
-- If received message is valid and at least one of the filters is
-- matching the message passed the filter.
valid_reg <= rec_ident_valid AND
(
int_filter_A_valid OR
int_filter_B_valid OR
int_filter_C_valid OR
int_filter_ran_valid
) when drv_filters_ena = '1'
valid_reg <= (rec_ident_valid AND min_one_filt_valid)
when (drv_filters_ena = '1')
else rec_ident_valid;
end generate;
----------------------------------------------------------------------------
-- To avoid long combinational paths, valid filter output is pipelined.
-- This is OK since received frame is valid on input for many clock cycles!
......@@ -350,5 +356,6 @@ begin
out_ident_valid <= valid_reg;
end if;
end process valid_reg_proc;
end architecture;
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018
--
-- Authors:
-- Ondrej Ille <ondrej.ille@gmail.com>
-- Martin Jerabek <martin.jerabek01@gmail.com>
--
-- Project advisors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
--
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Range Filter for CAN identifiers. Interprets input value as decimal value
-- and compares if it is in range given by upper and lower threshold.
--------------------------------------------------------------------------------
-- Revision History:
-- 14.11.2018 Created file
--------------------------------------------------------------------------------
Library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;
use work.CANconstants.all;
use work.ID_transfer.all;
entity rangeFilter is
generic(
-- Filter width
constant width : natural;
-- Filter presence
constant is_present : boolean
);
port(
-- Upper threshold of a filter
signal filter_upp_th : in std_logic_vector(width - 1 downto 0);
-- Lower threshold of a filter
signal filter_low_th : in std_logic_vector(width - 1 downto 0);
-- Filter input
signal filter_input : in std_logic_vector(width - 1 downto 0);
-- Filter enable (output is stuck at zero when disabled)
signal enable : in std_logic;
-- Filter output
signal valid : out std_logic
);
end entity;
architecture rtl of rangeFilter is
-- Upper and lower threshold converted to unsigned values
signal upper_th_dec : natural range 0 to (2 ** width - 1);
signal lower_th_dec : natural range 0 to (2 ** width - 1);
-- Filter input converted to unsigned value
signal value_dec : natural range 0 to (2 ** width - 1);
begin
-- Conversion procedures
ID_reg_to_decimal(filter_input, value_dec);
ID_reg_to_decimal(filter_upp_th, upper_th_dec);
ID_reg_to_decimal(filter_low_th, lower_th_dec);
-- Filter implementation
gen_filt_pos : if (is_present = true) generate
valid <= '1' when ((value_dec <= upper_th_dec) and
(value_dec >= lower_th_dec) and
(enable = '1'))
else
'0';
end generate;
gen_filtRan_neg : if (is_present = false) generate
valid <= '0';
end generate;
end architecture;
......@@ -396,6 +396,42 @@ package CANcomponents is
end component;
----------------------------------------------------------------------------
-- Generic Bit Filter
----------------------------------------------------------------------------
component bitFilter is
generic(
constant width : natural;
constant is_present : boolean
);
port(
signal filter_mask : in std_logic_vector(width - 1 downto 0);
signal filter_value : in std_logic_vector(width - 1 downto 0);
signal filter_input : in std_logic_vector(width - 1 downto 0);
signal enable : in std_logic;
signal valid : out std_logic
);
end component;
----------------------------------------------------------------------------
-- Range filter
----------------------------------------------------------------------------
component rangeFilter is
generic(
constant width : natural;
constant is_present : boolean
);
port(
signal filter_upp_th : in std_logic_vector(width - 1 downto 0);
signal filter_low_th : in std_logic_vector(width - 1 downto 0);
signal filter_input : in std_logic_vector(width - 1 downto 0);
signal enable : in std_logic;
signal valid : out std_logic
);
end component;
----------------------------------------------------------------------------
-- Interrupt manager module
----------------------------------------------------------------------------
......
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