Commit ea21569e authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

src, test: Fixes vol. 3

parent 6397538e
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********************************************************************************
** Generating Lyx docs for VHDL entity interfaces!
********************************************************************************
Python version is: python3.6
********************************************************************************
Processing prescaler entity
********************************************************************************
../doc/template.lyx
This diff is collapsed.
......@@ -376,7 +376,7 @@ begin
-- psl rx_buf_cmds_one_hot_asrt : assert always
-- (cmd_join = "0000" or cmd_join = "0001" or cmd_join = "0010"
-- and cmd_join = "0100" or cmd_join = "1000")
-- or cmd_join = "0100" or cmd_join = "1000")
-- report "RX Buffer: RX Buffer commands should be one-hot encoded!"
-- severity error;
......
......@@ -393,9 +393,9 @@ begin
-- cover (rx_mem_free_int = G_RX_BUFF_SIZE);
--
-- psl rx_write_ptr_higher_than_read_ptr_cov :
-- cover (write_pointer_int > read_pointer_int);
-- cover (write_pointer_i > read_pointer_i);
--
-- psl rx_read_ptr_higher_than_write_ptr_cov :
-- cover (read_pointer_int > write_pointer_int);
-- cover (read_pointer_i > write_pointer_i);
end architecture;
\ No newline at end of file
......@@ -362,10 +362,16 @@ begin
end process;
------------------------------------------------------------------------------
-- Functional coverage
-- Assertions
------------------------------------------------------------------------------
-- psl default clock is rising_edge(clk_sys);
--
------------------------------------------------------------------------------
-- Functional coverage
------------------------------------------------------------------------------
--
-- psl txt_buf_wait_till_timestamp_cov : cover
-- (curr_state = s_arb_sel_upp_ts and fsm_wait_state_q = '0' and
-- timestamp_valid = '0')
......
......@@ -291,4 +291,4 @@ begin
end block;
end architecture;
end architecture;
\ No newline at end of file
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="Benchmark:Minimal_configuration" LaunchDir="/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.runs/Benchmark:Minimal_configuration" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="Benchmark:Minimal_configuration" LaunchDir="/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.runs/Benchmark:Minimal_configuration" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="Benchmark:Minimal_configuration" LaunchDir="/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.runs/Benchmark:Minimal_configuration" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="Benchmark:Minimal_configuration" LaunchDir="/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.runs/Benchmark:Minimal_configuration" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="Benchmark:Minimal_configuration" LaunchDir="/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.runs/Benchmark:Minimal_configuration" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="Benchmark:Minimal_configuration" LaunchDir="/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.runs/Benchmark:Minimal_configuration" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="Benchmark:Minimal_configuration" LaunchDir="/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.runs/Benchmark:Minimal_configuration" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="Benchmark:Minimal_configuration" LaunchDir="/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.runs/Benchmark:Minimal_configuration" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="Benchmark:Minimal_configuration" LaunchDir="/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.runs/Benchmark:Minimal_configuration" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="Benchmark:Minimal_configuration" LaunchDir="/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.runs/Benchmark:Minimal_configuration" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="Benchmark:Minimal_configuration" LaunchDir="/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.runs/Benchmark:Minimal_configuration" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>
set_property SRC_FILE_INFO {cfile:/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/synthesis/Constraints/CTU_CAN_FD_Xilinx.sdc rfile:../../../../../Constraints/CTU_CAN_FD_Xilinx.sdc id:1} [current_design]
set_property src_info {type:XDC file:1 line:48 export:INPUT save:INPUT read:READ} [current_design]
set_property ASYNC_REG true $rs_sync_chain_1
set_property src_info {type:XDC file:1 line:49 export:INPUT save:INPUT read:READ} [current_design]
set_property ASYNC_REG true $rs_sync_chain_2
set_property src_info {type:XDC file:1 line:56 export:INPUT save:INPUT read:READ} [current_design]
set_property ASYNC_REG true [get_cells *bus_sync_comp/sync_Chain_1*]
set_property src_info {type:XDC file:1 line:57 export:INPUT save:INPUT read:READ} [current_design]
set_property ASYNC_REG true [get_cells *bus_sync_comp/sync_Chain_2*]
#
# Synthesis run script generated by Vivado
#
proc create_report { reportName command } {
set status "."
append status $reportName ".fail"
if { [file exists $status] } {
eval file delete [glob $status]
}
send_msg_id runtcl-4 info "Executing : $command"
set retval [eval catch { $command } msg]
if { $retval != 0 } {
set fp [open $status w]
close $fp
send_msg_id runtcl-5 warning "$msg"
}
}
create_project -in_memory -part xc7z007sclg225-2
set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_property webtalk.parent_dir /DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.cache/wt [current_project]
set_property parent.project_path /DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.xpr [current_project]
set_property default_lib lib [current_project]
set_property target_language VHDL [current_project]
set_property ip_output_repo /DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
set_property generic {dummy=Minimal_configuration use_logger=false rx_buffer_size=32 use_sync=true ID=1 sup_filtA=false sup_filtB=false sup_filtC=false sup_range=false logger_size=8} [current_fileset]
read_vhdl -vhdl2008 -library lib {
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/lib/can_fd_frame_format.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/lib/id_transfer.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/lib/can_constants.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/lib/can_types.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/memory_registers/generated/can_registers_pkg.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/lib/can_components.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/lib/cmn_lib.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/lib/drv_stat_pkg.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/common/endian_swap.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/lib/reduce_lib.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/lib/can_fd_register_map.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/memory_registers/generated/access_signaler.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/memory_registers/generated/address_decoder.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/can_core/bit_destuffing/bit_destuffing.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/frame_filters/bit_filter.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/can_core/bit_stuffing/bit_stuffing.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/bus_sampling/bus_sampling.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/can_core/bus_traffic_counters/bus_traffic_counters.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/can_core/operation_control/operation_control.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/can_core/protocol_control/protocol_control.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/can_core/fault_confinement/fault_confinement.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/can_core/crc/crc_wrapper.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/can_core/can_core.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/can_core/crc/can_crc.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/memory_registers/memory_registers.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/rx_buffer/rx_buffer.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/tx_arbitrator/tx_arbitrator.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/frame_filters/frame_filters.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/interrupts/int_manager.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/prescaler/prescaler.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/common/rst_sync.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/memory_registers/generated/cmn_reg_map_pkg.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/memory_registers/generated/control_registers_reg_map.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/can_core/crc/crc_calc.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/memory_registers/generated/data_mux.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/common/dff_arst.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/event_logger/event_logger.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/memory_registers/generated/event_logger_reg_map.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/common/inf_ram_wrapper.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/interrupts/int_module.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/common/majority_decoder_3.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/memory_registers/generated/memory_reg.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/tx_arbitrator/priority_decoder.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/frame_filters/range_filter.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/rx_buffer/rx_buffer_fsm.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/rx_buffer/rx_buffer_pointers.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/common/shift_reg.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/common/shift_reg_preload.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/common/sig_sync.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/tx_arbitrator/tx_arbitrator_fsm.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/txt_buffer/txt_buffer.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/txt_buffer/txt_buffer_fsm.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/can_top_level.vhd
}
read_vhdl -library lib {
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/prescaler/bit_time_cfg_capture.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/prescaler/bit_time_counters.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/prescaler/bit_time_fsm.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/prescaler/ipt_checker.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/prescaler/resynchronisation.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/prescaler/segment_end_detector.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/prescaler/synchronisation_checker.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/prescaler/trigger_generator.vhd
}
# Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the
# design are intentionally left as such for best results. Dcp files will be
# stitched into the design at a later time, either when this synthesis run is
# opened, or when it is stitched into a dependent implementation run.
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
set_property used_in_implementation false $dcp
}
read_xdc /DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/synthesis/Constraints/CTU_CAN_FD_Xilinx.sdc
set_property used_in_implementation false [get_files /DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/synthesis/Constraints/CTU_CAN_FD_Xilinx.sdc]
synth_design -top can_top_level -part xc7z007sclg225-2 -flatten_hierarchy none -retiming -fsm_extraction one_hot
# disable binary constraint mode for synth run checkpoints
set_param constraints.enableBinaryConstraints false
write_checkpoint -force -noxdef can_top_level.dcp
create_report "Benchmark:Minimal_configuration_synth_report_utilization_0" "report_utilization -file can_top_level_utilization_synth.rpt -pb CAN_top_level_utilization_synth.pb"
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
| Date : Wed Mar 6 14:28:29 2019
| Host : ondrej-Aspire-V3-771 running 64-bit Ubuntu 18.04.1 LTS
| Command : report_utilization -file can_top_level_utilization_synth.rpt -pb CAN_top_level_utilization_synth.pb
| Design : can_top_level
| Device : 7z007sclg225-2
| Design State : Synthesized
---------------------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Memory
3. DSP
4. IO and GT Specific
5. Clocking
6. Specific Feature
7. Primitives
8. Black Boxes
9. Instantiated Netlists
1. Slice Logic
--------------
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs* | 2147 | 0 | 14400 | 14.91 |
| LUT as Logic | 2147 | 0 | 14400 | 14.91 |
| LUT as Memory | 0 | 0 | 6000 | 0.00 |
| Slice Registers | 1353 | 0 | 28800 | 4.70 |
| Register as Flip Flop | 1353 | 0 | 28800 | 4.70 |
| Register as Latch | 0 | 0 | 28800 | 0.00 |
| F7 Muxes | 31 | 0 | 8800 | 0.35 |
| F8 Muxes | 8 | 0 | 4400 | 0.18 |
+-------------------------+------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 76 | Yes | - | Set |
| 1265 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 12 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Memory
---------
+-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 2.5 | 0 | 50 | 5.00 |
| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 |
| RAMB18 | 5 | 0 | 100 | 5.00 |
| RAMB18E1 only | 5 | | | |
+-------------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
3. DSP
------
+-----------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
| DSPs | 0 | 0 | 66 | 0.00 |
+-----------+------+-------+-----------+-------+
4. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+--------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+--------+
| Bonded IOB | 159 | 0 | 54 | 294.44 |
| Bonded IPADs | 0 | 0 | 2 | 0.00 |
| Bonded IOPADs | 0 | 0 | 130 | 0.00 |
| PHY_CONTROL | 0 | 0 | 2 | 0.00 |
| PHASER_REF | 0 | 0 | 2 | 0.00 |
| OUT_FIFO | 0 | 0 | 8 | 0.00 |
| IN_FIFO | 0 | 0 | 8 | 0.00 |
| IDELAYCTRL | 0 | 0 | 2 | 0.00 |
| IBUFDS | 0 | 0 | 54 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 8 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 8 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 100 | 0.00 |
| ILOGIC | 0 | 0 | 54 | 0.00 |
| OLOGIC | 0 | 0 | 54 | 0.00 |
+-----------------------------+------+-------+-----------+--------+
5. Clocking
-----------
+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 1 | 0 | 32 | 3.13 |
| BUFIO | 0 | 0 | 8 | 0.00 |
| MMCME2_ADV | 0 | 0 | 2 | 0.00 |
| PLLE2_ADV | 0 | 0 | 2 | 0.00 |
| BUFMRCE | 0 | 0 | 4 | 0.00 |
| BUFHCE | 0 | 0 | 48 | 0.00 |
| BUFR | 0 | 0 | 8 | 0.00 |
+------------+------+-------+-----------+-------+
6. Specific Feature
-------------------
+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+
7. Primitives
-------------
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDCE | 1265 | Flop & Latch |
| LUT6 | 910 | LUT |
| LUT4 | 561 | LUT |
| LUT3 | 401 | LUT |
| LUT2 | 390 | LUT |
| LUT5 | 342 | LUT |
| IBUF | 124 | IO |
| LUT1 | 104 | LUT |
| FDPE | 76 | Flop & Latch |
| CARRY4 | 67 | CarryLogic |
| OBUF | 35 | IO |
| MUXF7 | 31 | MuxFx |
| FDRE | 12 | Flop & Latch |
| MUXF8 | 8 | MuxFx |
| RAMB18E1 | 5 | Block Memory |
| BUFG | 1 | Clock |
+----------+------+---------------------+
8. Black Boxes
--------------
+-----------------------+------+
| Ref Name | Used |
+-----------------------+------+
| tx_data_cache | 1 |
| trv_delay_measurement | 1 |
| sample_mux | 1 |
| endian_swapper | 1 |
| data_edge_detector | 1 |
| bit_errror_detector | 1 |
+-----------------------+------+
9. Instantiated Netlists
------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
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*-27.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
@200
-Test details
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[*]
[*] GTKWave Analyzer v3.3.98 (w)1999-2019 BSI
[*] Sun Mar 17 14:53:57 2019
[*]
[dumpfile] "/build/test/build/vunit_out/test_output/lib.tb_sanity.1Mb_10Mb_20_m_Star_19cff8652e0a3d517c03100ae1b1ae07ab78df87/ghdl/wave.ghw"
[dumpfile_mtime] "Sun Mar 17 14:12:50 2019"
[dumpfile_size] 123971756
[savefile] "/build/test/sanity_waves.gtkw"
[timestart] 198432000000
[size] 1726 859
[pos] -1 -1
*-29.471088 200200000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] top.
[treeopen] top.tb_sanity.
[treeopen] top.tb_sanity.t_sanity.
[treeopen] top.tb_sanity.t_sanity.comp_gen[1].
[treeopen] top.tb_sanity.t_sanity.comp_gen[1].node_1_comp.
[treeopen] top.tb_sanity.t_sanity.comp_gen[1].node_1_comp.can_core_comp.
[treeopen] top.tb_sanity.t_sanity.comp_gen[2].node_1_comp.
[treeopen] top.tb_sanity.t_sanity.comp_gen[2].node_1_comp.can_core_comp.
[treeopen] top.tb_sanity.t_sanity.comp_gen[2].node_1_comp.can_core_comp.protocol_control_comp.
[treeopen] top.tb_sanity.t_sanity.comp_gen[3].node_1_comp.
[treeopen] top.tb_sanity.t_sanity.comp_gen[3].node_1_comp.can_core_comp.
[treeopen] top.tb_sanity.t_sanity.comp_gen[4].node_1_comp.
[sst_width] 446
[signals_width] 282
[sst_expanded] 1
[sst_vpaned_height] 354
@28
top.tb_sanity.t_sanity.comp_gen[2].node_1_comp.can_core_comp.protocol_control_comp.clk_sys
@420
top.tb_sanity.t_sanity.comp_gen[1].node_1_comp.can_core_comp.pc_state
top.tb_sanity.t_sanity.comp_gen[4].node_1_comp.can_core_comp.pc_state
top.tb_sanity.t_sanity.comp_gen[2].node_1_comp.can_core_comp.pc_state
top.tb_sanity.t_sanity.comp_gen[3].node_1_comp.can_core_comp.pc_state
@28
top.tb_sanity.t_sanity.comp_gen[1].node_1_comp.can_tx
top.tb_sanity.t_sanity.comp_gen[2].node_1_comp.can_tx
top.tb_sanity.t_sanity.comp_gen[3].node_1_comp.can_tx
top.tb_sanity.t_sanity.comp_gen[4].node_1_comp.can_tx
top.tb_sanity.t_sanity.comp_gen[1].node_1_comp.can_core_comp.data_tx
top.tb_sanity.t_sanity.comp_gen[1].node_1_comp.prescaler_comp.no_pos_resync
top.tb_sanity.t_sanity.comp_gen[1].node_1_comp.prescaler_comp.sync_edge
top.tb_sanity.t_sanity.comp_gen[1].node_1_comp.prescaler_comp.tq_edge_nbt
@420
top.tb_sanity.t_sanity.comp_gen[1].node_1_comp.prescaler_comp.bt_fsm_out
@28
top.tb_sanity.t_sanity.comp_gen[1].node_1_comp.can_core_comp.data_rx
@420
top.tb_sanity.t_sanity.comp_gen[1].node_1_comp.can_core_comp.protocol_control_comp.control_pointer
@28
top.tb_sanity.t_sanity.comp_gen[1].node_1_comp.can_core_comp.protocol_control_comp.sec_ack
@29
top.tb_sanity.t_sanity.comp_gen[1].node_1_comp.can_core_comp.protocol_control_comp.rec_trig
@28
top.tb_sanity.t_sanity.comp_gen[1].node_1_comp.can_core_comp.protocol_control_comp.tran_trig
@420
top.tb_sanity.t_sanity.comp_gen[1].node_1_comp.can_core_comp.protocol_control_comp.op_state
@28
top.tb_sanity.t_sanity.comp_gen[1].node_1_comp.can_core_comp.protocol_control_comp.ack_recieved_out
#{top.tb_sanity.t_sanity.comp_gen[1].node_1_comp.can_core_comp.sp_control[1:0]} top.tb_sanity.t_sanity.comp_gen[1].node_1_comp.can_core_comp.sp_control[1] top.tb_sanity.t_sanity.comp_gen[1].node_1_comp.can_core_comp.sp_control[0]
@22
#{top.tb_sanity.t_sanity.comp_gen[1].node_1_comp.prescaler_comp.sjw_nbt[4:0]} top.tb_sanity.t_sanity.comp_gen[1].node_1_comp.prescaler_comp.sjw_nbt[4] top.tb_sanity.t_sanity.comp_gen[1].node_1_comp.prescaler_comp.sjw_nbt[3] top.tb_sanity.t_sanity.comp_gen[1].node_1_comp.prescaler_comp.sjw_nbt[2] top.tb_sanity.t_sanity.comp_gen[1].node_1_comp.prescaler_comp.sjw_nbt[1] top.tb_sanity.t_sanity.comp_gen[1].node_1_comp.prescaler_comp.sjw_nbt[0]
@28
#{top.tb_sanity.t_sanity.comp_gen[1].node_1_comp.prescaler_comp.sync_control[1:0]} top.tb_sanity.t_sanity.comp_gen[1].node_1_comp.prescaler_comp.sync_control[1] top.tb_sanity.t_sanity.comp_gen[1].node_1_comp.prescaler_comp.sync_control[0]
[pattern_trace] 1
[pattern_trace] 0
......@@ -221,7 +221,7 @@ def get_default_compile_and_sim_options() -> Tuple[OptionsDict, OptionsDict]:
sim_options = OptionsDict({
"ghdl.elab_flags": elab_flags,
"modelsim.init_files.after_load": common_modelsim_init_files,
"ghdl.sim_flags": ["--ieee-asserts=disable-at-0"],
"ghdl.sim_flags": ["--ieee-asserts=disable-at-0", "--disp-tree"],
})
return compile_options, sim_options
......
_default: &default
log_level: info
log_level: debug
psl_coverage: true
error_tolerance: 0
# seed: 0 # optional; use to reconstruct results from randomized runs
......@@ -9,7 +9,7 @@ _default: &default
unit:
default:
<<: *default
log_level: warning
log_level: info
iterations: 50
timeout: 100 ms
tests:
......@@ -30,11 +30,13 @@ unit:
wave: unit/Prescaler/prsc_unit.tcl
protocol_control:
wave: unit/Protocol_Control/pctl_unit.tcl
iterations: 100
rx_buf:
wave: unit/RX_Buffer/rxbf_unit.tcl
iterations: 10
tx_arb:
wave: unit/TX_Arbitrator/txar_unit.tcl
iterations: 1000
tx_buf:
wave: unit/TX_Buffer/txbf_unit.tcl
feature:
......
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