Commit e7a1a4c3 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Finished Data brief 2.1

parent f96f6c11
Pipeline #5319 passed with stages
in 6 minutes and 41 seconds
......@@ -117,88 +117,6 @@ thispagestyle{fancy}
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Czech Technical University in Prague
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Faculty of Electrical Engineering
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Department of Measurement
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......@@ -207,7 +125,7 @@ Martin Jerabek, Ondrej Ille
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September 2018
October 2018
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......
......@@ -135,83 +135,6 @@ thispagestyle{fancy}
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......@@ -232,7 +155,20 @@ CAN Flexible Data-Rate IP Core connects functionality of CAN 2.0, CAN FD
It is a soft-core IP Core written in VHDL, with no vendor specific libraries
needed.
The main target of usage are FPGA applications, and the core RTL is freely
available under MIT License in Gitlab repository of CTU FEE.
available under MIT License in
\color blue
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.
It is optimized for inference of native hardware blocks such as SRAM memories
and DSP blocks.
Generic settings achieve high level of flexibility before synthesis.
......@@ -249,8 +185,8 @@ The IP Core is accessed as a slave memory mapped peripheria via Avalon bus
of CAN frames can be triggered by external timestamp.
Three Bit filters and one Range filter is available for HW filtration of
received CAN frames.
The Core was synthesized in Xilinx and Altera FPGAs with approximate maximal
operating frequency of 100 MHz.
The Core was synthesized in low-end Xilinx and Altera FPGAs with maximal
operating frequencies above 100 MHz.
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