Commit e75f1f3b authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

test: Debug form error in Control field feature test.

Remove r0 on CAN 2.0 extended frame format! This should NOT be
treated as form error when Recessive is detected!

Swap test to check on receiver as on transmitter this is now
detected as bit error, not form error. Selectively enable/disable
FD support so that form error can be detected at correct spot!
parent e9337528
Pipeline #19590 passed with stages
in 19 minutes and 47 seconds
......@@ -47,18 +47,20 @@
--
-- @Verifies:
-- @1. Detection of form error in control field on r0 bit in CAN 2.0 base frame,
-- on r0 bit in CAN FD base frame, on r0/r1 bits in CAN 2.0 extended frame
-- and r0 in CAN FD extended frame!
-- on r0 bit in CAN FD base frame, on r1 bit in CAN 2.0 extended frame
-- and r0 in CAN FD extended frame when protocol exception handling is
-- disabled!
-- @2. Value of ERR_CAPT[ERR_POS] when form error shall be detected in control
-- field of CAN frame!
--
-- @Test sequence:
-- @1. Check that ERR_CAPT contains no error (post reset).
-- @2. Generate CAN frame (CAN 2.0 Base only, CAN FD Base only, CAN 2.0 Extended,
-- CAN FD extended), send it by Node 1. Wait until Arbitration field and wait
-- CAN FD extended), send it by Node 1. Wait until Arbitration field of the
-- othter node and wait and wait
-- for 13 (Base ID, RTR, IDE) or 14 (Base ID, RTR, IDE, EDL) or 32 bits
-- (Base ID, SRR, IDE, Ext ID, RTR) or 33 (Base ID, SRR, IDE, Ext ID, RTR,
-- r1) or 33 (Base ID, SRR, IDE, Ext ID, RTR, EDL) bits based on frame type.
-- (Base ID, SRR, IDE, Ext ID, RTR) or 33 (Base ID, SRR, IDE, Ext ID, RTR,
-- EDL) bits based on frame type.
-- Force bus Recessive (reserved bits are dominant) and wait until sample
-- point. Check that Node is transmitting error frame. Check that ERR_CAPT
-- signals Form Error in Control field. Reset the node, Wait until integration
......@@ -96,12 +98,17 @@ package body err_capt_ctrl_form_feature is
signal bus_level : in std_logic
) is
variable ID_1 : natural := 1;
variable ID_2 : natural := 2;
-- Generated frames
variable frame_1 : SW_CAN_frame_type;
-- Node status
variable stat_1 : SW_status;
variable stat_2 : SW_status;
-- Node mode
variable mode_2 : SW_mode;
variable wait_time : natural;
variable frame_sent : boolean;
......@@ -115,14 +122,19 @@ package body err_capt_ctrl_form_feature is
CAN_read_error_code_capture(err_capt, ID_1, mem_bus(1));
check(err_capt.err_pos = err_pos_other, "Reset of ERR_CAPT!");
-- Protocol exception should be disabled!!!
get_core_mode(mode_2, ID_2, mem_bus(2));
mode_2.pex_support := false;
set_core_mode(mode_2, ID_2, mem_bus(2));
-----------------------------------------------------------------------
-- @2. Generate CAN frame (CAN 2.0 Base only, CAN FD Base only, CAN 2.0
-- Extended, CAN FD extended), send it by Node 1. Wait until
-- Arbitration field and wait for 13 (Base ID, RTR, IDE) or 14 (Base
-- ID, RTR, IDE, EDL) or 34 bits (Base ID, SRR, IDE, Ext ID, RTR) or
-- 35 (Base ID, SRR, IDE, Ext ID, RTR, r1) or 35 (Base ID, SRR, IDE,
-- Ext ID, RTR, EDL) bits based on frame type. Force bus Recessive
-- Arbitration field of the other node and wait for 13 (Base ID, RTR,
-- IDE) or 14 (Base ID, RTR, IDE, EDL) or 34 bits (Base ID, SRR, IDE,
--- Ext ID, RTR) or 35 bits (Base ID, SRR, IDE, Ext ID, RTR, EDL)
-- bits based on frame type. Force bus Recessive
-- (reserved bits are dominant) and wait until sample point. Check
-- that Node is transmitting error frame. Check that ERR_CAPT signals
-- Form Error in Control field. Reset the node, Wait until integration
......@@ -130,10 +142,10 @@ package body err_capt_ctrl_form_feature is
--- check that next loops will truly set ERR_CAPT). Repeat with each
-- frame type!
-----------------------------------------------------------------------
for i in 1 to 5 loop
for i in 1 to 4 loop
info ("Inner Loop: " & integer'image(i));
CAN_generate_frame(rand_ctr, frame_1);
-- ID is not important in this TC. Avoid overflows of high generated
-- IDs on Base IDs!
frame_1.identifier := 10;
......@@ -147,54 +159,75 @@ package body err_capt_ctrl_form_feature is
frame_1.frame_format := NORMAL_CAN;
frame_1.ident_type := BASE;
wait_time := 13; -- Till r0
-- This is to get Form error on r0 RECESSIVE
get_core_mode(mode_2, ID_2, mem_bus(2));
mode_2.flexible_data_rate := false;
set_core_mode(mode_2, ID_2, mem_bus(2));
when 2 =>
frame_1.frame_format := FD_CAN;
frame_1.ident_type := BASE;
wait_time := 14; -- Till r0
-- This is to get Form error on r0 (after EDL) RECESSIVE
get_core_mode(mode_2, ID_2, mem_bus(2));
mode_2.flexible_data_rate := true;
set_core_mode(mode_2, ID_2, mem_bus(2));
when 3 =>
frame_1.frame_format := NORMAL_CAN;
frame_1.ident_type := EXTENDED;
wait_time := 32; -- Till r1
-- This is to get Form error on r1
get_core_mode(mode_2, ID_2, mem_bus(2));
mode_2.flexible_data_rate := false;
set_core_mode(mode_2, ID_2, mem_bus(2));
when 4 =>
frame_1.frame_format := NORMAL_CAN;
frame_1.ident_type := EXTENDED;
wait_time := 33; -- Till r0
when 5 =>
frame_1.frame_format := FD_CAN;
frame_1.ident_type := EXTENDED;
wait_time := 33; -- Till r0
-- This is to get Form error on r0 (after EDL) RECESSIVE
get_core_mode(mode_2, ID_2, mem_bus(2));
mode_2.flexible_data_rate := true;
set_core_mode(mode_2, ID_2, mem_bus(2));
end case;
CAN_send_frame(frame_1, 1, ID_1, mem_bus(1), frame_sent);
CAN_wait_pc_state(pc_deb_arbitration, ID_1, mem_bus(1));
CAN_wait_pc_state(pc_deb_arbitration, ID_2, mem_bus(2));
info("Waiting for: " & integer'image(wait_time) & " bits!");
for j in 1 to wait_time loop
CAN_wait_sample_point(iout(1).stat_bus, true);
CAN_wait_sample_point(iout(2).stat_bus, true);
end loop;
-- Force bus for one bit time
force_bus_level(RECESSIVE, so.bl_force, so.bl_inject);
CAN_wait_sample_point(iout(1).stat_bus, false);
CAN_wait_sample_point(iout(2).stat_bus, false);
wait for 20 ns; -- To be sure that opposite bit is sampled!
release_bus_level(so.bl_force);
-- Check errors
get_controller_status(stat_1, ID_1, mem_bus(1));
check (stat_1.error_transmission,
get_controller_status(stat_2, ID_2, mem_bus(2));
check (stat_2.error_transmission,
"Error frame is being transmitted!");
CAN_read_error_code_capture(err_capt, ID_1, mem_bus(1));
CAN_read_error_code_capture(err_capt, ID_2, mem_bus(2));
check(err_capt.err_type = can_err_form, "Form error detected!");
check(err_capt.err_pos = err_pos_ctrl,
"Error detected in Control field!");
wait for 100 ns; -- For debug only to see waves properly!
-- Reset the node
exec_SW_reset(ID_1, mem_bus(1));
CAN_turn_controller(true, ID_1, mem_bus(1));
CAN_wait_bus_on(ID_1, mem_bus(1));
CAN_read_error_code_capture(err_capt, ID_1, mem_bus(1));
exec_SW_reset(ID_1, mem_bus(2));
CAN_turn_controller(true, ID_2, mem_bus(2));
CAN_wait_bus_on(ID_2, mem_bus(2));
CAN_read_error_code_capture(err_capt, ID_2, mem_bus(2));
check(err_capt.err_pos = err_pos_other, "Reset value other");
end loop;
......
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