Commit e527ba9d authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch 'rx_data_to_ram' into 'master'

Rx data to ram

See merge request illeondr/CAN_FD_IP_Core!3
parents c638e462 0ff8e43f
This diff is collapsed.
......@@ -36085,6 +36085,7 @@ Default value
\begin_layout Description
TXT_1_EMPTY Active when Transmit buffer 1 is empty.
\end_layout
\begin_layout Description
......@@ -36109,15 +36110,12 @@ label{sec:TX_SETTINGS}
\end_layout
\begin_layout Description
Type: Read / Write - Partially automatically erased
Type: Read / Write
\end_layout
\begin_layout Standard
This register controls the frame inserton into the TX buffers (The frame
to be transmitted in registers TX_DATA_1 to TX_DATA_20).
This register controls the access into TX buffers.
All bits are active in logic 1.
Once a frame is committed into the buffer it is transmitted as soon as
it passes TX Arbitrator.
\begin_inset Separator latexpar
\end_inset
......@@ -36128,14 +36126,13 @@ This register controls the frame inserton into the TX buffers (The frame
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="3" columns="6">
<lyxtabular version="3" rows="3" columns="5">
<features tabularvalignment="middle">
<column alignment="center" valignment="top">
<column alignment="center" valignment="top">
<column alignment="center" valignment="top">
<column alignment="center" valignment="top">
<column alignment="center" valignment="top">
<column alignment="center" valignment="top">
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text
......@@ -36150,16 +36147,7 @@ Bit offset
\begin_inset Text
\begin_layout Plain Layout
31-4
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
3
31-3
\end_layout
\end_inset
......@@ -36215,16 +36203,7 @@ Reserved
\begin_inset Text
\begin_layout Plain Layout
TXT_2_COMMIT
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
TXT_1_COMMIT
BUF_DIR
\end_layout
\end_inset
......@@ -36233,7 +36212,7 @@ TXT_1_COMMIT
\begin_inset Text
\begin_layout Plain Layout
TXT_2_ALLOW
TXT2_ALLOW
\end_layout
\end_inset
......@@ -36242,7 +36221,7 @@ TXT_2_ALLOW
\begin_inset Text
\begin_layout Plain Layout
TXT_1_ALLOW
TXT1_ALLOW
\end_layout
\end_inset
......@@ -36279,15 +36258,6 @@ Default value
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
1
\end_layout
......@@ -36312,23 +36282,22 @@ Default value
\end_layout
\begin_layout Description
TXT_2_ALLOW Allow transmitting frames from TXT buffer 2.
\end_layout
\begin_layout Description
TXT_1_ALLOW Allow transmitting frames from TXT buffer 1.
\end_layout
\begin_layout Description
TXT_2_COMMIT When active value is written into this bit, frame in registers
TX_DATA_1 to TX_DATA_20 are inserted into Transmit buffer 2.
Afterward, this value is automatically erased.
TXTX_ALLOW Allow transmitting frames from TXT buffer X (1 or 2).
Content of TX Buffer (1 or 2) is validated by 0 to 1 transition on these
bits.
\end_layout
\begin_layout Description
TXT_1_COMMIT When active value is written into this bit, frame in registers
TX_DATA_1 to TX_DATA_20 are inserted into Transmit buffer 1.
Afterward, this value is automatically erased.
BUF_DIR Buffer to which the transmit data should be stored.
To insert data for transmission first set TXTX_ALLOW to 0, then set BUF_DIR
to select TXT_BUFFER buffer.
As next write the data into buffer by executing accesses into TX_DATA_X
registers.
As last step, validate the content of the buffer by setting TXTX_ALLOW
to 1.
TXT_1_EMPTY bit of TX_STAT register is automatically cleared by this action.
\end_layout
\begin_layout Section
......@@ -36353,8 +36322,8 @@ Type: Write
\end_layout
\begin_layout Standard
Registers TX_DATA_1 to TX_DATA_20 contain frame to be inserted into transmit
buffers.
Acesses from TX_DATA_1 to TX_DATA_20 reflect into accesses into TXT buffer.
Destination TXT buffer is selected by BUF_DIR bit in TX_SETTINGS register.
The data in these registers must have the following format in order to
be properly sent:
\begin_inset Separator latexpar
......@@ -47962,7 +47931,6 @@ The main purpose of this testing is to reveal errors which were not covered
In order to achieve this reference controllers are used for communication.
Without reference controller there is always a chance that error will be
compensated by receiving node thus error remains undetected.
\end_layout
\begin_layout Standard
......@@ -48157,14 +48125,6 @@ tranBuffer
and TXT_Buffer to be synthesized into RAM elements, not to LUTs.
\end_layout
\begin_layout Itemize
Actual implementation stores Transmitted frame in 3 following pipeline stages:
Memory registers, TXT Buffers and TranBuffer.
This requires up to 3*640 memory bits! It might be beneficial to optimize
the architecture in such a manner that one of the stages will be ommited!
E.g user would be directly writing into TXT_Buffer and not to the registers.
\end_layout
\begin_layout Itemize
Add hard synchronisation and resynchronisation part into Prescaler unit
test
......@@ -16886,7 +16886,7 @@ rec_message_valid
input signal is in logic 1 first word is stored.
In following up to 19 clock cycles remaining words are stored.
This requires the received data to be valid for at least 20 clock cycles
(register in CAN Core).
(RAM in CAN Core).
Since frame is validated at the end of EOF field, until received data are
erased by the next frame, bus is in the intermission field.
Having minimum 7 clock cycles per nominal bit time this gives minimum 21
......@@ -36085,6 +36085,7 @@ Default value
\begin_layout Description
TXT_1_EMPTY Active when Transmit buffer 1 is empty.
\end_layout
\begin_layout Description
......@@ -36109,15 +36110,12 @@ label{sec:TX_SETTINGS}
\end_layout
\begin_layout Description
Type: Read / Write - Partially automatically erased
Type: Read / Write
\end_layout
\begin_layout Standard
This register controls the frame inserton into the TX buffers (The frame
to be transmitted in registers TX_DATA_1 to TX_DATA_20).
This register controls the access into TX buffers.
All bits are active in logic 1.
Once a frame is committed into the buffer it is transmitted as soon as
it passes TX Arbitrator.
\begin_inset Separator latexpar
\end_inset
......@@ -36128,14 +36126,13 @@ This register controls the frame inserton into the TX buffers (The frame
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="3" columns="6">
<lyxtabular version="3" rows="3" columns="5">
<features tabularvalignment="middle">
<column alignment="center" valignment="top">
<column alignment="center" valignment="top">
<column alignment="center" valignment="top">
<column alignment="center" valignment="top">
<column alignment="center" valignment="top">
<column alignment="center" valignment="top">
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text
......@@ -36150,16 +36147,7 @@ Bit offset
\begin_inset Text
\begin_layout Plain Layout
31-4
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
3
31-3
\end_layout
\end_inset
......@@ -36215,16 +36203,7 @@ Reserved
\begin_inset Text
\begin_layout Plain Layout
TXT_2_COMMIT
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
TXT_1_COMMIT
BUF_DIR
\end_layout
\end_inset
......@@ -36233,7 +36212,7 @@ TXT_1_COMMIT
\begin_inset Text
\begin_layout Plain Layout
TXT_2_ALLOW
TXT2_ALLOW
\end_layout
\end_inset
......@@ -36242,7 +36221,7 @@ TXT_2_ALLOW
\begin_inset Text
\begin_layout Plain Layout
TXT_1_ALLOW
TXT1_ALLOW
\end_layout
\end_inset
......@@ -36279,15 +36258,6 @@ Default value
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
1
\end_layout
......@@ -36312,23 +36282,22 @@ Default value
\end_layout
\begin_layout Description
TXT_2_ALLOW Allow transmitting frames from TXT buffer 2.
\end_layout
\begin_layout Description
TXT_1_ALLOW Allow transmitting frames from TXT buffer 1.
\end_layout
\begin_layout Description
TXT_2_COMMIT When active value is written into this bit, frame in registers
TX_DATA_1 to TX_DATA_20 are inserted into Transmit buffer 2.
Afterward, this value is automatically erased.
TXTX_ALLOW Allow transmitting frames from TXT buffer X (1 or 2).
Content of TX Buffer (1 or 2) is validated by 0 to 1 transition on these
bits.
\end_layout
\begin_layout Description
TXT_1_COMMIT When active value is written into this bit, frame in registers
TX_DATA_1 to TX_DATA_20 are inserted into Transmit buffer 1.
Afterward, this value is automatically erased.
BUF_DIR Buffer to which the transmit data should be stored.
To insert data for transmission first set TXTX_ALLOW to 0, then set BUF_DIR
to select TXT_BUFFER buffer.
As next write the data into buffer by executing accesses into TX_DATA_X
registers.
As last step, validate the content of the buffer by setting TXTX_ALLOW
to 1.
TXT_1_EMPTY bit of TX_STAT register is automatically cleared by this action.
\end_layout
\begin_layout Section
......@@ -36353,8 +36322,8 @@ Type: Write
\end_layout
\begin_layout Standard
Registers TX_DATA_1 to TX_DATA_20 contain frame to be inserted into transmit
buffers.
Acesses from TX_DATA_1 to TX_DATA_20 reflect into accesses into TXT buffer.
Destination TXT buffer is selected by BUF_DIR bit in TX_SETTINGS register.
The data in these registers must have the following format in order to
be properly sent:
\begin_inset Separator latexpar
......@@ -48157,14 +48126,6 @@ tranBuffer
and TXT_Buffer to be synthesized into RAM elements, not to LUTs.
\end_layout
\begin_layout Itemize
Actual implementation stores Transmitted frame in 3 following pipeline stages:
Memory registers, TXT Buffers and TranBuffer.
This requires up to 3*640 memory bits! It might be beneficial to optimize
the architecture in such a manner that one of the stages will be ommited!
E.g user would be directly writing into TXT_Buffer and not to the registers.
\end_layout
\begin_layout Itemize
Add hard synchronisation and resynchronisation part into Prescaler unit
test
......@@ -29,15 +29,15 @@ use work.CANconstants.all;
-- Revision History:
--
-- July 2015 Created file
--
-- 30.11.2017 Changed the buffer implementation from parallel into 32*20 buffer of data. Reading so far
-- left parallel. User is directly accessing the buffer and storing the data to it.
-------------------------------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------
-- Purpose:
-- Transmit message buffer. RAM type memory. Storing by command on drv bus. All the data stored at once --
-- Erasing by activating signal txt_data_ack. Possible to store and erase at the same cycle without --
-- losing the data. If buffer is full and new data are commited then data are not written but lost. --
-- txt_disc output is active in this case ! --
-- Transmit message buffer. Access to TX_DATA_REG of user registers is combinationally mapped
-- to the TXT Buffers. User is storing the data directly into the TX buffer. Once the user allows to
-- transmitt from the buffer, content of the buffer is validated and "empty" is cleared.
---------------------------------------------------------------------------------------------------------
entity txtBuffer is
......@@ -56,19 +56,20 @@ entity txtBuffer is
--Driving Registers Interface--
-------------------------------
signal drv_bus :in std_logic_vector(1023 downto 0); --Driving bus
signal tran_data_in :in std_logic_vector(639 downto 0); --Input data frame (Format B value of transcieve register of driving registers)
signal tran_data :in std_logic_vector(31 downto 0); --Data into the RAM of TXT Buffer
signal tran_addr :in std_logic_vector(4 downto 0); --Address in the RAM of TXT buffer
------------------
--Status signals--
------------------
signal txt_empty :out std_logic; --Logic 1 signals empty TxTime buffer
signal txt_disc :out std_logic; --Info that message store into buffer from driving registers failed because buffer is full
------------------------------------
--CAN Core and TX Arbiter Interface-
------------------------------------
signal txt_buffer_out :out std_logic_vector(639 downto 0); --Output value of message in the buffer
signal txt_data_ack :in std_logic --Signal from TX Arbiter that data were sent and buffer can be erased
signal txt_data_ack :in std_logic --Signal from TX Arbiter that data were sent and buffer can be erased
);
end entity;
......@@ -79,205 +80,81 @@ architecture rtl of txtBuffer is
----------------------
--Internal registers--
----------------------
type memory is array(0 to 0) of
std_logic_vector(639 downto 0);
--Modification for SRAM inferrence, only attempt
--type RAM_memory is array(0 to 0) of std_logic_vector(127 downto 0);
--signal data_memory:RAM_memory;
type short_memory is array(0 to 0) of
std_logic_vector(639 downto 448);
signal txt_empty_reg :std_logic; --Register of empty buffer
signal prev_store :std_logic; --Registred value of store command for edge detection
type memory is array(0 to 19) of
std_logic_vector(31 downto 0);
------------------
--Signal aliases--
------------------
signal drv_erase_txt :std_logic; --Command for erasing time transcieve buffer
signal drv_store_txt :std_logic; --Command for storing data from tran_data_in into txt_buffer
signal txt_buffer : memory; -- Time transcieve buffer
signal tran_wr : std_logic_vector(1 downto 0); -- Store into TXT buffer 1 or 2
signal txt_empty_reg : std_logic; -- Status of the register
constant empty :std_logic_vector(447 downto 0):=(OTHERS=>'0');
signal drv_allow : std_logic;
signal drv_allow_reg : std_logic; -- Registered value for the detection 0-1 transition and signalling that the buffer is full
signal txt_buffer :memory; --Time transcieve buffer
signal txt_buffer_s :short_memory; --Time transcieve buffer
begin
drv_erase_txt <= drv_bus(DRV_ERASE_TXT1_INDEX) when ID=1 else
drv_bus(DRV_ERASE_TXT2_INDEX) when ID=2 else
'0';
drv_store_txt <= drv_bus(DRV_STORE_TXT1_INDEX) when ID=1 else
drv_bus(DRV_STORE_TXT2_INDEX) when ID=2 else
'0';
--Write signals for buffer
tran_wr <= drv_bus(DRV_TXT2_WR)&drv_bus(DRV_TXT1_WR);
txt_empty <= txt_empty_reg;
GEN:if(useFDsize=true)generate
--Driving bus aliases
drv_allow <= drv_bus(DRV_ALLOW_TXT1_INDEX) when ID=1 else
drv_bus(DRV_ALLOW_TXT2_INDEX) when ID=2 else
'0';
--Output assignment and aliases
--txt_buffer_out <= txt_buffer(0);
txt_buffer_out <= txt_buffer(0);
txt_buffer_s(0) <= (OTHERS=>'0');
mem_acess:process(clk_sys,res_n)
variable aux:std_logic_vector(1 downto 0); --Auxiliarly variable
begin
if (res_n=ACT_RESET) then
txt_buffer(0) <= (OTHERS=>'0');
txt_disc <= '0';
txt_empty_reg <= '1';
prev_store <= '0';
elsif rising_edge(clk_sys) then
-- So far reading of the data from buffer is parelell. It will be modified to reading by word...
sizegen_fd: if (useFDsize=true) generate
txt_buffer_out <= txt_buffer(0)&txt_buffer(1)&txt_buffer(2)&txt_buffer(3)&
txt_buffer(4)&txt_buffer(5)&txt_buffer(6)&txt_buffer(7)&txt_buffer(8)&
txt_buffer(9)&txt_buffer(10)&txt_buffer(11)&txt_buffer(12)&txt_buffer(13)&
txt_buffer(14)&txt_buffer(15)&txt_buffer(16)&txt_buffer(17)&txt_buffer(18)&txt_buffer(19);
end generate;
--Registering the store value for edge detection
prev_store <= drv_erase_txt;
------------------------------------------------------------
--Decoding the control signals for storing and erasing the
--buffer into auxiliarly variable
------------------------------------------------------------
if((drv_erase_txt='1') or (txt_data_ack='1'))then
if(drv_store_txt='1' and prev_store='0')then
aux := "11";
else
aux := "01";
end if;
else
if(drv_store_txt='1' and prev_store='0')then
aux:="10";
else
aux:="00";
end if;
end if;
-----------------------------------------
--Storing and erasing the memory buffer--
-----------------------------------------
case aux is
--Since RAM is read only by TX Arbitrator and CAN Core, we can just disconnect the outputs
-- if we dont want to synthesize the Full FD support. Synthesizer will then remove part of the
-- memory/registers since there will be no fan-out.
sizegen_nofd: if (useFDsize=false) generate
txt_buffer_out(639 downto 448) <= txt_buffer(0)&txt_buffer(1)&txt_buffer(2)&txt_buffer(3)&
txt_buffer(4)&txt_buffer(5);
txt_buffer_out(446 downto 0) <= (OTHERS => '0');
end generate;
--------------------------------------------------------------------------------
-- Main buffer comment
--------------------------------------------------------------------------------
tx_buf_proc:process(res_n,clk_sys)
begin
if (res_n = ACT_RESET) then
--No write, No discard
when "00" =>
txt_buffer <= txt_buffer;
txt_disc <= '0';
txt_empty_reg <= txt_empty_reg;
-- In order to use RAM for the buffer, async reset cannot be done!
-- synthesis translate_off
txt_buffer <= (OTHERS => (OTHERS => '0'));
-- synthesis translate_on
--No write, discard
when "01" =>
txt_buffer(0) <= (OTHERS=>'0');
txt_empty_reg <= '1';
txt_disc <= '0';
txt_empty_reg <= '1';
elsif (rising_edge(clk_sys))then
--Write, No discard
when "10" =>
if(txt_empty_reg='0')then
txt_buffer <= txt_buffer;
txt_disc <= '1';
else
txt_buffer(0) <= tran_data_in;
txt_disc<='0';
end if;
txt_empty_reg <= '0';
--Registering the previous allow value
drv_allow_reg <= drv_allow;
--Write, and discard
when "11" =>
if(txt_empty_reg='0')then --If write and discard is at same then old data discarded new data stored
txt_empty_reg <= '0';
txt_disc <= '0';
txt_buffer(0) <= tran_data_in;
else
txt_empty_reg <= '0';
txt_buffer(0) <= tran_data_in;
txt_disc <= '0';
end if;
when others =>
txt_buffer <= txt_buffer;
txt_empty_reg <= txt_empty_reg;
txt_disc <= '0';
end case;
end if;
end process mem_acess;
end generate GEN;
GEN2:if(useFDsize=false)generate
--Output assignment and aliases
txt_buffer_out <= txt_buffer_s(0)&empty;
txt_buffer(0) <= (OTHERS=>'0');
mem_acess:process(clk_sys,res_n)
variable aux:std_logic_vector(1 downto 0); --Auxiliarly variable
begin
if res_n=ACT_RESET then
txt_buffer_s(0) <= (OTHERS=>'0');
txt_disc <= '0';
txt_empty_reg <= '1';
prev_store <= '0';
elsif rising_edge(clk_sys) then
--Registering the store value for edge detection
prev_store<=drv_erase_txt;
--Updating the value of empty either from Registers or TX Arbitrator
if (txt_data_ack='1') then
txt_empty_reg <= '1';
elsif (drv_allow_reg='0' and drv_allow='1') then -- 0-1 on drv_allow signals validation of the buffer content!
txt_empty_reg <= '0';
else
txt_empty_reg <= txt_empty_reg;
end if;
------------------------------------------------------------
--Decoding the control signals for storing and erasing the
--buffer into auxiliarly variable
------------------------------------------------------------
if((drv_erase_txt='1') or (txt_data_ack='1'))then
if(drv_store_txt='1' and prev_store='0')then
aux := "11";
else
aux := "01";
end if;
else
if(drv_store_txt='1' and prev_store='0')then
aux := "10";
else
aux := "00";
end if;
end if;
--Store the data into the Buffer during the access
if (tran_wr(ID-1)='1') then
txt_buffer(to_integer(unsigned(tran_addr))) <= tran_data;
end if;
-----------------------------------------
--Storing and erasing the memory buffer--
-----------------------------------------
case aux is
when "00" => --No write, No discard
txt_buffer_s <= txt_buffer_s;
txt_disc <= '0';