Commit e262087d authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.
Browse files

Merge branch '232-add-timestamp-support-to-can-testlib' into 'master'

Resolve "Add Timestamp support to  CAN Testlib"

Closes #232

See merge request !201
parents bfbe8fbb 1edf8384
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018
--
-- Authors:
-- Ondrej Ille <ondrej.ille@gmail.com>
-- Martin Jerabek <martin.jerabek01@gmail.com>
--
-- Project advisors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
--
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Feature test for Timestamp options on RX frame in RX Buffer!
--
--------------------------------------------------------------------------------
-- Revision History:
--
-- 29.6.2018 Created file
--------------------------------------------------------------------------------
context work.ctu_can_synth_context;
context work.ctu_can_test_context;
use lib.pkg_feature_exec_dispath.all;
package timestamp_registers_feature is
procedure timestamp_registers_feature_exec(
variable o : out feature_outputs_t;
signal so : out feature_signal_outputs_t;
signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE;
signal iout : in instance_outputs_arr_t;
signal mem_bus : inout mem_bus_arr_t;
signal bus_level : in std_logic
);
end package;
package body timestamp_registers_feature is
procedure timestamp_registers_feature_exec(
variable o : out feature_outputs_t;
signal so : out feature_signal_outputs_t;
signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE;
signal iout : in instance_outputs_arr_t;
signal mem_bus : inout mem_bus_arr_t;
signal bus_level : in std_logic
) is
variable r_data : std_logic_vector(31 downto 0) :=
(OTHERS => '0');
variable ID_1 : natural := 1;
variable diff : unsigned(63 downto 0);
variable ts_input : std_logic_vector(63 downto 0);
variable ts_read : std_logic_vector(63 downto 0);
begin
o.outcome := true;
wait for 1000 ns;
for i in 0 to 50 loop
-------------------------------------------------------------------
-- Read and save timestamp from registers
-------------------------------------------------------------------
ts_input := iout(1).stat_bus(STAT_TS_HIGH downto STAT_TS_LOW);
-------------------------------------------------------------------
-- Read timestamp with lib function
-------------------------------------------------------------------
CAN_read_timestamp(ts_read, ID_1, mem_bus(1));
-------------------------------------------------------------------
-- Compare both values
-------------------------------------------------------------------
info("Timestamp input: 0x" & to_hstring(ts_input));
info("Timestamp read: 0x" & to_hstring(ts_read));
-------------------------------------------------------------------
-- Substract Read timestamp from Input timestamp. Input timestamp is
-- stored first, thus it will be always lower than read timestamp
-- (memory access lasts one clock cycle). When substracting in this
-- order, we avoid underflow on "unsigned" data type, which is
-- defined from 0.
-------------------------------------------------------------------
diff := unsigned(ts_read) - unsigned(ts_input);
check(to_integer(diff) < 10, "Timestamp difference is too big! " &
"Difference " & integer'image(to_integer(diff)));
end loop;
end procedure;
end package body;
......@@ -1788,6 +1788,22 @@ package CANtestLib is
signal mem_bus : inout Avalon_mem_type
);
----------------------------------------------------------------------------
-- Read Timestamp from TIMESTAMP_LOW and TIMESTAMP_HIGH registers
--
-- Arguments:
-- ts Variable in which timestamp will be stored
-- ID Index of CTU CAN FD Core instance.
-- mem_bus Avalon memory bus to execute the access on.
----------------------------------------------------------------------------
procedure CAN_read_timestamp(
variable ts : out std_logic_vector(63 downto 0);
constant ID : in natural range 0 to 15;
signal mem_bus : inout Avalon_mem_type
);
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Component declarations
......@@ -4383,6 +4399,24 @@ package body CANtestLib is
trv_delay := to_integer(unsigned(data(
TRV_DELAY_VALUE_H downto TRV_DELAY_VALUE_L)));
end procedure;
procedure CAN_read_timestamp(
variable ts : out std_logic_vector(63 downto 0);
constant ID : in natural range 0 to 15;
signal mem_bus : inout Avalon_mem_type
) is
variable lower_word : std_logic_vector(31 downto 0);
variable upper_word : std_logic_vector(31 downto 0);
begin
CAN_read(lower_word, TIMESTAMP_LOW_ADR, ID, mem_bus);
CAN_read(upper_word, TIMESTAMP_HIGH_ADR, ID, mem_bus);
ts := upper_word & lower_word;
end procedure;
end package body;
......
......@@ -10,4 +10,4 @@ feature:
timeout: 100 ms
wave: feature/feature_env_setup.tcl
tests:
suspend_transmission:
timestamp_registers:
......@@ -70,6 +70,7 @@ feature:
iterations: 1
message_filter:
iterations: 1
timestamp_registers:
reference:
default:
<<: *default
......
......@@ -99,6 +99,7 @@ feature:
iterations: 1
message_filter:
iterations: 1
timestamp_registers:
sanity:
default:
<<: *default
......
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