Commit e1eeb945 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch '134-buffer-data-endianess' into 'master'

Resolve "Buffer Data endianess"

Closes #134

See merge request illeondr/CAN_FD_IP_Core!70
parents 8bc20139 47243466
This diff is collapsed.
......@@ -143,15 +143,15 @@ union ctu_can_fd_data_1_4_w {
struct ctu_can_fd_data_1_4_w_s {
#ifdef __LITTLE_ENDIAN_BITFIELD
/* DATA_1_4_W */
uint32_t data_4 : 8;
uint32_t data_3 : 8;
uint32_t data_2 : 8;
uint32_t data_1 : 8;
#else
uint32_t data_1 : 8;
uint32_t data_2 : 8;
uint32_t data_3 : 8;
uint32_t data_4 : 8;
#else
uint32_t data_4 : 8;
uint32_t data_3 : 8;
uint32_t data_2 : 8;
uint32_t data_1 : 8;
#endif
} s;
};
......@@ -161,15 +161,15 @@ union ctu_can_fd_data_5_8_w {
struct ctu_can_fd_data_5_8_w_s {
#ifdef __LITTLE_ENDIAN_BITFIELD
/* DATA_5_8_W */
uint32_t data_8 : 8;
uint32_t data_7 : 8;
uint32_t data_6 : 8;
uint32_t data_5 : 8;
#else
uint32_t data_5 : 8;
uint32_t data_6 : 8;
uint32_t data_7 : 8;
uint32_t data_8 : 8;
#else
uint32_t data_8 : 8;
uint32_t data_7 : 8;
uint32_t data_6 : 8;
uint32_t data_5 : 8;
#endif
} s;
};
......@@ -179,15 +179,15 @@ union ctu_can_fd_data_61_64_w {
struct ctu_can_fd_data_61_64_w_s {
#ifdef __LITTLE_ENDIAN_BITFIELD
/* DATA_61_64_W */
uint32_t data_64 : 8;
uint32_t data_63 : 8;
uint32_t data_62 : 8;
uint32_t data_61 : 8;
#else
uint32_t data_61 : 8;
uint32_t data_62 : 8;
uint32_t data_63 : 8;
uint32_t data_64 : 8;
#else
uint32_t data_64 : 8;
uint32_t data_63 : 8;
uint32_t data_62 : 8;
uint32_t data_61 : 8;
#endif
} s;
};
......
This diff is collapsed.
......@@ -3675,26 +3675,26 @@ and synchronisation edge appeared during resynchronisation.</ipxact:description>
<ipxact:size>32</ipxact:size>
<ipxact:field>
<ipxact:name>DATA_1</ipxact:name>
<ipxact:description>Data byte 1 of the CAN Frame.</ipxact:description>
<ipxact:bitOffset>24</ipxact:bitOffset>
<ipxact:description>Data byte 1 of CAN Frame.</ipxact:description>
<ipxact:bitOffset>0</ipxact:bitOffset>
<ipxact:bitWidth>8</ipxact:bitWidth>
</ipxact:field>
<ipxact:field>
<ipxact:name>DATA_2</ipxact:name>
<ipxact:description>Data byte 2 of the CAN Frame.</ipxact:description>
<ipxact:bitOffset>16</ipxact:bitOffset>
<ipxact:description>Data byte 2 of CAN Frame.</ipxact:description>
<ipxact:bitOffset>8</ipxact:bitOffset>
<ipxact:bitWidth>8</ipxact:bitWidth>
</ipxact:field>
<ipxact:field>
<ipxact:name>DATA_3</ipxact:name>
<ipxact:description>Data byte 3 of the CAN Frame.</ipxact:description>
<ipxact:bitOffset>8</ipxact:bitOffset>
<ipxact:description>Data byte 3 of CAN Frame.</ipxact:description>
<ipxact:bitOffset>16</ipxact:bitOffset>
<ipxact:bitWidth>8</ipxact:bitWidth>
</ipxact:field>
<ipxact:field>
<ipxact:name>DATA_4</ipxact:name>
<ipxact:description>Data byte 4 of the CAN Frame.</ipxact:description>
<ipxact:bitOffset>0</ipxact:bitOffset>
<ipxact:description>Data byte 4 of CAN Frame.</ipxact:description>
<ipxact:bitOffset>24</ipxact:bitOffset>
<ipxact:bitWidth>8</ipxact:bitWidth>
</ipxact:field>
</ipxact:register>
......@@ -3706,26 +3706,26 @@ and synchronisation edge appeared during resynchronisation.</ipxact:description>
<ipxact:size>32</ipxact:size>
<ipxact:field>
<ipxact:name>DATA_61</ipxact:name>
<ipxact:description>Data byte 61 of the CAN Frame.</ipxact:description>
<ipxact:bitOffset>24</ipxact:bitOffset>
<ipxact:description>Data byte 61 of CAN Frame.</ipxact:description>
<ipxact:bitOffset>0</ipxact:bitOffset>
<ipxact:bitWidth>8</ipxact:bitWidth>
</ipxact:field>
<ipxact:field>
<ipxact:name>DATA_62</ipxact:name>
<ipxact:description>Data byte 62 of the CAN Frame.</ipxact:description>
<ipxact:bitOffset>16</ipxact:bitOffset>
<ipxact:description>Data byte 62 of CAN Frame.</ipxact:description>
<ipxact:bitOffset>8</ipxact:bitOffset>
<ipxact:bitWidth>8</ipxact:bitWidth>
</ipxact:field>
<ipxact:field>
<ipxact:name>DATA_63</ipxact:name>
<ipxact:description>Data byte 63 of the CAN Frame.</ipxact:description>
<ipxact:bitOffset>8</ipxact:bitOffset>
<ipxact:description>Data byte 63 of CAN Frame.</ipxact:description>
<ipxact:bitOffset>16</ipxact:bitOffset>
<ipxact:bitWidth>8</ipxact:bitWidth>
</ipxact:field>
<ipxact:field>
<ipxact:name>DATA_64</ipxact:name>
<ipxact:description>Data byte 64 of the CAN Frame.</ipxact:description>
<ipxact:bitOffset>0</ipxact:bitOffset>
<ipxact:description>Data byte 64 of CAN Frame.</ipxact:description>
<ipxact:bitOffset>24</ipxact:bitOffset>
<ipxact:bitWidth>8</ipxact:bitWidth>
</ipxact:field>
</ipxact:register>
......@@ -3737,26 +3737,26 @@ and synchronisation edge appeared during resynchronisation.</ipxact:description>
<ipxact:size>32</ipxact:size>
<ipxact:field>
<ipxact:name>DATA_5</ipxact:name>
<ipxact:description>Data byte 5 of the CAN Frame.</ipxact:description>
<ipxact:bitOffset>24</ipxact:bitOffset>
<ipxact:description>Data byte 5 of CAN Frame.</ipxact:description>
<ipxact:bitOffset>0</ipxact:bitOffset>
<ipxact:bitWidth>8</ipxact:bitWidth>
</ipxact:field>
<ipxact:field>
<ipxact:name>DATA_6</ipxact:name>
<ipxact:description>Data byte 6 of the CAN Frame.</ipxact:description>
<ipxact:bitOffset>16</ipxact:bitOffset>
<ipxact:description>Data byte 6 of CAN Frame.</ipxact:description>
<ipxact:bitOffset>8</ipxact:bitOffset>
<ipxact:bitWidth>8</ipxact:bitWidth>
</ipxact:field>
<ipxact:field>
<ipxact:name>DATA_7</ipxact:name>
<ipxact:description>Data byte 7 of the CAN Frame.</ipxact:description>
<ipxact:bitOffset>8</ipxact:bitOffset>
<ipxact:description>Data byte 7 of CAN Frame.</ipxact:description>
<ipxact:bitOffset>16</ipxact:bitOffset>
<ipxact:bitWidth>8</ipxact:bitWidth>
</ipxact:field>
<ipxact:field>
<ipxact:name>DATA_8</ipxact:name>
<ipxact:description>Data byte 8 of the CAN Frame.</ipxact:description>
<ipxact:bitOffset>0</ipxact:bitOffset>
<ipxact:description>Data byte 8 of CAN Frame.</ipxact:description>
<ipxact:bitOffset>24</ipxact:bitOffset>
<ipxact:bitWidth>8</ipxact:bitWidth>
</ipxact:field>
</ipxact:register>
......
......@@ -196,9 +196,11 @@
-- 6.4.2018 Added direct addressing of identifier from Protocol control.
-- In SOF TXT buffer pointer is set to identifier word and
-- Identifier is stored in the first cycle of Arbitration field.
-- 19.5.2018 Added "store_data", "store_metadata", "rec_abort" signals
-- as a storing protocol between CAN Core and RX Buffer for
-- continous storing of CAN frame during reception.
-- 19.5.2018 1. Added "store_data", "store_metadata", "rec_abort" signals
-- as a storing protocol between CAN Core and RX Buffer for
-- continous storing of CAN frame during reception.
-- 2. Added endian swap for transceived and received data to
-- have Data byte 0 at address 0.
--------------------------------------------------------------------------------
Library ieee;
......@@ -208,6 +210,8 @@ use work.CANconstants.all;
use work.CAN_FD_frame_format.all;
use work.CAN_FD_register_map.all;
use work.endian_swap.all;
entity protocolControl is
port(
-------------------
......@@ -618,6 +622,9 @@ entity protocolControl is
--Pointer directly to TXT buffer to get the data
signal txt_buf_ptr_r : natural range 0 to 19;
-- Data word to transmit after endian swapping.
signal tx_data_word : std_logic_vector(31 downto 0);
-----------------------
--CRC field registers--
......@@ -767,6 +774,9 @@ begin
txt_buf_ptr <= txt_buf_ptr_r;
sof_pulse <= sof_pulse_r;
-- TX Data word endian swap
tx_data_word <= endian_swap_32(tran_data);
-----------------------
--Auxiliarly vectors
......@@ -1795,10 +1805,9 @@ begin
if(OP_State=transciever)then
if(tran_trig='1')then
--data_tx_r <= tran_data(data_pointer);
data_tx_r <= tran_data(data_pointer mod 32);
data_tx_r <= tx_data_word(data_pointer mod 32);
--Move to the next word
-- Move to the next word
if ((data_pointer mod 32) = 0) then
if (txt_buf_ptr_r < 19) then
txt_buf_ptr_r <= txt_buf_ptr_r + 1;
......@@ -1822,22 +1831,22 @@ begin
rec_word_bind <= (rec_word_bind + 1) mod 4;
case rec_word_bind is
when 0 =>
store_data_word_r <= rec_data_sr(6 downto 0) &
data_rx &
"000000000000000000000000";
-- First byte of word, whole word is written to avoid
-- bytes from old frames!
store_data_word_r <= "000000000000000000000000" &
rec_data_sr(6 downto 0) &
data_rx;
when 1 =>
store_data_word_r(23 downto 0) <=
store_data_word_r(15 downto 8) <=
rec_data_sr(6 downto 0) &
data_rx &
"0000000000000000";
data_rx;
when 2 =>
store_data_word_r(15 downto 0) <=
store_data_word_r(23 downto 16) <=
rec_data_sr(6 downto 0) &
data_rx &
"00000000";
data_rx;
when 3 =>
store_data_word_r(7 downto 0) <=
rec_data_sr(6 downto 0)&
store_data_word_r(31 downto 24) <=
rec_data_sr(6 downto 0) &
data_rx;
when others =>
report "Unknown state" severity error;
......
......@@ -137,14 +137,14 @@ package CAN_FD_frame_format is
-- DATA_1_4_W register
--
------------------------------------------------------------------------------
constant DATA_4_L : natural := 0;
constant DATA_4_H : natural := 7;
constant DATA_3_L : natural := 8;
constant DATA_3_H : natural := 15;
constant DATA_2_L : natural := 16;
constant DATA_2_H : natural := 23;
constant DATA_1_L : natural := 24;
constant DATA_1_H : natural := 31;
constant DATA_1_L : natural := 0;
constant DATA_1_H : natural := 7;
constant DATA_2_L : natural := 8;
constant DATA_2_H : natural := 15;
constant DATA_3_L : natural := 16;
constant DATA_3_H : natural := 23;
constant DATA_4_L : natural := 24;
constant DATA_4_H : natural := 31;
-- DATA_1_4_W register reset values
......@@ -152,14 +152,14 @@ package CAN_FD_frame_format is
-- DATA_5_8_W register
--
------------------------------------------------------------------------------
constant DATA_8_L : natural := 0;
constant DATA_8_H : natural := 7;
constant DATA_7_L : natural := 8;
constant DATA_7_H : natural := 15;
constant DATA_6_L : natural := 16;
constant DATA_6_H : natural := 23;
constant DATA_5_L : natural := 24;
constant DATA_5_H : natural := 31;
constant DATA_5_L : natural := 0;
constant DATA_5_H : natural := 7;
constant DATA_6_L : natural := 8;
constant DATA_6_H : natural := 15;
constant DATA_7_L : natural := 16;
constant DATA_7_H : natural := 23;
constant DATA_8_L : natural := 24;
constant DATA_8_H : natural := 31;
-- DATA_5_8_W register reset values
......@@ -167,14 +167,14 @@ package CAN_FD_frame_format is
-- DATA_61_64_W register
--
------------------------------------------------------------------------------
constant DATA_64_L : natural := 0;
constant DATA_64_H : natural := 7;
constant DATA_63_L : natural := 8;
constant DATA_63_H : natural := 15;
constant DATA_62_L : natural := 16;
constant DATA_62_H : natural := 23;
constant DATA_61_L : natural := 24;
constant DATA_61_H : natural := 31;
constant DATA_61_L : natural := 0;
constant DATA_61_H : natural := 7;
constant DATA_62_L : natural := 8;
constant DATA_62_H : natural := 15;
constant DATA_63_L : natural := 16;
constant DATA_63_H : natural := 23;
constant DATA_64_L : natural := 24;
constant DATA_64_H : natural := 31;
-- DATA_61_64_W register reset values
......
......@@ -107,7 +107,8 @@ package CANconstants is
constant INC_EIGHT_CON : std_logic_vector(2 downto 0) := "010";
constant DEC_ONE_CON : std_logic_vector(2 downto 0) := "001";
constant TXT_BUFFER_COUNT : natural := 4;
-- Common definitions should not be generic at the moment
constant TXT_BUFFER_COUNT : natural := 4;
constant INT_COUNT : natural := 12;
......
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com>
--
-- Project advisors and co-authors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
-- Martin Jerabek <jerabma7@fel.cvut.cz>
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Package with conversion functions of byte endianess.
--------------------------------------------------------------------------------
-- Revision History:
-- 19.5.2018 Created file
--------------------------------------------------------------------------------
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
use work.CAN_FD_frame_format.all;
package endian_swap is
-- Register value to decimal value
function endian_swap_32(
signal input : std_logic_vector
) return std_logic_vector;
end package endian_swap;
package body endian_swap is
function endian_swap_32(
signal input : std_logic_vector
) return std_logic_vector is
begin
if (input'length /= 32) then
report "Invalid input length to endian swap" severity error;
return x"00000000";
else
return input(7 downto 0) &
input(15 downto 8) &
input(23 downto 16) &
input(31 downto 24);
end if;
end function;
end endian_swap;
......@@ -75,6 +75,7 @@ set_parameter -name sup_filtC true
set_parameter -name sup_range true
set_parameter -name tx_time_sup true
set_parameter -name logger_size 64
set_global_assignment -name VHDL_FILE ../../src/endian_swap.vhd
set_global_assignment -name VHDL_FILE ../../src/Buffers_Message_Handling/priorityDecoder.vhd
set_global_assignment -name VHDL_FILE ../../src/Libraries/CANconstants.vhd
set_global_assignment -name VHDL_FILE ../../src/Libraries/CANcomponents.vhd
......
......@@ -391,6 +391,8 @@ package CANtestLib is
end record;
type SW_CAN_data_type is array (0 to 63) of std_logic_vector(7 downto 0);
----------------------------------------------------------------------------
-- Software CAN Frame type. Used for generation, transmission, reception,
-- comparison of CAN Frames.
......@@ -402,7 +404,7 @@ package CANtestLib is
identifier : natural;
-- Data payload
data : std_logic_vector(511 downto 0);
data : SW_CAN_data_type;
-- Data length code as defined in CAN Standard
dlc : std_logic_vector(3 downto 0);
......@@ -1998,13 +2000,13 @@ package body CANtestLib is
)is
variable rand_value : real := 0.0;
variable aux : std_logic_vector(28 downto 0);
variable data_byte : std_logic_vector(7 downto 0);
begin
rand_logic_v(rand_ctr, frame.ident_type, 0.5);
rand_logic_v(rand_ctr, frame.frame_format, 0.5);
rand_logic_v(rand_ctr, frame.rtr, 0.5);
rand_logic_v(rand_ctr, frame.brs, 0.5);
rand_logic_vect_v(rand_ctr, frame.data, 0.5);
rand_logic_vect_v(rand_ctr, frame.dlc, 0.3);
rand_real_v(rand_ctr, rand_value);
......@@ -2037,7 +2039,7 @@ package body CANtestLib is
frame.timestamp := (OTHERS => '0');
if (frame.rtr = RTR_FRAME) then
frame.data := (OTHERS => '0');
frame.data := (OTHERS => (OTHERS => '0'));
frame.dlc := (OTHERS => '0');
frame.data_length := 0;
end if;
......@@ -2049,8 +2051,15 @@ package body CANtestLib is
-- ESI is read only, but is is better to have initialized value in it!
frame.esi := '0';
-- Generate random data
-- Unused bytes of data can be set to 0
frame.data(511 - frame.data_length * 8 downto 0) := (OTHERS => '0');
if (frame.data_length > 0) then
for i in 0 to frame.data_length - 1 loop
rand_logic_vect_v(rand_ctr, data_byte, 0.5);
frame.data(i) := data_byte;
end loop;
end if;
end procedure;
......@@ -2059,6 +2068,7 @@ package body CANtestLib is
constant log_level : in log_lvl_type
)is
variable msg : line;
variable data_byte : std_logic_vector(7 downto 0);
begin
write(msg, string'("CAN Frame:"));
......@@ -2094,9 +2104,14 @@ package body CANtestLib is
write(msg, Integer'image(frame.rwcnt));
-- Data words
if (frame.rtr = NO_RTR_FRAME) then
write(msg, string'(" Data: "));
hwrite(msg, frame.data);
if (frame.rtr = NO_RTR_FRAME and frame.data_length > 0) then
write(msg, string'(" Data: "));
for i in 0 to frame.data_length - 1 loop
data_byte := frame.data(i);
write(msg, string'("0x"));
hwrite(msg, frame.data(i));
write(msg, string'(" "));
end loop;
end if;
writeline(output, msg);
......@@ -2165,10 +2180,8 @@ package body CANtestLib is
if ((frame_A.rtr = NO_RTR_FRAME or frame_A.frame_format = FD_CAN)
and frame_A.data_length /= 0)
then
for i in 0 to (frame_A.data_length - 1) / 4 loop
if (frame_A.data(511 - i * 32 downto 480 - i * 32) /=
frame_B.data(511 - i * 32 downto 480 - i * 32))
then
for i in 0 to (frame_A.data_length - 1) loop
if (frame_A.data(i) /= frame_B.data(i)) then
outcome := false;
end if;
end loop;
......@@ -2250,7 +2263,10 @@ package body CANtestLib is
-- Data words
decode_dlc_v(frame.dlc, length);
for i in 0 to (length - 1) / 4 loop
w_data:= frame.data(511 - i * 32 downto 480 - i * 32);
w_data := frame.data((i * 4) + 3) &
frame.data((i * 4) + 2) &
frame.data((i * 4) + 1) &
frame.data((i * 4));
CAN_write(w_data, std_logic_vector(unsigned(buf_offset) +
unsigned(DATA_1_4_W_ADR) + i * 4),
ID, mem_bus);
......@@ -2299,7 +2315,10 @@ package body CANtestLib is
then
for i in 0 to (frame.data_length - 1) / 4 loop
CAN_read(r_data, RX_DATA_ADR, ID, mem_bus);
frame.data(511 - i * 32 downto 480 - i * 32) := r_data;
frame.data(i * 4) := r_data(7 downto 0);
frame.data((i * 4) + 1) := r_data(15 downto 8);
frame.data((i * 4) + 2) := r_data(23 downto 16);
frame.data((i * 4) + 3) := r_data(31 downto 24);
end loop;
end if;
end procedure;
......
......@@ -367,7 +367,10 @@ architecture behavioral of sanity_test is
(frame.data_length /= 0))
then
for i in 0 to ((frame.data_length - 1) / 4) loop
memory(pointer + i) <= frame.data(511 - i * 32 downto 480 - i * 32);
memory(pointer + i) <= frame.data((i * 4) + 3) &
frame.data((i * 4) + 2) &
frame.data((i * 4) + 1) &
frame.data((i * 4));
wait for 0 ns;
end loop;
......@@ -389,7 +392,7 @@ architecture behavioral of sanity_test is
variable aux_vect : std_logic_vector(28 downto 0);
begin
-- Erase some unnecessary stuff
frame.data := (OTHERS => '0');
frame.data := (OTHERS => (OTHERS => '0'));
frame.identifier := 0;
--Frame format
......@@ -398,7 +401,7 @@ architecture behavioral of sanity_test is
frame.ident_type := memory(mem_index)(pointer)(6);
frame.frame_format := memory(mem_index)(pointer)(7);
frame.brs := memory(mem_index)(pointer)(9);
decode_dlc_v(frame.dlc,frame.data_length);
decode_dlc_v(frame.dlc, frame.data_length);
frame.rwcnt :=
to_integer(unsigned(memory(mem_index)(pointer)(15 downto 11)));
......@@ -431,8 +434,10 @@ architecture behavioral of sanity_test is
frame.data_length /= 0)
then
for i in 0 to ((frame.data_length - 1) / 4) loop
frame.data(511 - i * 32 downto 480 - i * 32) :=
memory(mem_index)(pointer);
frame.data((i * 4) + 3) := memory(mem_index)(pointer)(31 downto 24);
frame.data((i * 4) + 2) := memory(mem_index)(pointer)(23 downto 16);
frame.data((i * 4) + 1) := memory(mem_index)(pointer)(15 downto 8);
frame.data((i * 4)) := memory(mem_index)(pointer)(7 downto 0);
pointer := pointer + 1;
end loop;
end if;
......
......@@ -208,8 +208,10 @@ architecture rx_buf_unit_test of CAN_test is
-- Store the data
if (length > 0) then
for i in 0 to (length - 1) / 4 loop
memory(in_pointer) <= frame.data
(511 - i * 32 downto 480 - i * 32);
memory(in_pointer) <= frame.data((i * 4) + 3) &
frame.data((i * 4) + 2) &
frame.data((i * 4) + 1) &
frame.data((i * 4));
in_pointer <= in_pointer + 1;
wait for 0 ns;
end loop;
......@@ -347,8 +349,10 @@ architecture rx_buf_unit_test of CAN_test is
wait_rand_cycles(rand_ctr, clk_sys, 10, 50);
-- Send signal to store data
store_data_word <= CAN_frame.data(511 - i * 32 downto
480 - i * 32);
store_data_word <= CAN_frame.data((i * 4) + 3) &
CAN_frame.data((i * 4) + 2) &
CAN_frame.data((i * 4) + 1) &
CAN_frame.data((i * 4));
store_data <= '1';
log("Storing data word", info_l, log_level);
......
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