Commit e015bf36 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch '303-block-btr-and-btr_fd-during-operation' into 'master'

Resolve "Block BTR and BTR_FD during operation"

Closes #303

See merge request !303
parents 3f9b25ee 0d41aebc
......@@ -11632,6 +11632,8 @@ Address: 0x24
\begin_layout Description
Size: 4 bytes
\end_layout
\begin_layout Description
Note: Register can be only written when SETTINGS[ENA] = 0, otherwise write has no effect.\end_layout
\begin_layout Standard
Bit Timing Register for nominal bit rate. This register should be modified only when SETTINGS[ENA]=0.
\end_layout
......@@ -12953,6 +12955,8 @@ Address: 0x28
\begin_layout Description
Size: 4 bytes
\end_layout
\begin_layout Description
Note: Register can be only written when SETTINGS[ENA] = 0, otherwise write has no effect.\end_layout
\begin_layout Standard
Bit Timing Register for data bit rate. This register can be modified only when SETTINGS[ENA]=0.
\end_layout
......@@ -39941,6 +39945,8 @@ Address: 0x82
\begin_layout Description
Size: 2 bytes
\end_layout
\begin_layout Description
Note: Register can be only written when SETTINGS[ENA] = 0, otherwise write has no effect.\end_layout
\begin_layout Standard
Secondary Sampling Point configuration register. Used by transmitter in data bit rate for calculation of Secondary Sampling Point. This register should be modified only when SETTINGS[ENA]=0.
\end_layout
Subproject commit ca7524b99d6d43b49a15428d6f9c6aeca6c59437
Subproject commit 4caf19087cc058d1b55bd7f8b107d5e73d167eba
......@@ -3092,10 +3092,12 @@
<kactus2:kts_firmness>Mutable</kactus2:kts_firmness>
</kactus2:kts_attributes>
<ipxact:regLocks>
<ipxact:regLock name="CTR_PRES"/>
<ipxact:regLock name="EWL"/>
<ipxact:regLock name="ERP"/>
<ipxact:Description>Register can be only written when MODE[TSTM] = 1, otherwise write has no effect.</ipxact:Description>
<ipxact:regLock reg_name="CTR_PRES" lock_signal="lock_1" description="Register can be only written when MODE[TSTM] = 1, otherwise write has no effect."/>
<ipxact:regLock reg_name="EWL" lock_signal="lock_1" description="Register can be only written when MODE[TSTM] = 1, otherwise write has no effect."/>
<ipxact:regLock reg_name="ERP" lock_signal="lock_1" description="Register can be only written when MODE[TSTM] = 1, otherwise write has no effect."/>
<ipxact:regLock reg_name="BTR" lock_signal="lock_2" description="Register can be only written when SETTINGS[ENA] = 0, otherwise write has no effect."/>
<ipxact:regLock reg_name="BTR_FD" lock_signal="lock_2" description="Register can be only written when SETTINGS[ENA] = 0, otherwise write has no effect."/>
<ipxact:regLock reg_name="SSP_CFG" lock_signal="lock_2" description="Register can be only written when SETTINGS[ENA] = 0, otherwise write has no effect."/>
</ipxact:regLocks>
<kactus2:license>MIT</kactus2:license>
</ipxact:vendorExtensions>
......
......@@ -4428,7 +4428,8 @@ package can_components is
signal read :in std_logic;
signal write :in std_logic;
signal be :in std_logic_vector(data_width / 8 - 1 downto 0);
signal lock :in std_logic;
signal lock_1 :in std_logic;
signal lock_2 :in std_logic;
signal control_registers_out :out Control_registers_out_t;
signal control_registers_in :in Control_registers_in_t
);
......
......@@ -99,7 +99,7 @@ component memory_reg is
constant reset_polarity : std_logic := '0';
constant reset_value : std_logic_vector;
constant auto_clear : std_logic_vector;
constant is_lockable : std_logic
constant is_lockable : boolean
);
port(
signal clk_sys :in std_logic;
......
......@@ -74,7 +74,8 @@ port (
signal read :in std_logic;
signal write :in std_logic;
signal be :in std_logic_vector(data_width / 8 - 1 downto 0);
signal lock :in std_logic;
signal lock_1 :in std_logic;
signal lock_2 :in std_logic;
signal control_registers_out :out Control_registers_out_t;
signal control_registers_in :in Control_registers_in_t
);
......@@ -122,7 +123,7 @@ begin
reset_polarity => RESET_POLARITY ,
reset_value => "0000000000010000" ,
auto_clear => "0000000000000001" ,
is_lockable => '0'
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
......@@ -131,7 +132,7 @@ begin
write => write ,-- in
cs => reg_sel(1) ,-- in
w_be => be(1 downto 0) ,-- in
lock => lock ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.mode -- out
);
......@@ -146,7 +147,7 @@ begin
reset_polarity => RESET_POLARITY ,
reset_value => "0000000000000000" ,
auto_clear => "0000000000000000" ,
is_lockable => '0'
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
......@@ -155,7 +156,7 @@ begin
write => write ,-- in
cs => reg_sel(1) ,-- in
w_be => be(3 downto 2) ,-- in
lock => lock ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.settings -- out
);
......@@ -170,7 +171,7 @@ begin
reset_polarity => RESET_POLARITY ,
reset_value => "00000000000000000000000000000000" ,
auto_clear => "00000000000000000000000001111100" ,
is_lockable => '0'
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
......@@ -179,7 +180,7 @@ begin
write => write ,-- in
cs => reg_sel(3) ,-- in
w_be => be(3 downto 0) ,-- in
lock => lock ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.command -- out
);
......@@ -194,7 +195,7 @@ begin
reset_polarity => RESET_POLARITY ,
reset_value => "0000000000000000" ,
auto_clear => "0000111111111111" ,
is_lockable => '0'
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
......@@ -203,7 +204,7 @@ begin
write => write ,-- in
cs => reg_sel(4) ,-- in
w_be => be(1 downto 0) ,-- in
lock => lock ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.int_stat -- out
);
......@@ -218,7 +219,7 @@ begin
reset_polarity => RESET_POLARITY ,
reset_value => "0000000000000000" ,
auto_clear => "0000111111111111" ,
is_lockable => '0'
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
......@@ -227,7 +228,7 @@ begin
write => write ,-- in
cs => reg_sel(5) ,-- in
w_be => be(1 downto 0) ,-- in
lock => lock ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.int_ena_set -- out
);
......@@ -242,7 +243,7 @@ begin
reset_polarity => RESET_POLARITY ,
reset_value => "0000000000000000" ,
auto_clear => "0000111111111111" ,
is_lockable => '0'
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
......@@ -251,7 +252,7 @@ begin
write => write ,-- in
cs => reg_sel(6) ,-- in
w_be => be(1 downto 0) ,-- in
lock => lock ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.int_ena_clr -- out
);
......@@ -266,7 +267,7 @@ begin
reset_polarity => RESET_POLARITY ,
reset_value => "0000000000000000" ,
auto_clear => "0000111111111111" ,
is_lockable => '0'
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
......@@ -275,7 +276,7 @@ begin
write => write ,-- in
cs => reg_sel(7) ,-- in
w_be => be(1 downto 0) ,-- in
lock => lock ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.int_mask_set -- out
);
......@@ -290,7 +291,7 @@ begin
reset_polarity => RESET_POLARITY ,
reset_value => "0000000000000000" ,
auto_clear => "0000111111111111" ,
is_lockable => '0'
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
......@@ -299,7 +300,7 @@ begin
write => write ,-- in
cs => reg_sel(8) ,-- in
w_be => be(1 downto 0) ,-- in
lock => lock ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.int_mask_clr -- out
);
......@@ -314,7 +315,7 @@ begin
reset_polarity => RESET_POLARITY ,
reset_value => "00010000010100001010000110000101" ,
auto_clear => "00000000000000000000000000000000" ,
is_lockable => '0'
is_lockable => true
)
port map(
clk_sys => clk_sys ,-- in
......@@ -323,7 +324,7 @@ begin
write => write ,-- in
cs => reg_sel(9) ,-- in
w_be => be(3 downto 0) ,-- in
lock => lock ,-- in
lock => lock_2 ,-- in
reg_value => control_registers_out_i.btr -- out
);
......@@ -338,7 +339,7 @@ begin
reset_polarity => RESET_POLARITY ,
reset_value => "00010000001000000110000110000011" ,
auto_clear => "00000000000000000000000000000000" ,
is_lockable => '0'
is_lockable => true
)
port map(
clk_sys => clk_sys ,-- in
......@@ -347,7 +348,7 @@ begin
write => write ,-- in
cs => reg_sel(10) ,-- in
w_be => be(3 downto 0) ,-- in
lock => lock ,-- in
lock => lock_2 ,-- in
reg_value => control_registers_out_i.btr_fd -- out
);
......@@ -362,7 +363,7 @@ begin
reset_polarity => RESET_POLARITY ,
reset_value => "01100000" ,
auto_clear => "00000000" ,
is_lockable => '1'
is_lockable => true
)
port map(
clk_sys => clk_sys ,-- in
......@@ -371,7 +372,7 @@ begin
write => write ,-- in
cs => reg_sel(11) ,-- in
w_be => be(0 downto 0) ,-- in
lock => lock ,-- in
lock => lock_1 ,-- in
reg_value => control_registers_out_i.ewl -- out
);
......@@ -386,7 +387,7 @@ begin
reset_polarity => RESET_POLARITY ,
reset_value => "10000000" ,
auto_clear => "00000000" ,
is_lockable => '1'
is_lockable => true
)
port map(
clk_sys => clk_sys ,-- in
......@@ -395,7 +396,7 @@ begin
write => write ,-- in
cs => reg_sel(11) ,-- in
w_be => be(1 downto 1) ,-- in
lock => lock ,-- in
lock => lock_1 ,-- in
reg_value => control_registers_out_i.erp -- out
);
......@@ -410,7 +411,7 @@ begin
reset_polarity => RESET_POLARITY ,
reset_value => "00000000000000000000000000000000" ,
auto_clear => "00000000000000000001111111111111" ,
is_lockable => '1'
is_lockable => true
)
port map(
clk_sys => clk_sys ,-- in
......@@ -419,7 +420,7 @@ begin
write => write ,-- in
cs => reg_sel(14) ,-- in
w_be => be(3 downto 0) ,-- in
lock => lock ,-- in
lock => lock_1 ,-- in
reg_value => control_registers_out_i.ctr_pres -- out
);
......@@ -435,7 +436,7 @@ begin
reset_polarity => RESET_POLARITY ,
reset_value => "00000000000000000000000000000000" ,
auto_clear => "00000000000000000000000000000000" ,
is_lockable => '0'
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
......@@ -444,7 +445,7 @@ begin
write => write ,-- in
cs => reg_sel(15) ,-- in
w_be => be(3 downto 0) ,-- in
lock => lock ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.filter_a_mask -- out
);
......@@ -466,7 +467,7 @@ begin
reset_polarity => RESET_POLARITY ,
reset_value => "00000000000000000000000000000000" ,
auto_clear => "00000000000000000000000000000000" ,
is_lockable => '0'
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
......@@ -475,7 +476,7 @@ begin
write => write ,-- in
cs => reg_sel(16) ,-- in
w_be => be(3 downto 0) ,-- in
lock => lock ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.filter_a_val -- out
);
......@@ -497,7 +498,7 @@ begin
reset_polarity => RESET_POLARITY ,
reset_value => "00000000000000000000000000000000" ,
auto_clear => "00000000000000000000000000000000" ,
is_lockable => '0'
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
......@@ -506,7 +507,7 @@ begin
write => write ,-- in
cs => reg_sel(17) ,-- in
w_be => be(3 downto 0) ,-- in
lock => lock ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.filter_b_mask -- out
);
......@@ -528,7 +529,7 @@ begin
reset_polarity => RESET_POLARITY ,
reset_value => "00000000000000000000000000000000" ,
auto_clear => "00000000000000000000000000000000" ,
is_lockable => '0'
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
......@@ -537,7 +538,7 @@ begin
write => write ,-- in
cs => reg_sel(18) ,-- in
w_be => be(3 downto 0) ,-- in
lock => lock ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.filter_b_val -- out
);
......@@ -559,7 +560,7 @@ begin
reset_polarity => RESET_POLARITY ,
reset_value => "00000000000000000000000000000000" ,
auto_clear => "00000000000000000000000000000000" ,
is_lockable => '0'
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
......@@ -568,7 +569,7 @@ begin
write => write ,-- in
cs => reg_sel(19) ,-- in
w_be => be(3 downto 0) ,-- in
lock => lock ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.filter_c_mask -- out
);
......@@ -590,7 +591,7 @@ begin
reset_polarity => RESET_POLARITY ,
reset_value => "00000000000000000000000000000000" ,
auto_clear => "00000000000000000000000000000000" ,
is_lockable => '0'
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
......@@ -599,7 +600,7 @@ begin
write => write ,-- in
cs => reg_sel(20) ,-- in
w_be => be(3 downto 0) ,-- in
lock => lock ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.filter_c_val -- out
);
......@@ -621,7 +622,7 @@ begin
reset_polarity => RESET_POLARITY ,
reset_value => "00000000000000000000000000000000" ,
auto_clear => "00000000000000000000000000000000" ,
is_lockable => '0'
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
......@@ -630,7 +631,7 @@ begin
write => write ,-- in
cs => reg_sel(21) ,-- in
w_be => be(3 downto 0) ,-- in
lock => lock ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.filter_ran_low -- out
);
......@@ -652,7 +653,7 @@ begin
reset_polarity => RESET_POLARITY ,
reset_value => "00000000000000000000000000000000" ,
auto_clear => "00000000000000000000000000000000" ,
is_lockable => '0'
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
......@@ -661,7 +662,7 @@ begin
write => write ,-- in
cs => reg_sel(22) ,-- in
w_be => be(3 downto 0) ,-- in
lock => lock ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.filter_ran_high -- out
);
......@@ -682,7 +683,7 @@ begin
reset_polarity => RESET_POLARITY ,
reset_value => "0000000000001111" ,
auto_clear => "0000000000000000" ,
is_lockable => '0'
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
......@@ -691,7 +692,7 @@ begin
write => write ,-- in
cs => reg_sel(23) ,-- in
w_be => be(1 downto 0) ,-- in
lock => lock ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.filter_control -- out
);
......@@ -706,7 +707,7 @@ begin
reset_polarity => RESET_POLARITY ,
reset_value => "00000000" ,
auto_clear => "00000000" ,
is_lockable => '0'
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
......@@ -715,7 +716,7 @@ begin
write => write ,-- in
cs => reg_sel(26) ,-- in
w_be => be(2 downto 2) ,-- in
lock => lock ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.rx_settings -- out
);
......@@ -754,7 +755,7 @@ begin
reset_polarity => RESET_POLARITY ,
reset_value => "0000000000000000" ,
auto_clear => "0000111100000111" ,
is_lockable => '0'
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
......@@ -763,7 +764,7 @@ begin
write => write ,-- in
cs => reg_sel(29) ,-- in
w_be => be(1 downto 0) ,-- in
lock => lock ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.tx_command -- out
);
......@@ -778,7 +779,7 @@ begin
reset_polarity => RESET_POLARITY ,
reset_value => "0000000000000001" ,
auto_clear => "0000000000000000" ,
is_lockable => '0'
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
......@@ -787,7 +788,7 @@ begin
write => write ,-- in
cs => reg_sel(30) ,-- in
w_be => be(1 downto 0) ,-- in
lock => lock ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.tx_priority -- out
);
......@@ -802,7 +803,7 @@ begin
reset_polarity => RESET_POLARITY ,
reset_value => "0000000000001010" ,
auto_clear => "0000000000000000" ,
is_lockable => '0'
is_lockable => true
)
port map(
clk_sys => clk_sys ,-- in
......@@ -811,7 +812,7 @@ begin
write => write ,-- in
cs => reg_sel(32) ,-- in
w_be => be(3 downto 2) ,-- in
lock => lock ,-- in
lock => lock_2 ,-- in
reg_value => control_registers_out_i.ssp_cfg -- out
);
......
......@@ -84,7 +84,12 @@ entity memory_bus_template is
signal read :in std_logic;
signal write :in std_logic;
signal be :in std_logic_vector(data_width / 8 - 1 downto 0);
signal lock :in std_logic
------------------------------------------------------------------------
-- Lock signals
------------------------------------------------------------------------
signal lock_1 :in std_logic;
signal lock_2 :in std_logic
);
end entity memory_bus_template;
......
......@@ -61,7 +61,7 @@ entity memory_reg is
-- When set to 1, Logic 1 on 'lock' input will prevent register
-- from being written!
constant is_lockable : std_logic
constant is_lockable : boolean
);
port(
------------------------------------------------------------------------
......@@ -125,14 +125,14 @@ begin
------------------------------------------------------------------------
-- Register with write lock
------------------------------------------------------------------------
wr_sel_lock_gen : if (is_lockable = '1') generate
wr_sel_lock_gen : if (is_lockable = true) generate
wr_select(i) <= write and cs and w_be(i) and (not lock);
end generate wr_sel_lock_gen;
------------------------------------------------------------------------
-- Register without write lock
------------------------------------------------------------------------
wr_sel_no_lock_gen : if (is_lockable = '0') generate
wr_sel_no_lock_gen : if (is_lockable = false) generate
wr_select(i) <= write and cs and w_be(i);
end generate wr_sel_no_lock_gen;
......
......@@ -270,8 +270,9 @@ architecture rtl of memory_registers is
-- Internal value of output reset. This is combined res_n and MODE[RST]
signal res_out_i : std_logic;
-- Lock active (inactive only in test mode)
signal reg_lock_active : std_logic;
-- Locks active
signal reg_lock_1_active : std_logic;
signal reg_lock_2_active : std_logic;
-- Soft reset registering
signal soft_res_q : std_logic;
......@@ -406,7 +407,8 @@ begin
read => srd,
write => swr,
be => sbe,
lock => reg_lock_active,
lock_1 => reg_lock_1_active,
lock_2 => reg_lock_2_active,
control_registers_out => control_registers_out,
control_registers_in => control_registers_in
);
......@@ -414,7 +416,8 @@ begin
----------------------------------------------------------------------------
-- Several registers are locked and accessible only in Test mode!
----------------------------------------------------------------------------
reg_lock_active <= not control_registers_out.mode(TSTM_IND);
reg_lock_1_active <= not control_registers_out.mode(TSTM_IND);
reg_lock_2_active <= control_registers_out.settings(ENA_IND mod 16);
----------------------------------------------------------------------------
-- Pipeline on Soft reset register.
......
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018
--
-- Authors:
-- Ondrej Ille <ondrej.ille@gmail.com>
-- Martin Jerabek <martin.jerabek01@gmail.com>
--
-- Project advisors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>