Commit e015bf36 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch '303-block-btr-and-btr_fd-during-operation' into 'master'

Resolve "Block BTR and BTR_FD during operation"

Closes #303

See merge request !303
parents 3f9b25ee 0d41aebc
......@@ -11632,6 +11632,8 @@ Address: 0x24
\begin_layout Description
Size: 4 bytes
\end_layout
\begin_layout Description
Note: Register can be only written when SETTINGS[ENA] = 0, otherwise write has no effect.\end_layout
\begin_layout Standard
Bit Timing Register for nominal bit rate. This register should be modified only when SETTINGS[ENA]=0.
\end_layout
......@@ -12953,6 +12955,8 @@ Address: 0x28
\begin_layout Description
Size: 4 bytes
\end_layout
\begin_layout Description
Note: Register can be only written when SETTINGS[ENA] = 0, otherwise write has no effect.\end_layout
\begin_layout Standard
Bit Timing Register for data bit rate. This register can be modified only when SETTINGS[ENA]=0.
\end_layout
......@@ -39941,6 +39945,8 @@ Address: 0x82
\begin_layout Description
Size: 2 bytes
\end_layout
\begin_layout Description
Note: Register can be only written when SETTINGS[ENA] = 0, otherwise write has no effect.\end_layout
\begin_layout Standard
Secondary Sampling Point configuration register. Used by transmitter in data bit rate for calculation of Secondary Sampling Point. This register should be modified only when SETTINGS[ENA]=0.
\end_layout
Subproject commit ca7524b99d6d43b49a15428d6f9c6aeca6c59437
Subproject commit 4caf19087cc058d1b55bd7f8b107d5e73d167eba
......@@ -3092,10 +3092,12 @@
<kactus2:kts_firmness>Mutable</kactus2:kts_firmness>
</kactus2:kts_attributes>
<ipxact:regLocks>
<ipxact:regLock name="CTR_PRES"/>
<ipxact:regLock name="EWL"/>
<ipxact:regLock name="ERP"/>
<ipxact:Description>Register can be only written when MODE[TSTM] = 1, otherwise write has no effect.</ipxact:Description>
<ipxact:regLock reg_name="CTR_PRES" lock_signal="lock_1" description="Register can be only written when MODE[TSTM] = 1, otherwise write has no effect."/>
<ipxact:regLock reg_name="EWL" lock_signal="lock_1" description="Register can be only written when MODE[TSTM] = 1, otherwise write has no effect."/>
<ipxact:regLock reg_name="ERP" lock_signal="lock_1" description="Register can be only written when MODE[TSTM] = 1, otherwise write has no effect."/>
<ipxact:regLock reg_name="BTR" lock_signal="lock_2" description="Register can be only written when SETTINGS[ENA] = 0, otherwise write has no effect."/>
<ipxact:regLock reg_name="BTR_FD" lock_signal="lock_2" description="Register can be only written when SETTINGS[ENA] = 0, otherwise write has no effect."/>
<ipxact:regLock reg_name="SSP_CFG" lock_signal="lock_2" description="Register can be only written when SETTINGS[ENA] = 0, otherwise write has no effect."/>
</ipxact:regLocks>
<kactus2:license>MIT</kactus2:license>
</ipxact:vendorExtensions>
......
......@@ -4428,7 +4428,8 @@ package can_components is
signal read :in std_logic;
signal write :in std_logic;
signal be :in std_logic_vector(data_width / 8 - 1 downto 0);
signal lock :in std_logic;
signal lock_1 :in std_logic;
signal lock_2 :in std_logic;
signal control_registers_out :out Control_registers_out_t;
signal control_registers_in :in Control_registers_in_t
);
......
......@@ -99,7 +99,7 @@ component memory_reg is
constant reset_polarity : std_logic := '0';
constant reset_value : std_logic_vector;
constant auto_clear : std_logic_vector;
constant is_lockable : std_logic
constant is_lockable : boolean
);
port(
signal clk_sys :in std_logic;
......
......@@ -84,7 +84,12 @@ entity memory_bus_template is
signal read :in std_logic;
signal write :in std_logic;
signal be :in std_logic_vector(data_width / 8 - 1 downto 0);
signal lock :in std_logic
------------------------------------------------------------------------
-- Lock signals
------------------------------------------------------------------------
signal lock_1 :in std_logic;
signal lock_2 :in std_logic
);
end entity memory_bus_template;
......
......@@ -61,7 +61,7 @@ entity memory_reg is
-- When set to 1, Logic 1 on 'lock' input will prevent register
-- from being written!
constant is_lockable : std_logic
constant is_lockable : boolean
);
port(
------------------------------------------------------------------------
......@@ -125,14 +125,14 @@ begin
------------------------------------------------------------------------
-- Register with write lock
------------------------------------------------------------------------
wr_sel_lock_gen : if (is_lockable = '1') generate
wr_sel_lock_gen : if (is_lockable = true) generate
wr_select(i) <= write and cs and w_be(i) and (not lock);
end generate wr_sel_lock_gen;
------------------------------------------------------------------------
-- Register without write lock
------------------------------------------------------------------------
wr_sel_no_lock_gen : if (is_lockable = '0') generate
wr_sel_no_lock_gen : if (is_lockable = false) generate
wr_select(i) <= write and cs and w_be(i);
end generate wr_sel_no_lock_gen;
......
......@@ -270,8 +270,9 @@ architecture rtl of memory_registers is
-- Internal value of output reset. This is combined res_n and MODE[RST]
signal res_out_i : std_logic;
-- Lock active (inactive only in test mode)
signal reg_lock_active : std_logic;
-- Locks active
signal reg_lock_1_active : std_logic;
signal reg_lock_2_active : std_logic;
-- Soft reset registering
signal soft_res_q : std_logic;
......@@ -406,7 +407,8 @@ begin
read => srd,
write => swr,
be => sbe,
lock => reg_lock_active,
lock_1 => reg_lock_1_active,
lock_2 => reg_lock_2_active,
control_registers_out => control_registers_out,
control_registers_in => control_registers_in
);
......@@ -414,7 +416,8 @@ begin
----------------------------------------------------------------------------
-- Several registers are locked and accessible only in Test mode!
----------------------------------------------------------------------------
reg_lock_active <= not control_registers_out.mode(TSTM_IND);
reg_lock_1_active <= not control_registers_out.mode(TSTM_IND);
reg_lock_2_active <= control_registers_out.settings(ENA_IND mod 16);
----------------------------------------------------------------------------
-- Pipeline on Soft reset register.
......
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018
--
-- Authors:
-- Ondrej Ille <ondrej.ille@gmail.com>
-- Martin Jerabek <martin.jerabek01@gmail.com>
--
-- Project advisors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
--
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- BTR, BTR_FD and SSP_CFG register access feature test.
--
-- Verifies:
-- 1. When node is disabled SETTINGS[ENA]='0', BTR, BTR_FD and SSP_CFG registers
-- are not writable. When node is enabled, they are writable!
--
-- Test sequence:
-- 1. Read values in BTR, BTR_FD and SSP_CFG registers. Try to write them,
-- read them back and check that value has not changed! Node 1 is enabled!
-- 2. Disable Node 1 and try to write BTR, BTR_FD and SSP_CFG registers. Read
-- them back and check that value was written!
--------------------------------------------------------------------------------
-- Revision History:
-- 06.12.2019 Created file
--------------------------------------------------------------------------------
context work.ctu_can_synth_context;
context work.ctu_can_test_context;
use lib.pkg_feature_exec_dispath.all;
package btr_ssp_access_feature is
procedure btr_ssp_access_feature_exec(
variable o : out feature_outputs_t;
signal so : out feature_signal_outputs_t;
signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE;
signal iout : in instance_outputs_arr_t;
signal mem_bus : inout mem_bus_arr_t;
signal bus_level : in std_logic
);
end package;
package body btr_ssp_access_feature is
procedure btr_ssp_access_feature_exec(
variable o : out feature_outputs_t;
signal so : out feature_signal_outputs_t;
signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE;
signal iout : in instance_outputs_arr_t;
signal mem_bus : inout mem_bus_arr_t;
signal bus_level : in std_logic
) is
constant ID_1 : natural := 1;
constant ID_2 : natural := 2;
variable CAN_frame : SW_CAN_frame_type;
variable CAN_frame_2 : SW_CAN_frame_type :=
(0, (OTHERS => (OTHERS => '0')), "0000", 0, '0', '0',
'0', '0', '0', (OTHERS => '0'), 0);
variable frame_sent : boolean;
variable frames_equal : boolean;
variable pc_dbg : SW_PC_Debug;
variable btr : std_logic_vector(31 downto 0) :=
(OTHERS => '0');
variable btr_fd : std_logic_vector(31 downto 0) :=
(OTHERS => '0');
variable ssp_cfg : std_logic_vector(31 downto 0) :=
(OTHERS => '0');
variable btr_2 : std_logic_vector(31 downto 0) :=
(OTHERS => '0');
variable btr_fd_2 : std_logic_vector(31 downto 0) :=
(OTHERS => '0');
variable ssp_cfg_2 : std_logic_vector(31 downto 0) :=
(OTHERS => '0');
variable rand_value : std_logic_vector(31 downto 0) :=
(OTHERS => '0');
begin
o.outcome := true;
----------------------------------------------------------------------
-- 1. Read values in BTR, BTR_FD and SSP_CFG registers. Try to write
-- them, read them back and check that value has not changed!
-- Node 1 is enabled!
----------------------------------------------------------------------
info("Step 1");
CAN_read(btr, BTR_ADR, ID_1, mem_bus(1), BIT_32);
CAN_read(btr_fd, BTR_FD_ADR, ID_1, mem_bus(1), BIT_32);
CAN_read(ssp_cfg, SSP_CFG_ADR, ID_1, mem_bus(1), BIT_16);
rand_logic_vect_v(rand_ctr, rand_value, 0.5);
CAN_write(rand_value, BTR_ADR, ID_1, mem_bus(1), BIT_32);
rand_logic_vect_v(rand_ctr, rand_value, 0.5);
CAN_write(rand_value, BTR_FD_ADR, ID_1, mem_bus(1), BIT_32);
rand_logic_vect_v(rand_ctr, rand_value, 0.5);
CAN_write(rand_value, SSP_CFG_ADR, ID_1, mem_bus(1), BIT_16);
CAN_read(btr_2, BTR_ADR, ID_1, mem_bus(1), BIT_32);
CAN_read(btr_fd_2, BTR_FD_ADR, ID_1, mem_bus(1), BIT_32);
CAN_read(ssp_cfg_2, SSP_CFG_ADR, ID_1, mem_bus(1), BIT_16);
check(btr = btr_2, "BTR register not written!");
check(btr_fd = btr_fd_2, "BTR FD register not written!");
check(ssp_cfg = ssp_cfg_2, "SSP_CFG register not written!");
----------------------------------------------------------------------
-- 2. Disable Node 1 and try to write BTR, BTR_FD and SSP_CFG
-- registers. Read them back and check that value was written!
----------------------------------------------------------------------
info("Step 2");
CAN_turn_controller(false, ID_1, mem_bus(1));
CAN_turn_controller(false, ID_2, mem_bus(2));
rand_logic_vect_v(rand_ctr, rand_value, 0.5);
CAN_write(rand_value, BTR_ADR, ID_1, mem_bus(1), BIT_32);
CAN_read(btr, BTR_ADR, ID_1, mem_bus(1), BIT_32);
check(btr = rand_value, "BTR register written!");
rand_logic_vect_v(rand_ctr, rand_value, 0.5);
rand_value(18) := '0';
rand_value(12) := '0';
rand_value(6) := '0'; -- These bits are not implemented!
CAN_write(rand_value, BTR_FD_ADR, ID_1, mem_bus(1), BIT_32);
CAN_read(btr, BTR_FD_ADR, ID_1, mem_bus(1), BIT_32);
check(btr = rand_value, "BTR FD register written!");
rand_logic_vect_v(rand_ctr, rand_value, 0.5);
rand_value(15 downto 0) := (OTHERS => '0');
rand_value(31 downto 26) := (OTHERS => '0');
CAN_write(rand_value, SSP_CFG_ADR, ID_1, mem_bus(1), BIT_16);
CAN_read(btr, SSP_CFG_ADR, ID_1, mem_bus(1), BIT_16);
btr(15 downto 0) := (OTHERS => '0'); -- 16 LSBs are other register!
btr(31 downto 26) := (OTHERS => '0'); -- These are not implemented!
check(btr = rand_value, "SSP CFG register written!");
end procedure;
end package body;
\ No newline at end of file
......@@ -52,6 +52,7 @@ feature:
alc_rtr_r0:
btr:
btr_fd:
btr_ssp_access:
bus_start:
byte_enable:
command_rrb:
......
......@@ -80,6 +80,7 @@ feature:
iterations: 3
btr_fd:
iterations: 3
btr_ssp_access:
bus_start:
byte_enable:
command_rrb:
......
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