diff --git a/scripts/component.xml.j2 b/scripts/component.xml.j2 new file mode 100644 index 0000000000000000000000000000000000000000..c263a502eed722ab98a67c1359f8e089ef296f8c --- /dev/null +++ b/scripts/component.xml.j2 @@ -0,0 +1,642 @@ + + + + user.org + user + CTU_CAN_FD + 1.0 + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_RESET + arstn + + + + + time_quanta_clk + + + + + + + CLK + + + time_quanta_clk + + + + + + irq + + + + + + + INTERRUPT + + + irq + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + s_apb + S_APB + S_APB + + + + + + + PADDR + + + s_apb_paddr + + + + + PPROT + + + s_apb_pprot + + + + + PSEL + + + s_apb_psel + + + + + PENABLE + + + s_apb_penable + + + + + PWRITE + + + s_apb_pwrite + + + + + PWDATA + + + s_apb_pwdata + + + + + PSTRB + + + s_apb_pstrb + + + + + PREADY + + + s_apb_pready + + + + + PRDATA + + + s_apb_prdata + + + + + PSLVERR + + + s_apb_pslverr + + + + + + arstn + + + + + + + RST + + + arstn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + VHDL + CTU_CAN_FD_v1_0 + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + bd93fd12 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + VHDL + CTU_CAN_FD_v1_0 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + bd93fd12 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + aabbb6d4 + + + + + + + aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + arstn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + irq + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + CAN_tx + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + CAN_rx + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + time_quanta_clk + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + timestamp + + in + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_apb_paddr + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_apb_penable + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_apb_pprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_apb_prdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_apb_pready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_apb_psel + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_apb_pslverr + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_apb_pstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_apb_pwdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_apb_pwrite + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + use_logger + Use Logger + true + + + rx_buffer_size + Rx Buffer Size + 128 + + + use_sync + Use Sync + true + + + sup_filtA + Sup Filta + true + + + sup_filtB + Sup Filtb + true + + + sup_filtC + Sup Filtc + true + + + sup_range + Sup Range + true + + + logger_size + Logger Size + 8 + + + + + + choice_list_99a1d2b9 + LEVEL_HIGH + LEVEL_LOW + EDGE_RISING + EDGE_FALLING + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset +{% for file in files %} + + {{file}} + vhdlSource + xil_defaultlib + +{% endfor %} + + + xilinx_anylanguagebehavioralsimulation_view_fileset +{% for file in files %} + + {{file}} + vhdlSource + USED_IN_ipstatic + xil_defaultlib + +{% endfor %} + + + xilinx_xpgui_view_fileset + + xgui/CTU_CAN_FD_v1_0.tcl + tclSource + CHECKSUM_aabbb6d4 + XGUI_VERSION_2 + + + + CTU_CAN_FD_v1_0 + + + use_logger + Use Logger + true + + + rx_buffer_size + Rx Buffer Size + 128 + + + use_sync + Use Sync + true + + + sup_filtA + Sup Filta + true + + + sup_filtB + Sup Filtb + true + + + sup_filtC + Sup Filtc + true + + + sup_range + Sup Range + true + + + logger_size + Logger Size + 8 + + + Component_Name + CTU_CAN_FD_v1_0 + + + + + + zynq + qzynq + azynq + + + /UserIP + + CTU_CAN_FD_v1_0 + package_project + 4 + 2019-01-07T11:37:47Z + + + /home/pi/fpga/zynq/canbech-sw/modules/CTU_CAN_FD/src + + + + 2017.4 + + + + + + + + diff --git a/scripts/gen_vivado_component.py b/scripts/gen_vivado_component.py new file mode 100755 index 0000000000000000000000000000000000000000..84babd39d150b3f8b4fadbad7f4c201513789f68 --- /dev/null +++ b/scripts/gen_vivado_component.py @@ -0,0 +1,26 @@ +#!/usr/bin/python3 +""" +Generate vivado component file in /src/component.xml. + +Serves to update the list of source files -- run when you add/delete/rename +a src vhdl file. +""" + +from jinja2 import Environment, FileSystemLoader, select_autoescape +from pathlib import Path + +d = Path(__file__).parent + +jinja_env = Environment( + loader=FileSystemLoader(str(d)), + autoescape=select_autoescape(['html', 'xml'])) + +template = jinja_env.get_template('component.xml.j2') + +src_dir = d / '..' / 'src' +files = [str(f.relative_to(src_dir)) for f in src_dir.glob('**/*.vhd')] +files = sorted(files) + +contents = template.render(files=files) +with (src_dir / 'component.xml').open('wt', encoding='utf-8') as f: + f.write(contents)