Commit daafc010 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing. Committed by Martin Jeřábek

Updated documentation. Added new PDF versions of pictures.

parent 5f69d043
......@@ -727,7 +727,7 @@ SDC and XDC design constraints for synthesis to Altera and Xilinx FPGAs.
\end_layout
\begin_layout Standard
The CTU_CAN_FD IP core is published under MIT License:
CTU_CAN_FD IP core is published under MIT License:
\end_layout
\begin_layout Quote
......@@ -3998,7 +3998,7 @@ buses
are used:
\series bold
Driving bus
Driving Bus
\series default
(
\family roman
......@@ -4008,7 +4008,7 @@ drv_bus
\shape default
) and
\series bold
Status bus
Status Bus
\series default
(
\family roman
......@@ -4022,7 +4022,7 @@ stat_bus
\end_layout
\begin_layout Subsection
2.4.1 Driving bus
2.4.1 Driving Bus
\end_layout
\begin_layout Standard
......@@ -4030,7 +4030,7 @@ The Driving bus is used to control functionality of every module from user
registers.
It is driven in
\series bold
Memory registers
Memory Registers
\series default
(
\begin_inset CommandInset ref
......@@ -4058,7 +4058,7 @@ signal drv_bus : std_logic_vector(1023 downto 0)
\end_layout
\begin_layout Subsection
2.4.2 Status bus
2.4.2 Status Bus
\end_layout
\begin_layout Standard
......@@ -4522,6 +4522,13 @@ name "fig:IP-function-block"
\end_inset
\end_layout
\begin_layout Standard
\begin_inset Newpage pagebreak
\end_inset
\end_layout
\begin_layout Section
......@@ -4626,6 +4633,13 @@ name "fig:Pipeline-Architecture"
\end_inset
\end_layout
\begin_layout Standard
\begin_inset Newpage pagebreak
\end_inset
\end_layout
\begin_layout Section
......@@ -4851,7 +4865,7 @@ name "fig:CAN-Core-block"
\end_layout
\begin_layout Subsubsection
2.5.1.1 Protocol control
2.5.1.1 Protocol Control
\end_layout
\begin_layout Description
......@@ -4954,9 +4968,53 @@ reference "fig:PC_control-1"
For simplicity only main state transitions are displayed!
\end_layout
\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open
\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
filename ../pics/Visio_generated/FSM_protocol_control.pdf
lyxscale 20
scale 130
\end_inset
\end_layout
\begin_layout Plain Layout
\begin_inset Caption Standard
\begin_layout Plain Layout
Protocol Control State Machine
\begin_inset CommandInset label
LatexCommand label
name "fig:PC_control-1"
\end_inset
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
\begin_inset Float table
placement h
placement H
wide false
sideways false
status open
......@@ -6281,44 +6339,7 @@ name "tab: PC_most_important_signals"
\end_layout
\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open
\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
filename ../pics/Visio_generated/FSM_protocol_control.pdf
lyxscale 20
scale 130
\end_inset
\end_layout
\begin_layout Plain Layout
\begin_inset Caption Standard
\begin_layout Plain Layout
Protocol Control State Machine
\begin_inset CommandInset label
LatexCommand label
name "fig:PC_control-1"
\end_inset
\end_layout
\end_inset
\end_layout
\begin_inset Newpage pagebreak
\end_inset
......@@ -7221,6 +7242,50 @@ interframe
\shape default
.
\end_layout
\begin_layout Standard
\begin_inset Float figure
placement h
wide false
sideways false
status open
\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
filename ../pics/Visio_generated/FSM_Interframe.pdf
lyxscale 20
scale 130
\end_inset
\end_layout
\begin_layout Plain Layout
\begin_inset Caption Standard
\begin_layout Plain Layout
Interframe State Machine
\begin_inset CommandInset label
LatexCommand label
name "fig:Interframe-FSM-1"
\end_inset
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Paragraph*
......@@ -7360,50 +7425,6 @@ sof
.
\end_layout
\begin_layout Standard
\begin_inset Float figure
placement h
wide false
sideways false
status open
\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
filename ../pics/Visio_generated/FSM_Interframe.pdf
lyxscale 20
scale 130
\end_inset
\end_layout
\begin_layout Plain Layout
\begin_inset Caption Standard
\begin_layout Plain Layout
Interframe State Machine
\begin_inset CommandInset label
LatexCommand label
name "fig:Interframe-FSM-1"
\end_inset
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Paragraph*
error
\end_layout
......@@ -7495,122 +7516,34 @@ interframe
.
\end_layout
\begin_layout Paragraph*
overload
\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open
\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
filename ../pics/Visio_generated/FSM_Error.pdf
lyxscale 20
scale 130
\end_inset
\end_layout
\begin_layout Standard
Upon detection of Overload Condition, Protocol Control state is updated
to
\family roman
\shape italic
overload
\family default
\shape default
.
Logic of this state is formally very similar to state
\family roman
\shape italic
error
\family default
\shape default
.
This state consists of sub-FSM
\family roman
\shape italic
ovr_frame_state
\family default
\shape default
which is displayed in Figure
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:Overload-Frame-FSM-1-1"
plural "false"
caps "false"
noprefix "false"
\end_inset
.
FSM is started from
\family roman
\shape italic
ovr_flg_sup
\family default
\shape default
, which represent Overload Delimiter.
Duration of state is cotrolled via
\family roman
\shape italic
control_pointer
\family default
\shape default
.
Upon detection of 14 consecutive Dominant bits, Protocol Control is updated
to
\family roman
\shape italic
error
\family default
\shape default
.
Upon reception of Recessive bit,
\family roman
\shape italic
ovr_frame_state
\family default
\shape default
is updated to
\family roman
\shape italic
ovr_delim
\family default
\shape default
.
Overload Delimiter consists of 8 Recessive bits.
Upon expiration of
\family roman
\shape italic
control_pointer
\family default
\shape default
, Protocol Control is moved to
\family roman
\shape italic
interframe
\family default
\shape default
.
\end_layout
\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open
\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
filename ../pics/Visio_generated/FSM_Error.pdf
lyxscale 20
scale 130
\end_inset
\end_layout
\begin_layout Plain Layout
\begin_inset Caption Standard
\begin_layout Plain Layout
Error Frame State Machine
\begin_inset CommandInset label
LatexCommand label
name "fig:Error-Frame-FSM-1"
\begin_layout Plain Layout
\begin_inset Caption Standard
\begin_layout Plain Layout
Error Frame State Machine
\begin_inset CommandInset label
LatexCommand label
name "fig:Error-Frame-FSM-1"
\end_inset
......@@ -7669,6 +7602,101 @@ name "fig:Overload-Frame-FSM-1-1"
\end_inset
\end_layout
\begin_layout Paragraph*
overload
\end_layout
\begin_layout Standard
Upon detection of Overload Condition, Protocol Control state is updated
to
\family roman
\shape italic
overload
\family default
\shape default
.
Logic of this state is formally very similar to state
\family roman
\shape italic
error
\family default
\shape default
.
This state consists of sub-FSM
\family roman
\shape italic
ovr_frame_state
\family default
\shape default
which is displayed in Figure
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:Overload-Frame-FSM-1-1"
plural "false"
caps "false"
noprefix "false"
\end_inset
.
FSM is started from
\family roman
\shape italic
ovr_flg_sup
\family default
\shape default
, which represent Overload Delimiter.
Duration of state is cotrolled via
\family roman
\shape italic
control_pointer
\family default
\shape default
.
Upon detection of 14 consecutive Dominant bits, Protocol Control is updated
to
\family roman
\shape italic
error
\family default
\shape default
.
Upon reception of Recessive bit,
\family roman
\shape italic
ovr_frame_state
\family default
\shape default
is updated to
\family roman
\shape italic
ovr_delim
\family default
\shape default
.
Overload Delimiter consists of 8 Recessive bits.
Upon expiration of
\family roman
\shape italic
control_pointer
\family default
\shape default
, Protocol Control is moved to
\family roman
\shape italic
interframe
\family default
\shape default
.
\end_layout
\begin_layout Standard
\begin_inset Newpage pagebreak
\end_inset
\end_layout
\begin_layout Subsubsection
......@@ -7854,6 +7882,13 @@ name "fig:OP_control"
\end_inset
\end_layout
\begin_layout Standard
\begin_inset Newpage pagebreak
\end_inset
\end_layout
\begin_layout Subsubsection
......@@ -7880,7 +7915,7 @@ faultConf
\end_layout
\begin_layout Standard
Fault confinement module implements Fault confinement state (
Fault confinement module implements Fault Confinement state (
\family roman
\shape italic
error_state
......@@ -7899,7 +7934,17 @@ rx_counter
\family default
\shape default
), Bit error and Stuff error validation.
Block diagram of this module is shown in Figure TODO.
Block diagram of this module is shown in Figure
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:Fault-block-diagram"
plural "false"
caps "false"
noprefix "false"
\end_inset
.
Error counters for Fault confinement (
\family roman
\shape italic
......@@ -7938,7 +7983,7 @@ literal "true"
\end_inset
(Fault Confinement chapter) are managed by Protocol Control FSM.
(Fault Confinement Chapter) are managed by Protocol Control FSM.
These error counters are implemented to be read / write (via Driving Bus,
signals
\family roman
......@@ -8010,8 +8055,14 @@ counter is incremented.
cons_128_11_rec_ctr
\family default
\shape default
reaches 127, reset_err_counters is set, Error counters are set to 0 and
both Fault confinement state is set to
reaches 127,
\family roman
\shape italic
reset_err_counters
\family default
\shape default
is set, Error counters are set to 0 and both Fault confinement state is
set to
\family roman
\shape italic
error_active
......@@ -8020,96 +8071,63 @@ error_active
.
\end_layout
\begin_layout Subsubsection
2.5.1.4 Bit stuffing
\end_layout
\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open
\begin_layout Description
File bitStuffing.vhd
\end_layout
\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
filename ../pics/Visio_generated/Fault_State_Block_diagram.pdf
lyxscale 20
scale 70
\begin_layout Description
Used
\begin_inset space ~
\end_inset
in core_top.vhd
\end_layout
\begin_layout Description
Entity bitStuffing
\end_layout
\begin_layout Standard
Bit stuffing module implements functionality stuff bit insertion into a
serial data stream.
The number of equal consecutive bits is variable (
\begin_inset Quotes eld
\end_inset
\begin_layout Plain Layout
\begin_inset Caption Standard
stuff_length
\begin_inset Quotes erd
\end_inset
\begin_layout Plain Layout