Commit d412b32f authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Re-organized src folder structure. Renamed files to follow

the same naming rules.
parent 8ac7e419
# ** Error: (vish-3296) Unknown option '--help'.
# Use the -help option for complete vsim usage.
......@@ -156,8 +156,9 @@ entity CAN_top_level is
-------------------------------------------
signal timestamp : in std_logic_vector(63 downto 0)
);
end entity CAN_top_level;
architecture rtl of CAN_top_level is
----------------------------------------------------------------------------
----------------------------------------------------------------------------
......@@ -468,23 +469,19 @@ entity CAN_top_level is
-- Transceiver delay output
signal trv_delay_out : std_logic_vector(15 downto 0);
end entity CAN_top_level;
architecture rtl of CAN_top_level is
----------------------------------------------------------------------------
-- Defining explicit architectures for used entites
----------------------------------------------------------------------------
for reg_comp : canfd_registers use entity work.canfd_registers(rtl);
for rx_buf_comp : rx_buffer use entity work.rx_buffer(rtl);
for tx_arb_comp : txArbitrator use entity work.txArbitrator(rtl);
for mes_filt_comp : messageFilter use entity work.messageFilter(rtl);
for int_man_comp : intManager use entity work.intManager(rtl);
for core_top_comp : core_top use entity work.core_top(rtl);
for prescaler_comp : prescaler_v3 use entity work.prescaler_v3(rtl);
for bus_sync_comp : busSync use entity work.busSync(rtl);
for memory_registers_comp : memory_registers use entity work.memory_registers(rtl);
for rx_buffer_comp : rx_buffer use entity work.rx_buffer(rtl);
for tx_arbitrator_comp : tx_arbitrator use entity work.tx_arbitrator(rtl);
for frame_filters_comp : frame_filters use entity work.frame_filters(rtl);
for int_manager_comp : int_manager use entity work.int_manager(rtl);
for can_core_comp : can_core use entity work.can_core(rtl);
for prescaler_comp : prescaler use entity work.prescaler(rtl);
for bus_sampling_comp : bus_sampling use entity work.bus_sampling(rtl);
for rst_sync_comp : rst_sync use entity work.rst_sync(rtl);
--for log_comp : CAN_logger use entity work.CAN_logger(rtl);
begin
......@@ -503,7 +500,7 @@ begin
rst => res_n_sync
);
reg_comp : canfd_registers
memory_registers_comp : memory_registers
generic map(
compType => CAN_COMPONENT_TYPE,
use_logger => use_logger,
......@@ -559,7 +556,7 @@ begin
);
rx_buf_comp : rx_buffer
rx_buffer_comp : rx_buffer
generic map(
buff_size => rx_buffer_size
)
......@@ -596,9 +593,8 @@ begin
txt_buf_comp_gen : for i in 0 to TXT_BUFFER_COUNT - 1 generate
txtBuffer_comp : txtBuffer
txt_buffer_comp : txt_buffer
generic map(
buf_count => TXT_BUFFER_COUNT,
ID => i
......@@ -623,7 +619,7 @@ begin
end generate;
tx_arb_comp : txArbitrator
tx_arbitrator_comp : tx_arbitrator
generic map(
buf_count => TXT_BUFFER_COUNT
)
......@@ -649,7 +645,7 @@ begin
timestamp => timestamp
);
mes_filt_comp : messageFilter
frame_filters_comp : frame_filters
generic map(
sup_filtA => sup_filtA,
sup_filtB => sup_filtB,
......@@ -683,7 +679,7 @@ begin
rx_store_data_valid <= rx_store_data and out_ident_valid;
rec_message_store <= rec_message_valid and out_ident_valid;
int_man_comp : intManager
int_manager_comp : int_manager
generic map(
int_count => INT_COUNT
)
......@@ -709,7 +705,7 @@ begin
int_mask => int_mask
);
core_top_comp : core_top
can_core_comp : can_core
port map(
clk_sys => clk_sys,
res_n => res_n_int,
......@@ -769,7 +765,7 @@ begin
sof_pulse => sof_pulse
);
prescaler_comp : prescaler_v3
prescaler_comp : prescaler
port map(
clk_sys => clk_sys,
res_n => res_n_int,
......@@ -795,7 +791,7 @@ begin
sync_control => sync_control
);
bus_sync_comp : busSync
bus_sampling_comp : bus_sampling
generic map (
use_Sync => use_sync
)
......@@ -826,8 +822,8 @@ begin
);
LOG_GEN : if (use_logger) generate
log_comp : CAN_logger
event_logger_gen_true : if (use_logger) generate
event_logger_comp : event_logger
generic map(
memory_size => logger_size
)
......@@ -849,16 +845,16 @@ begin
bt_FSM => bt_FSM_out,
data_overrun => rx_data_overrun
);
end generate LOG_GEN;
end generate event_logger_gen_true;
LOG_GEN2 : if (use_logger = false) generate
event_logger_gen_false : if (not use_logger) generate
loger_finished <= '0';
loger_act_data <= (others => '0');
log_write_pointer <= (others => '0');
log_read_pointer <= (others => '0');
log_size <= (others => '0');
log_state_out <= config;
end generate LOG_GEN2;
end generate event_logger_gen_false;
--Bit time clock output propagation
time_quanta_clk <= clk_tq_nbt when sp_control = NOMINAL_SAMPLE else
......
......@@ -114,7 +114,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- Registers
----------------------------------------------------------------------------
component canfd_registers is
component memory_registers is
generic(
constant compType : std_logic_vector(3 downto 0) := CAN_COMPONENT_TYPE;
constant use_logger : boolean := true;
......@@ -362,7 +362,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- TXT Buffer module
----------------------------------------------------------------------------
component txtBuffer is
component txt_buffer is
generic(
constant buf_count : natural range 1 to 8;
constant ID : natural := 1
......@@ -392,7 +392,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- TXT Buffer FSM
----------------------------------------------------------------------------
component txtBuffer_fsm is
component txt_buffer_fsm is
generic(
constant ID : natural
);
......@@ -414,7 +414,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- TXT Arbitrator module
----------------------------------------------------------------------------
component txArbitrator is
component tx_arbitrator is
generic(
constant buf_count : natural range 1 to 8
);
......@@ -446,7 +446,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- Priority decoder for TXT Buffer selection
----------------------------------------------------------------------------
component priorityDecoder is
component priority_decoder is
generic(
constant buf_count : natural range 1 to 8
);
......@@ -463,7 +463,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- TX Arbitrator FSM
----------------------------------------------------------------------------
component txArbitrator_fsm is
component tx_arbitrator_fsm is
port(
signal clk_sys :in std_logic;
signal res_n :in std_logic;
......@@ -487,9 +487,9 @@ package CANcomponents is
----------------------------------------------------------------------------
-- Message filter module
-- Frame filters module
----------------------------------------------------------------------------
component messageFilter is
component frame_filters is
generic(
constant sup_filtA : boolean := true;
constant sup_filtB : boolean := true;
......@@ -512,7 +512,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- Generic Bit Filter
----------------------------------------------------------------------------
component bitFilter is
component bit_filter is
generic(
constant width : natural;
constant is_present : boolean
......@@ -530,7 +530,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- Range filter
----------------------------------------------------------------------------
component rangeFilter is
component range_filter is
generic(
constant width : natural;
constant is_present : boolean
......@@ -548,7 +548,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- Interrupt manager module
----------------------------------------------------------------------------
component intManager is
component int_manager is
generic(
constant int_count : natural range 0 to 32 := 11
);
......@@ -614,7 +614,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- CAN Core module
----------------------------------------------------------------------------
component core_top is
component can_core is
port(
signal clk_sys : in std_logic;
signal res_n : in std_logic;
......@@ -679,7 +679,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- Prescaler module
----------------------------------------------------------------------------
component prescaler_v3 is
component prescaler is
port(
signal clk_sys : in std_logic;
signal res_n : in std_logic;
......@@ -708,9 +708,9 @@ package CANcomponents is
----------------------------------------------------------------------------
-- Bus synchroniser module
-- Bus Sampling module
----------------------------------------------------------------------------
component busSync is
component bus_sampling is
generic (
use_Sync : boolean
);
......@@ -739,9 +739,9 @@ package CANcomponents is
----------------------------------------------------------------------------
-- CAN Logger module
-- Event Logger module
----------------------------------------------------------------------------
component CAN_logger is
component event_logger is
generic(
constant memory_size : natural := 16
);
......@@ -773,7 +773,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- CAN CRC module
----------------------------------------------------------------------------
component canCRC is
component can_crc is
generic(
constant crc15_pol : std_logic_vector(15 downto 0) := x"C599";
constant crc17_pol : std_logic_vector(19 downto 0) := x"3685B";
......@@ -796,7 +796,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- Generic CRC calculation module
----------------------------------------------------------------------------
component CRC_calc is
component crc_calc is
generic(
constant crc_width : natural;
constant reset_polarity : std_logic := '0';
......@@ -817,7 +817,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- Bit Stuffing
----------------------------------------------------------------------------
component bitStuffing_v2 is
component bit_stuffing is
port(
signal clk_sys : in std_logic;
signal res_n : in std_logic;
......@@ -836,7 +836,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- Bit Destuffing
----------------------------------------------------------------------------
component bitDestuffing is
component bit_destuffing is
port(
signal clk_sys : in std_logic;
signal res_n : in std_logic;
......@@ -855,9 +855,9 @@ package CANcomponents is
----------------------------------------------------------------------------
-- Operation control FSM
-- Operation control module
----------------------------------------------------------------------------
component operationControl is
component operation_control is
port(
signal clk_sys : in std_logic;
signal res_n : in std_logic;
......@@ -878,9 +878,9 @@ package CANcomponents is
----------------------------------------------------------------------------
-- Protocol Control FSM
-- Protocol Control module
----------------------------------------------------------------------------
component protocolControl is
component protocol_control is
port(
signal clk_sys : in std_logic;
signal res_n : in std_logic;
......@@ -958,7 +958,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- Fault confinement
----------------------------------------------------------------------------
component faultConf is
component fault_confinement is
port(
signal clk_sys : in std_logic;
signal res_n : in std_logic;
......
......@@ -95,7 +95,7 @@ USE WORK.CANconstants.ALL;
use work.CAN_FD_register_map.all;
use work.cmn_lib.all;
entity busSync is
entity bus_sampling is
GENERIC (
------------------------------------------------------------------------
......@@ -183,7 +183,7 @@ entity busSync is
end entity;
architecture rtl of busSync is
architecture rtl of bus_sampling is
-----------------------------------------------------------------------------
......
......@@ -79,7 +79,7 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use WORK.CANconstants.all;
entity bitDestuffing is
entity bit_destuffing is
port(
------------------------------------------------------------------------
-- Clock And Reset
......@@ -131,6 +131,9 @@ entity bitDestuffing is
-- Number of destuffed bits with regular bit stuffing method
signal dst_ctr : out natural range 0 to 7
);
end entity;
architecture rtl of bit_destuffing is
----------------------------------------------------------------------------
--Internal signals and registers
......@@ -150,9 +153,6 @@ entity bitDestuffing is
-- Note: Number of stuffed, destuffed bits is transmitted modulo 8. Thus
-- only 3 bits counter is enough!!
end entity;
architecture rtl of bitDestuffing is
begin
----------------------------------------------------------------------------
......
......@@ -77,7 +77,7 @@ USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE WORK.CANconstants.ALL;
entity bitStuffing_v2 is
entity bit_stuffing is
port(
------------------------------------------------------------------------
......@@ -124,6 +124,10 @@ entity bitStuffing_v2 is
-- fed back to CAN Core for CRC calculation in CAN FD Phase!
);
end entity;
architecture rtl of bit_stuffing is
----------------------------------------------------------------------------
-- Internal Registers
......@@ -144,10 +148,6 @@ entity bitStuffing_v2 is
signal stuff_ctr : natural range 0 to 7;
signal enable_prev : std_logic;
end entity;
architecture rtl of bitStuffing_v2 is
begin
bst_ctr <= stuff_ctr;
......
......@@ -93,7 +93,7 @@ use work.CANcomponents.ALL;
use work.CAN_FD_frame_format.ALL;
use work.CAN_FD_frame_format.all;
entity core_top is
entity can_core is
port(
------------------------------------------------------------------------
-- System clock and Reset
......@@ -280,6 +280,10 @@ entity core_top is
signal sof_pulse :out std_logic
);
end entity;
architecture rtl of can_core is
----------------------------------------------------------------------------
-- Driving bus aliases
......@@ -524,37 +528,34 @@ entity core_top is
-- Signals start of frame to rest of the design
signal sof_pulse_r : std_logic;
end entity;
architecture rtl of core_top is
for OP_State_comp : operationControl
use entity work.operationControl(rtl);
for operation_control_comp : operation_control
use entity work.operation_control(rtl);
for PC_State_comp : protocolControl
use entity work.protocolControl(rtl);
for protocol_control_comp : protocol_control
use entity work.protocol_control(rtl);
for faultConf_comp : faultConf
use entity work.faultConf(rtl);
for fault_confinement_comp : fault_confinement
use entity work.fault_confinement(rtl);
for crc_wbs_rx_comp : canCRC
use entity work.canCRC(rtl);
for crc_wbs_rx_comp : can_crc
use entity work.can_crc(rtl);
for crc_nbs_rx_comp : canCRC
use entity work.canCRC(rtl);
for crc_nbs_rx_comp : can_crc
use entity work.can_crc(rtl);
for crc_wbs_tx_comp : canCRC
use entity work.canCRC(rtl);
for crc_wbs_tx_comp : can_crc
use entity work.can_crc(rtl);
for crc_nbs_tx_comp : canCRC
use entity work.canCRC(rtl);
for crc_nbs_tx_comp : can_crc
use entity work.can_crc(rtl);
for bs_comp : bitStuffing_v2
use entity work.bitStuffing_v2(rtl);
for bit_stuffing_comp : bit_stuffing
use entity work.bit_stuffing(rtl);
for bitDest_comp : bitDestuffing
use entity work.bitDestuffing(rtl);
for bit_destuffing_comp : bit_destuffing
use entity work.bit_destuffing(rtl);
begin
......@@ -587,7 +588,7 @@ begin
----------------------------------------------------------------------------
-- Operation control state machine
----------------------------------------------------------------------------
OP_State_comp : operationControl
operation_control_comp : operation_control
port map(
clk_sys => clk_sys,
res_n => res_n,
......@@ -607,9 +608,9 @@ begin
----------------------------------------------------------------------------
-- Protocol control state machine
-- Protocol control module
----------------------------------------------------------------------------
PC_State_comp : protocolControl
protocol_control_comp : protocol_control
port map(
clk_sys => clk_sys,
res_n => res_n,
......@@ -707,7 +708,7 @@ begin
----------------------------------------------------------------------------
-- Fault confinement
----------------------------------------------------------------------------
faultConf_comp : faultConf
fault_confinement_comp : fault_confinement
port map(
clk_sys => clk_sys,
res_n => res_n,
......@@ -758,7 +759,7 @@ begin
----------------------------------------------------------------------------
-- CRC with bit stuffing from RX Data
----------------------------------------------------------------------------
crc_wbs_rx_comp : canCRC
crc_wbs_rx_comp : can_crc
generic map(
crc15_pol => CRC15_POL,
crc17_pol => CRC17_POL,
......@@ -780,7 +781,7 @@ begin
----------------------------------------------------------------------------
-- CRC no bit stuffing from RX Data
----------------------------------------------------------------------------
crc_nbs_rx_comp : canCRC
crc_nbs_rx_comp : can_crc
generic map(
crc15_pol => CRC15_POL,
crc17_pol => CRC17_POL,
......@@ -802,7 +803,7 @@ begin
----------------------------------------------------------------------------
-- CRC with bit stuffing from TX Data
----------------------------------------------------------------------------
crc_wbs_tx_comp : canCRC
crc_wbs_tx_comp : can_crc
generic map(
crc15_pol => CRC15_POL,
crc17_pol => CRC17_POL,
......@@ -824,7 +825,7 @@ begin
----------------------------------------------------------------------------
-- CRC no bit stuffing from TX Data
----------------------------------------------------------------------------
crc_nbs_tx_comp : canCRC
crc_nbs_tx_comp : can_crc
generic map(
crc15_pol => CRC15_POL,
crc17_pol => CRC17_POL,
......@@ -850,7 +851,7 @@ begin
----------------------------------------------------------------------------
-- Bit Stuffing
----------------------------------------------------------------------------
bs_comp : bitStuffing_v2
bit_stuffing_comp : bit_stuffing
port map(
clk_sys => clk_sys,
res_n => res_n,
......@@ -868,7 +869,7 @@ begin
----------------------------------------------------------------------------
-- Bit De-Stuffing
----------------------------------------------------------------------------
bitDest_comp : bitDestuffing
bit_destuffing_comp : bit_destuffing
port map(
clk_sys => clk_sys,
res_n => res_n,
......
......@@ -71,7 +71,7 @@ use work.CAN_FD_register_map.all;
use work.CANcomponents.all;
entity canCRC is
entity can_crc is
generic(
constant crc15_pol : std_logic_vector(15 downto 0) := x"C599";
constant crc17_pol : std_logic_vector(19 downto 0) := x"3685B";
......@@ -116,7 +116,7 @@ entity canCRC is
end entity;
architecture rtl of canCRC is
architecture rtl of can_crc is
-- ISO CAN FD or NON ISO CAN FD Value
signal drv_fd_type : std_logic;
......@@ -149,7 +149,7 @@ begin
----------------------------------------------------------------------------
-- CRC instances
----------------------------------------------------------------------------
crc_15_comp : CRC_calc
crc_calc_15_comp : crc_calc
generic map(
crc_width => 15,
reset_polarity => ACT_RESET,
......@@ -166,7 +166,7 @@ begin
crc => crc15
);
crc_17_comp : CRC_calc
crc_calc_17_comp : crc_calc
generic map(
crc_width => 17,
reset_polarity => ACT_RESET,
......@@ -183,7 +183,7 @@ begin
crc => crc17
);
crc_21_comp : CRC_calc
crc_calc_21_comp : crc_calc
generic map(
crc_width => 21,
reset_polarity => ACT_RESET,
......
......@@ -59,7 +59,7 @@ USE IEEE.numeric_std.ALL;
use work.CANconstants.all;
use work.CAN_FD_register_map.all;
entity CRC_calc is
entity crc_calc is
generic(
-- Width of CRC sequence
......@@ -106,7 +106,7 @@ entity CRC_calc is
end entity;
architecture rtl of CRC_calc is <