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C
CTU CAN FD IP Core
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canbus
CTU CAN FD IP Core
Commits
d412b32f
Commit
d412b32f
authored
Dec 20, 2018
by
Ille, Ondrej, Ing.
Browse files
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Plain Diff
Re-organized src folder structure. Renamed files to follow
the same naming rules.
parent
8ac7e419
Changes
51
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51 changed files
with
327 additions
and
332 deletions
+327
-332
src/CAN_Core/transcript
src/CAN_Core/transcript
+0
-2
src/CAN_top_level.vhd
src/CAN_top_level.vhd
+25
-29
src/Libraries/CANcomponents.vhd
src/Libraries/CANcomponents.vhd
+26
-26
src/apb/apb_ifc.vhd
src/apb/apb_ifc.vhd
+0
-0
src/bus_sampling/bus_sampling.vhd
src/bus_sampling/bus_sampling.vhd
+2
-2
src/can_core/bit_destuffing/bit_destuffing.vhd
src/can_core/bit_destuffing/bit_destuffing.vhd
+4
-4
src/can_core/bit_stuffing/bit_stuffing.vhd
src/can_core/bit_stuffing/bit_stuffing.vhd
+5
-5
src/can_core/can_core.vhd
src/can_core/can_core.vhd
+33
-32
src/can_core/crc/can_crc.vhd
src/can_core/crc/can_crc.vhd
+5
-5
src/can_core/crc/crc_calc.vhd
src/can_core/crc/crc_calc.vhd
+2
-2
src/can_core/fault_confinement/fault_confinement.vhd
src/can_core/fault_confinement/fault_confinement.vhd
+5
-4
src/can_core/operation_control/operation_control.vhd
src/can_core/operation_control/operation_control.vhd
+2
-2
src/can_core/protocol_control/protocol_control.vhd
src/can_core/protocol_control/protocol_control.vhd
+2
-2
src/common/inf_RAM_wrapper.vhd
src/common/inf_RAM_wrapper.vhd
+0
-0
src/event_logger/event_logger.vhd
src/event_logger/event_logger.vhd
+5
-4
src/frame_filters/bit_filter.vhd
src/frame_filters/bit_filter.vhd
+2
-2
src/frame_filters/frame_filters.vhd
src/frame_filters/frame_filters.vhd
+8
-8
src/frame_filters/range_filter.vhd
src/frame_filters/range_filter.vhd
+2
-2
src/interrupts/int_manager.vhd
src/interrupts/int_manager.vhd
+5
-5
src/interrupts/int_module.vhd
src/interrupts/int_module.vhd
+0
-0
src/memory_registers/generated/access_signaler.vhd
src/memory_registers/generated/access_signaler.vhd
+0
-0
src/memory_registers/generated/address_decoder.vhd
src/memory_registers/generated/address_decoder.vhd
+0
-0
src/memory_registers/generated/can_registers_pkg.vhd
src/memory_registers/generated/can_registers_pkg.vhd
+0
-0
src/memory_registers/generated/cmn_reg_map_pkg.vhd
src/memory_registers/generated/cmn_reg_map_pkg.vhd
+0
-0
src/memory_registers/generated/control_registers_reg_map.vhd
src/memory_registers/generated/control_registers_reg_map.vhd
+0
-0
src/memory_registers/generated/data_mux.vhd
src/memory_registers/generated/data_mux.vhd
+0
-0
src/memory_registers/generated/event_logger_reg_map.vhd
src/memory_registers/generated/event_logger_reg_map.vhd
+0
-0
src/memory_registers/generated/memory_bus.vhd
src/memory_registers/generated/memory_bus.vhd
+0
-0
src/memory_registers/generated/memory_reg.vhd
src/memory_registers/generated/memory_reg.vhd
+0
-0
src/memory_registers/memory_registers.vhd
src/memory_registers/memory_registers.vhd
+2
-2
src/prescaler/prescaler.vhd
src/prescaler/prescaler.vhd
+164
-166
src/rx_buffer/rx_buffer.vhd
src/rx_buffer/rx_buffer.vhd
+0
-0
src/rx_buffer/rx_buffer_fsm.vhd
src/rx_buffer/rx_buffer_fsm.vhd
+0
-0
src/rx_buffer/rx_buffer_pointers.vhd
src/rx_buffer/rx_buffer_pointers.vhd
+0
-0
src/tx_arbitrator/priority_decoder.vhd
src/tx_arbitrator/priority_decoder.vhd
+2
-2
src/tx_arbitrator/tx_arbitrator.vhd
src/tx_arbitrator/tx_arbitrator.vhd
+4
-4
src/tx_arbitrator/tx_arbitrator_fsm.vhd
src/tx_arbitrator/tx_arbitrator_fsm.vhd
+2
-2
src/txt_buffer/txt_buffer.vhd
src/txt_buffer/txt_buffer.vhd
+3
-3
src/txt_buffer/txt_buffer_fsm.vhd
src/txt_buffer/txt_buffer_fsm.vhd
+2
-2
test/unit/Bit_Stuffing/Bit_Stuffing_tb.vhd
test/unit/Bit_Stuffing/Bit_Stuffing_tb.vhd
+2
-2
test/unit/Bus_Sampling/Bus_Sync_tb.vhd
test/unit/Bus_Sampling/Bus_Sync_tb.vhd
+1
-1
test/unit/CRC/CRC_tb.vhd
test/unit/CRC/CRC_tb.vhd
+1
-1
test/unit/Evnt_Logger/Event_logger_tb.vhd
test/unit/Evnt_Logger/Event_logger_tb.vhd
+1
-1
test/unit/Fault_confinement/Fault_confinement_tb.vhd
test/unit/Fault_confinement/Fault_confinement_tb.vhd
+1
-1
test/unit/Int_Manager/Int_Manager_tb.vhd
test/unit/Int_Manager/Int_Manager_tb.vhd
+1
-1
test/unit/Message_filter/message_filter_tb.vhd
test/unit/Message_filter/message_filter_tb.vhd
+2
-2
test/unit/Prescaler/Prescaler_tb.vhd
test/unit/Prescaler/Prescaler_tb.vhd
+1
-1
test/unit/Protocol_Control/Protocol_Control_tb.vhd
test/unit/Protocol_Control/Protocol_Control_tb.vhd
+2
-2
test/unit/RX_Buffer/RX_Buffer_tb.vhd
test/unit/RX_Buffer/RX_Buffer_tb.vhd
+1
-1
test/unit/TX_Arbitrator/TX_Arbitrator_tb.vhd
test/unit/TX_Arbitrator/TX_Arbitrator_tb.vhd
+1
-1
test/unit/TX_Buffer/Tx_Buffer_tb.vhd
test/unit/TX_Buffer/Tx_Buffer_tb.vhd
+1
-1
No files found.
src/CAN_Core/transcript
deleted
100644 → 0
View file @
8ac7e419
# ** Error: (vish-3296) Unknown option '--help'.
# Use the -help option for complete vsim usage.
src/CAN_top_level.vhd
View file @
d412b32f
...
...
@@ -156,8 +156,9 @@ entity CAN_top_level is
-------------------------------------------
signal
timestamp
:
in
std_logic_vector
(
63
downto
0
)
);
end
entity
CAN_top_level
;
architecture
rtl
of
CAN_top_level
is
----------------------------------------------------------------------------
----------------------------------------------------------------------------
...
...
@@ -468,23 +469,19 @@ entity CAN_top_level is
-- Transceiver delay output
signal
trv_delay_out
:
std_logic_vector
(
15
downto
0
);
end
entity
CAN_top_level
;
architecture
rtl
of
CAN_top_level
is
----------------------------------------------------------------------------
-- Defining explicit architectures for used entites
----------------------------------------------------------------------------
for
reg_comp
:
canfd_registers
use
entity
work
.
canfd_registers
(
rtl
);
for
rx_buf_comp
:
rx_buffer
use
entity
work
.
rx_buffer
(
rtl
);
for
tx_arb_comp
:
txArbitrator
use
entity
work
.
txArbitrator
(
rtl
);
for
mes_filt_comp
:
messageFilter
use
entity
work
.
messageFilter
(
rtl
);
for
int_man_comp
:
intManager
use
entity
work
.
intManager
(
rtl
);
for
core_top_comp
:
core_top
use
entity
work
.
core_top
(
rtl
);
for
prescaler_comp
:
prescaler_v3
use
entity
work
.
prescaler_v3
(
rtl
);
for
bus_sync_comp
:
busSync
use
entity
work
.
busSync
(
rtl
);
for
rst_sync_comp
:
rst_sync
use
entity
work
.
rst_sync
(
rtl
);
--for log_comp : CAN_logger use entity work.CAN_logger(rtl);
for
memory_registers_comp
:
memory_registers
use
entity
work
.
memory_registers
(
rtl
);
for
rx_buffer_comp
:
rx_buffer
use
entity
work
.
rx_buffer
(
rtl
);
for
tx_arbitrator_comp
:
tx_arbitrator
use
entity
work
.
tx_arbitrator
(
rtl
);
for
frame_filters_comp
:
frame_filters
use
entity
work
.
frame_filters
(
rtl
);
for
int_manager_comp
:
int_manager
use
entity
work
.
int_manager
(
rtl
);
for
can_core_comp
:
can_core
use
entity
work
.
can_core
(
rtl
);
for
prescaler_comp
:
prescaler
use
entity
work
.
prescaler
(
rtl
);
for
bus_sampling_comp
:
bus_sampling
use
entity
work
.
bus_sampling
(
rtl
);
for
rst_sync_comp
:
rst_sync
use
entity
work
.
rst_sync
(
rtl
);
begin
...
...
@@ -503,7 +500,7 @@ begin
rst
=>
res_n_sync
);
reg_comp
:
canfd
_registers
memory_registers_comp
:
memory
_registers
generic
map
(
compType
=>
CAN_COMPONENT_TYPE
,
use_logger
=>
use_logger
,
...
...
@@ -559,7 +556,7 @@ begin
);
rx_buf_comp
:
rx_buffer
rx_buf
fer
_comp
:
rx_buffer
generic
map
(
buff_size
=>
rx_buffer_size
)
...
...
@@ -596,9 +593,8 @@ begin
txt_buf_comp_gen
:
for
i
in
0
to
TXT_BUFFER_COUNT
-
1
generate
txt
Buffer_comp
:
txtB
uffer
txt
_buffer_comp
:
txt_b
uffer
generic
map
(
buf_count
=>
TXT_BUFFER_COUNT
,
ID
=>
i
...
...
@@ -623,7 +619,7 @@ begin
end
generate
;
tx_arb
_comp
:
txA
rbitrator
tx_arb
itrator_comp
:
tx_a
rbitrator
generic
map
(
buf_count
=>
TXT_BUFFER_COUNT
)
...
...
@@ -649,7 +645,7 @@ begin
timestamp
=>
timestamp
);
mes_filt_comp
:
messageFilter
frame_filters_comp
:
frame_filters
generic
map
(
sup_filtA
=>
sup_filtA
,
sup_filtB
=>
sup_filtB
,
...
...
@@ -683,7 +679,7 @@ begin
rx_store_data_valid
<=
rx_store_data
and
out_ident_valid
;
rec_message_store
<=
rec_message_valid
and
out_ident_valid
;
int_man
_comp
:
intM
anager
int_man
ager_comp
:
int_m
anager
generic
map
(
int_count
=>
INT_COUNT
)
...
...
@@ -709,7 +705,7 @@ begin
int_mask
=>
int_mask
);
c
ore_top_comp
:
core_top
c
an_core_comp
:
can_core
port
map
(
clk_sys
=>
clk_sys
,
res_n
=>
res_n_int
,
...
...
@@ -769,7 +765,7 @@ begin
sof_pulse
=>
sof_pulse
);
prescaler_comp
:
prescaler
_v3
prescaler_comp
:
prescaler
port
map
(
clk_sys
=>
clk_sys
,
res_n
=>
res_n_int
,
...
...
@@ -795,7 +791,7 @@ begin
sync_control
=>
sync_control
);
bus_s
ync_comp
:
busSync
bus_s
ampling_comp
:
bus_sampling
generic
map
(
use_Sync
=>
use_sync
)
...
...
@@ -826,8 +822,8 @@ begin
);
LOG_GEN
:
if
(
use_logger
)
generate
log_comp
:
CAN
_logger
event_logger_gen_true
:
if
(
use_logger
)
generate
event_logger_comp
:
event
_logger
generic
map
(
memory_size
=>
logger_size
)
...
...
@@ -849,16 +845,16 @@ begin
bt_FSM
=>
bt_FSM_out
,
data_overrun
=>
rx_data_overrun
);
end
generate
LOG_GEN
;
end
generate
event_logger_gen_true
;
LOG_GEN2
:
if
(
use_logger
=
false
)
generate
event_logger_gen_false
:
if
(
not
use_logger
)
generate
loger_finished
<=
'0'
;
loger_act_data
<=
(
others
=>
'0'
);
log_write_pointer
<=
(
others
=>
'0'
);
log_read_pointer
<=
(
others
=>
'0'
);
log_size
<=
(
others
=>
'0'
);
log_state_out
<=
config
;
end
generate
LOG_GEN2
;
end
generate
event_logger_gen_false
;
--Bit time clock output propagation
time_quanta_clk
<=
clk_tq_nbt
when
sp_control
=
NOMINAL_SAMPLE
else
...
...
src/Libraries/CANcomponents.vhd
View file @
d412b32f
...
...
@@ -114,7 +114,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- Registers
----------------------------------------------------------------------------
component
canfd
_registers
is
component
memory
_registers
is
generic
(
constant
compType
:
std_logic_vector
(
3
downto
0
)
:
=
CAN_COMPONENT_TYPE
;
constant
use_logger
:
boolean
:
=
true
;
...
...
@@ -362,7 +362,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- TXT Buffer module
----------------------------------------------------------------------------
component
txt
B
uffer
is
component
txt
_b
uffer
is
generic
(
constant
buf_count
:
natural
range
1
to
8
;
constant
ID
:
natural
:
=
1
...
...
@@ -392,7 +392,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- TXT Buffer FSM
----------------------------------------------------------------------------
component
txt
B
uffer_fsm
is
component
txt
_b
uffer_fsm
is
generic
(
constant
ID
:
natural
);
...
...
@@ -414,7 +414,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- TXT Arbitrator module
----------------------------------------------------------------------------
component
tx
A
rbitrator
is
component
tx
_a
rbitrator
is
generic
(
constant
buf_count
:
natural
range
1
to
8
);
...
...
@@ -446,7 +446,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- Priority decoder for TXT Buffer selection
----------------------------------------------------------------------------
component
priority
D
ecoder
is
component
priority
_d
ecoder
is
generic
(
constant
buf_count
:
natural
range
1
to
8
);
...
...
@@ -463,7 +463,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- TX Arbitrator FSM
----------------------------------------------------------------------------
component
tx
A
rbitrator_fsm
is
component
tx
_a
rbitrator_fsm
is
port
(
signal
clk_sys
:
in
std_logic
;
signal
res_n
:
in
std_logic
;
...
...
@@ -487,9 +487,9 @@ package CANcomponents is
----------------------------------------------------------------------------
--
Message filter
module
--
Frame filters
module
----------------------------------------------------------------------------
component
messageFilter
is
component
frame_filters
is
generic
(
constant
sup_filtA
:
boolean
:
=
true
;
constant
sup_filtB
:
boolean
:
=
true
;
...
...
@@ -512,7 +512,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- Generic Bit Filter
----------------------------------------------------------------------------
component
bit
F
ilter
is
component
bit
_f
ilter
is
generic
(
constant
width
:
natural
;
constant
is_present
:
boolean
...
...
@@ -530,7 +530,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- Range filter
----------------------------------------------------------------------------
component
range
F
ilter
is
component
range
_f
ilter
is
generic
(
constant
width
:
natural
;
constant
is_present
:
boolean
...
...
@@ -548,7 +548,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- Interrupt manager module
----------------------------------------------------------------------------
component
int
M
anager
is
component
int
_m
anager
is
generic
(
constant
int_count
:
natural
range
0
to
32
:
=
11
);
...
...
@@ -614,7 +614,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- CAN Core module
----------------------------------------------------------------------------
component
c
ore_top
is
component
c
an_core
is
port
(
signal
clk_sys
:
in
std_logic
;
signal
res_n
:
in
std_logic
;
...
...
@@ -679,7 +679,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- Prescaler module
----------------------------------------------------------------------------
component
prescaler
_v3
is
component
prescaler
is
port
(
signal
clk_sys
:
in
std_logic
;
signal
res_n
:
in
std_logic
;
...
...
@@ -708,9 +708,9 @@ package CANcomponents is
----------------------------------------------------------------------------
-- Bus
synchroniser
module
-- Bus
Sampling
module
----------------------------------------------------------------------------
component
bus
Sync
is
component
bus
_sampling
is
generic
(
use_Sync
:
boolean
);
...
...
@@ -739,9 +739,9 @@ package CANcomponents is
----------------------------------------------------------------------------
--
CAN
Logger module
--
Event
Logger module
----------------------------------------------------------------------------
component
CAN
_logger
is
component
event
_logger
is
generic
(
constant
memory_size
:
natural
:
=
16
);
...
...
@@ -773,7 +773,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- CAN CRC module
----------------------------------------------------------------------------
component
can
CRC
is
component
can
_crc
is
generic
(
constant
crc15_pol
:
std_logic_vector
(
15
downto
0
)
:
=
x"C599"
;
constant
crc17_pol
:
std_logic_vector
(
19
downto
0
)
:
=
x"3685B"
;
...
...
@@ -796,7 +796,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- Generic CRC calculation module
----------------------------------------------------------------------------
component
CRC
_calc
is
component
crc
_calc
is
generic
(
constant
crc_width
:
natural
;
constant
reset_polarity
:
std_logic
:
=
'0'
;
...
...
@@ -817,7 +817,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- Bit Stuffing
----------------------------------------------------------------------------
component
bit
Stuffing_v2
is
component
bit
_stuffing
is
port
(
signal
clk_sys
:
in
std_logic
;
signal
res_n
:
in
std_logic
;
...
...
@@ -836,7 +836,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- Bit Destuffing
----------------------------------------------------------------------------
component
bit
D
estuffing
is
component
bit
_d
estuffing
is
port
(
signal
clk_sys
:
in
std_logic
;
signal
res_n
:
in
std_logic
;
...
...
@@ -855,9 +855,9 @@ package CANcomponents is
----------------------------------------------------------------------------
-- Operation control
FSM
-- Operation control
module
----------------------------------------------------------------------------
component
operation
C
ontrol
is
component
operation
_c
ontrol
is
port
(
signal
clk_sys
:
in
std_logic
;
signal
res_n
:
in
std_logic
;
...
...
@@ -878,9 +878,9 @@ package CANcomponents is
----------------------------------------------------------------------------
-- Protocol Control
FSM
-- Protocol Control
module
----------------------------------------------------------------------------
component
protocol
C
ontrol
is
component
protocol
_c
ontrol
is
port
(
signal
clk_sys
:
in
std_logic
;
signal
res_n
:
in
std_logic
;
...
...
@@ -958,7 +958,7 @@ package CANcomponents is
----------------------------------------------------------------------------
-- Fault confinement
----------------------------------------------------------------------------
component
fault
Conf
is
component
fault
_confinement
is
port
(
signal
clk_sys
:
in
std_logic
;
signal
res_n
:
in
std_logic
;
...
...
src/apb_ifc.vhd
→
src/apb
/apb
_ifc.vhd
View file @
d412b32f
File moved
src/
Bus_Timing_Synchronisation/busSync
.vhd
→
src/
bus_sampling/bus_sampling
.vhd
View file @
d412b32f
...
...
@@ -95,7 +95,7 @@ USE WORK.CANconstants.ALL;
use
work
.
CAN_FD_register_map
.
all
;
use
work
.
cmn_lib
.
all
;
entity
bus
Sync
is
entity
bus
_sampling
is
GENERIC
(
------------------------------------------------------------------------
...
...
@@ -183,7 +183,7 @@ entity busSync is
end
entity
;
architecture
rtl
of
bus
Sync
is
architecture
rtl
of
bus
_sampling
is
-----------------------------------------------------------------------------
...
...
src/
CAN_Core/bitDeS
tuffing.vhd
→
src/
can_core/bit_destuffing/bit_des
tuffing.vhd
View file @
d412b32f
...
...
@@ -79,7 +79,7 @@ use IEEE.std_logic_1164.all;
use
IEEE
.
numeric_std
.
all
;
use
WORK
.
CANconstants
.
all
;
entity
bit
D
estuffing
is
entity
bit
_d
estuffing
is
port
(
------------------------------------------------------------------------
-- Clock And Reset
...
...
@@ -131,6 +131,9 @@ entity bitDestuffing is
-- Number of destuffed bits with regular bit stuffing method
signal
dst_ctr
:
out
natural
range
0
to
7
);
end
entity
;
architecture
rtl
of
bit_destuffing
is
----------------------------------------------------------------------------
--Internal signals and registers
...
...
@@ -150,9 +153,6 @@ entity bitDestuffing is
-- Note: Number of stuffed, destuffed bits is transmitted modulo 8. Thus
-- only 3 bits counter is enough!!
end
entity
;
architecture
rtl
of
bitDestuffing
is
begin
----------------------------------------------------------------------------
...
...
src/
CAN_Core/bitStuffing_v2
.vhd
→
src/
can_core/bit_stuffing/bit_stuffing
.vhd
View file @
d412b32f
...
...
@@ -77,7 +77,7 @@ USE IEEE.std_logic_1164.all;
USE
IEEE
.
numeric_std
.
ALL
;
USE
WORK
.
CANconstants
.
ALL
;
entity
bit
Stuffing_v2
is
entity
bit
_stuffing
is
port
(
------------------------------------------------------------------------
...
...
@@ -124,6 +124,10 @@ entity bitStuffing_v2 is
-- fed back to CAN Core for CRC calculation in CAN FD Phase!
);
end
entity
;
architecture
rtl
of
bit_stuffing
is
----------------------------------------------------------------------------
-- Internal Registers
...
...
@@ -144,10 +148,6 @@ entity bitStuffing_v2 is
signal
stuff_ctr
:
natural
range
0
to
7
;
signal
enable_prev
:
std_logic
;
end
entity
;
architecture
rtl
of
bitStuffing_v2
is
begin
bst_ctr
<=
stuff_ctr
;
...
...
src/
CAN_Core/core_top
.vhd
→
src/
can_core/can_core
.vhd
View file @
d412b32f
...
...
@@ -93,7 +93,7 @@ use work.CANcomponents.ALL;
use
work
.
CAN_FD_frame_format
.
ALL
;
use
work
.
CAN_FD_frame_format
.
all
;
entity
c
ore_top
is
entity
c
an_core
is
port
(
------------------------------------------------------------------------
-- System clock and Reset
...
...
@@ -280,6 +280,10 @@ entity core_top is
signal
sof_pulse
:
out
std_logic
);
end
entity
;
architecture
rtl
of
can_core
is
----------------------------------------------------------------------------
-- Driving bus aliases
...
...
@@ -524,37 +528,34 @@ entity core_top is
-- Signals start of frame to rest of the design
signal
sof_pulse_r
:
std_logic
;
end
entity
;
architecture
rtl
of
core_top
is
for
OP_State_comp
:
operationControl
use
entity
work
.
operationControl
(
rtl
);
for
operation_control_comp
:
operation_control
use
entity
work
.
operation_control
(
rtl
);
for
PC_State_comp
:
protocolC
ontrol
use
entity
work
.
protocol
C
ontrol
(
rtl
);
for
protocol_control_comp
:
protocol_c
ontrol
use
entity
work
.
protocol
_c
ontrol
(
rtl
);
for
fault
Conf_comp
:
faultConf
use
entity
work
.
fault
Conf
(
rtl
);
for
fault
_confinement_comp
:
fault_confinement
use
entity
work
.
fault
_confinement
(
rtl
);
for
crc_wbs_rx_comp
:
can
CRC
use
entity
work
.
can
CRC
(
rtl
);
for
crc_wbs_rx_comp
:
can
_crc
use
entity
work
.
can
_crc
(
rtl
);
for
crc_nbs_rx_comp
:
can
CRC
use
entity
work
.
can
CRC
(
rtl
);
for
crc_nbs_rx_comp
:
can
_crc
use
entity
work
.
can
_crc
(
rtl
);
for
crc_wbs_tx_comp
:
can
CRC
use
entity
work
.
can
CRC
(
rtl
);
for
crc_wbs_tx_comp
:
can
_crc
use
entity
work
.
can
_crc
(
rtl
);
for
crc_nbs_tx_comp
:
can
CRC
use
entity
work
.
can
CRC
(
rtl
);
for
crc_nbs_tx_comp
:
can
_crc
use
entity
work
.
can
_crc
(
rtl
);
for
b
s_comp
:
bitStuffing_v2
use
entity
work
.
bit
Stuffing_v2
(
rtl
);
for
b
it_stuffing_comp
:
bit_stuffing
use
entity
work
.
bit
_stuffing
(
rtl
);
for
bit
Dest_comp
:
bitD
estuffing
use
entity
work
.
bit
D
estuffing
(
rtl
);
for
bit
_destuffing_comp
:
bit_d
estuffing
use
entity
work
.
bit
_d
estuffing
(
rtl
);
begin
...
...
@@ -587,7 +588,7 @@ begin
----------------------------------------------------------------------------
-- Operation control state machine
----------------------------------------------------------------------------
OP_State_comp
:
operationC
ontrol
operation_control_comp
:
operation_c
ontrol
port
map
(
clk_sys
=>
clk_sys
,
res_n
=>
res_n
,
...
...
@@ -607,9 +608,9 @@ begin
----------------------------------------------------------------------------
-- Protocol control
state machin
e
-- Protocol control
modul
e
----------------------------------------------------------------------------
PC_State_comp
:
protocolC
ontrol
protocol_control_comp
:
protocol_c
ontrol
port
map
(
clk_sys
=>
clk_sys
,
res_n
=>
res_n
,
...
...
@@ -707,7 +708,7 @@ begin
----------------------------------------------------------------------------
-- Fault confinement
----------------------------------------------------------------------------
fault
Conf_comp
:
faultConf
fault
_confinement_comp
:
fault_confinement
port
map
(
clk_sys
=>
clk_sys
,
res_n
=>
res_n
,
...
...
@@ -758,7 +759,7 @@ begin
----------------------------------------------------------------------------
-- CRC with bit stuffing from RX Data
----------------------------------------------------------------------------
crc_wbs_rx_comp
:
can
CRC
crc_wbs_rx_comp
:
can
_crc
generic
map
(
crc15_pol
=>
CRC15_POL
,
crc17_pol
=>
CRC17_POL
,
...
...
@@ -780,7 +781,7 @@ begin
----------------------------------------------------------------------------
-- CRC no bit stuffing from RX Data
----------------------------------------------------------------------------
crc_nbs_rx_comp
:
can
CRC
crc_nbs_rx_comp
:
can
_crc
generic
map
(
crc15_pol
=>
CRC15_POL
,
crc17_pol
=>
CRC17_POL
,
...
...
@@ -802,7 +803,7 @@ begin
----------------------------------------------------------------------------
-- CRC with bit stuffing from TX Data
----------------------------------------------------------------------------
crc_wbs_tx_comp
:
can
CRC
crc_wbs_tx_comp
:
can
_crc
generic
map
(
crc15_pol
=>
CRC15_POL
,
crc17_pol
=>
CRC17_POL
,
...
...
@@ -824,7 +825,7 @@ begin
----------------------------------------------------------------------------
-- CRC no bit stuffing from TX Data
----------------------------------------------------------------------------
crc_nbs_tx_comp
:
can
CRC
crc_nbs_tx_comp
:
can
_crc
generic
map
(
crc15_pol
=>
CRC15_POL
,
crc17_pol
=>
CRC17_POL
,
...
...
@@ -850,7 +851,7 @@ begin
----------------------------------------------------------------------------
-- Bit Stuffing
----------------------------------------------------------------------------
b
s_comp
:
bitStuffing_v2
b
it_stuffing_comp
:
bit_stuffing
port
map
(
clk_sys
=>
clk_sys
,
res_n
=>
res_n
,
...
...
@@ -868,7 +869,7 @@ begin
----------------------------------------------------------------------------
-- Bit De-Stuffing
----------------------------------------------------------------------------
bit
Dest_comp
:
bitD
estuffing
bit
_destuffing_comp
:
bit_d
estuffing
port
map
(
clk_sys
=>
clk_sys
,
res_n
=>
res_n
,
...
...
src/
CAN_Core/CRC
.vhd
→
src/
can_core/crc/can_crc
.vhd
View file @
d412b32f
...
...
@@ -71,7 +71,7 @@ use work.CAN_FD_register_map.all;
use
work
.
CANcomponents
.
all
;
entity
can
CRC
is
entity
can
_crc
is
generic
(
constant
crc15_pol
:
std_logic_vector
(
15
downto
0
)
:
=
x"C599"
;
constant
crc17_pol
:
std_logic_vector
(
19
downto
0
)
:
=
x"3685B"
;
...
...
@@ -116,7 +116,7 @@ entity canCRC is
end
entity
;
architecture
rtl
of
can
CRC
is
architecture
rtl
of
can
_crc
is
-- ISO CAN FD or NON ISO CAN FD Value
signal
drv_fd_type
:
std_logic
;
...
...
@@ -149,7 +149,7 @@ begin
----------------------------------------------------------------------------
-- CRC instances
----------------------------------------------------------------------------
crc_
15_comp
:
CRC
_calc
crc_
calc_15_comp
:
crc
_calc
generic
map
(
crc_width
=>
15
,
reset_polarity
=>
ACT_RESET
,
...
...
@@ -166,7 +166,7 @@ begin
crc
=>
crc15
);
crc_
17_comp
:
CRC
_calc
crc_
calc_17_comp
:
crc
_calc
generic
map
(
crc_width
=>
17
,
reset_polarity
=>
ACT_RESET
,
...
...
@@ -183,7 +183,7 @@ begin
crc
=>
crc17
);
crc_
21_comp
:
CRC
_calc
crc_
calc_21_comp
:
crc
_calc
generic
map
(
crc_width
=>
21
,
reset_polarity
=>
ACT_RESET
,
...
...
src/
CAN_Core/CRC
_calc.vhd
→
src/
can_core/crc/crc
_calc.vhd
View file @
d412b32f
...
...
@@ -59,7 +59,7 @@ USE IEEE.numeric_std.ALL;
use
work
.
CANconstants
.
all
;
use
work
.
CAN_FD_register_map
.
all
;
entity
CRC
_calc
is
entity
crc
_calc
is
generic
(
-- Width of CRC sequence
...
...
@@ -106,7 +106,7 @@ entity CRC_calc is
end
entity
;