Commit d11c02ae authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Code formatting nr 4

parent a9f7703a
......@@ -175,29 +175,29 @@ architecture rtl of messageFilter is
begin
--Driving signal aliases
drv_filter_A_mask <= drv_bus(DRV_FILTER_A_MASK_HIGH downto
DRV_FILTER_A_MASK_LOW);
DRV_FILTER_A_MASK_LOW);
drv_filter_A_ctrl <= drv_bus(DRV_FILTER_A_CTRL_HIGH downto
DRV_FILTER_A_CTRL_LOW);
DRV_FILTER_A_CTRL_LOW);
drv_filter_A_bits <= drv_bus(DRV_FILTER_A_BITS_HIGH downto
DRV_FILTER_A_BITS_LOW);
DRV_FILTER_A_BITS_LOW);
drv_filter_B_mask <= drv_bus(DRV_FILTER_B_MASK_HIGH downto
DRV_FILTER_B_MASK_LOW);
DRV_FILTER_B_MASK_LOW);
drv_filter_B_ctrl <= drv_bus(DRV_FILTER_B_CTRL_HIGH downto
DRV_FILTER_B_CTRL_LOW);
DRV_FILTER_B_CTRL_LOW);
drv_filter_B_bits <= drv_bus(DRV_FILTER_B_BITS_HIGH downto
DRV_FILTER_B_BITS_LOW);
DRV_FILTER_B_BITS_LOW);
drv_filter_C_mask <= drv_bus(DRV_FILTER_C_MASK_HIGH downto
DRV_FILTER_C_MASK_LOW);
DRV_FILTER_C_MASK_LOW);
drv_filter_C_ctrl <= drv_bus(DRV_FILTER_C_CTRL_HIGH downto
DRV_FILTER_C_CTRL_LOW);
DRV_FILTER_C_CTRL_LOW);
drv_filter_C_bits <= drv_bus(DRV_FILTER_C_BITS_HIGH downto
DRV_FILTER_C_BITS_LOW);
DRV_FILTER_C_BITS_LOW);
drv_filter_ran_ctrl <= drv_bus(DRV_FILTER_RAN_CTRL_HIGH downto
DRV_FILTER_RAN_CTRL_LOW);
DRV_FILTER_RAN_CTRL_LOW);
drv_filter_ran_lo_th <= drv_bus(DRV_FILTER_RAN_LO_TH_HIGH downto
DRV_FILTER_RAN_LO_TH_LOW);
DRV_FILTER_RAN_LO_TH_LOW);
drv_filter_ran_hi_th <= drv_bus(DRV_FILTER_RAN_HI_TH_HIGH downto
DRV_FILTER_RAN_HI_TH_LOW);
DRV_FILTER_RAN_HI_TH_LOW);
drv_filters_ena <= drv_bus(DRV_FILTERS_ENA_INDEX);
--Input frame type internal signal
......@@ -279,7 +279,7 @@ begin
int_filter_ran_valid <= '1' when (--Identifier matches the range set
(rec_ident_dec
<=
to_integer(unsigned(drv_filter_ran_hi_th)))
to_integer(unsigned(drv_filter_ran_hi_th)))
AND
(rec_ident_dec
>=
......
......@@ -91,10 +91,10 @@ use work.CANconstants.all;
entity rxBuffer is
GENERIC(
--Maximal number of 32 bit words to store (Minimal value=16, one 64 bytes
--message length) Only 2^k are allowed as buff_size. Memory adressing is
--in modular arithmetic, synthesis of modulo by number other than 2^k is
-- not supported!!!
--Maximal number of 32 bit words to store (Minimal value=16, one 64 bytes
--message length) Only 2^k are allowed as buff_size. Memory adressing is
--in modular arithmetic, synthesis of modulo by number other than 2^k is
-- not supported!!!
buff_size :natural range 4 to 512 :=32
);
PORT(
......@@ -206,7 +206,7 @@ entity rxBuffer is
constant data_width :natural := 32; --Word data width
type rx_memory is array(0 to buff_size-1) of
std_logic_vector(data_width-1 downto 0); --Memory type
std_logic_vector(data_width-1 downto 0); --Memory type
--Memory declaration inferred in SRAM
signal memory :rx_memory;
......@@ -267,10 +267,10 @@ begin
-- Address for the Receive data RAM in the CAN Core! Comparator is temporary
-- before the data order will be reversed!
rec_dram_addr <= 18-copy_counter when (copy_counter>2
and
copy_counter<19)
else
0;
and
copy_counter<19)
else
0;
------------------------------------------------------------------------------
--Storing data from CANCore and loading data into reading buffer
......@@ -392,11 +392,11 @@ begin
--Writing Frame format Word
rx_message_disc <= '0';
memory(write_pointer) <= "000000000000000000000"&
rec_esi&rec_brs&
'1'&rec_frame_type_in&
rec_ident_type_in&
rec_is_rtr&
'0'&rec_dlc_in;
rec_esi&rec_brs&
'1'&rec_frame_type_in&
rec_ident_type_in&
rec_is_rtr&
'0'&rec_dlc_in;
memory_valid(write_pointer) <= '1';
--Increasing write pointer
......@@ -487,7 +487,7 @@ begin
end if;
rx_mem_free <= std_logic_vector(
to_unsigned(mem_free,8));
to_unsigned(mem_free,8));
--Assigning output whenever memory is full
if (mem_free=0) then
......@@ -505,7 +505,7 @@ begin
--Propagating message count to output
rx_message_count <= std_logic_vector(
to_unsigned(message_count,8));
to_unsigned(message_count,8));
end if;
end process memory_acess;
......
......@@ -309,9 +309,9 @@ begin
--at least one of the frames is valid
------------------------------------------------------------------------------
tran_frame_valid_out <= '1' when (ts_valid="10" or
ts_valid="01" or
ts_valid="11")
else
ts_valid="01" or
ts_valid="11")
else
'0';
------------------------------------------------------------------------------
......
......@@ -76,9 +76,9 @@ USE WORK.CANconstants.ALL;
entity busSync is
GENERIC (
--Whenever Synchronisation chain should be used for sampled data from the
--bus. Turn off only when Synthetizer puts synchronisation chain automa-
--tically on the output pins! Otherwise metastability issues will occur!
--Whenever Synchronisation chain should be used for sampled data from the
--bus. Turn off only when Synthetizer puts synchronisation chain automa-
--tically on the output pins! Otherwise metastability issues will occur!
use_Sync:boolean:=false
);
PORT(
......
......@@ -31,9 +31,9 @@ USE WORK.CANconstants.ALL;
-- June 2015 Version 1 of circuit
-- July 2015 Version 2 and 3 of circuit
-- 19.12.2015 Added minimal information processing time protection. It is no
-- longer possible to shorten PH2 segment less than 4 clock cycles.
-- longer possible to shorten PH2 segment less than 4 clock cycles.
-- No sampling signals are left out in this case!
--
-- 14.6.2016 1.Added reset state into the bit time FSM. As long as reset is
-- active bt_FSM is kept in reset. First clock cyle it comes out
-- reset sync is set. This removes the error that Sync sequence
......@@ -328,7 +328,7 @@ begin
--Internal aliases
tq_dur <= to_integer(unsigned(drv_tq_nbt))
when (sp_control=NOMINAL_SAMPLE) else
when (sp_control=NOMINAL_SAMPLE) else
to_integer(unsigned(drv_tq_dbt));
......@@ -502,7 +502,7 @@ begin
ph2_real<=1;
end if;
else
--This causes finish of ph2 in next time quantum
--This causes finish of ph2 in next time quantum
ph2_real<=bt_counter;
end if;
end if;
......@@ -520,7 +520,7 @@ begin
--So we shorten PH2 only to its minimal possible length. The
--length is dependent on time quantum duration
if(tq_dbt=1)then --Presc=1
--This is only case not according to specification
--This is only case not according to specification
ph2_real<=4;
elsif (tq_dbt=2) then --Presc=2
ph2_real<=2;
......@@ -541,8 +541,8 @@ begin
--form positive resynchronisation. Also when dominant bit was just
--send on the bus, no positive resynchronization is performed
elsif((data_tx=RECESSIVE)
and
(not(OP_State=transciever and sp_control=SECONDARY_SAMPLE)))
and
(not(OP_State=transciever and sp_control=SECONDARY_SAMPLE)))
then
if(bt_FSM=prop)then
if(sp_control=NOMINAL_SAMPLE)then
......@@ -723,7 +723,10 @@ begin
FSM_Preset<='0';
elsif(hard_sync_valid='1' and FSM_Preset='0')then
hard_sync_valid<='0';
elsif(hard_sync_valid='0' and FSM_Preset='0' and FSM_Preset_2='0')then
elsif(hard_sync_valid='0' and
FSM_Preset='0' and
FSM_Preset_2='0')
then
--One cycle has to be between sync signal! Otherwise PC control
--wont be able to react on hard sync valid!
--Here sync signal is finally set!
......@@ -766,25 +769,25 @@ begin
sample_nbt_del_1_r<='0';
sample_dbt_del_1_r<='0';
elsif rising_edge(clk_sys)then
if(sync_nbt_r='1')then sync_nbt_del_1_r<='1';
else sync_nbt_del_1_r<='0';
if (sync_nbt_r='1') then sync_nbt_del_1_r<='1';
else sync_nbt_del_1_r<='0';
end if;
if(sync_dbt_r='1')then sync_dbt_del_1_r<='1';
else sync_dbt_del_1_r<='0';
if (sync_dbt_r='1') then sync_dbt_del_1_r<='1';
else sync_dbt_del_1_r<='0';
end if;
if(sample_nbt_r='1')then sample_nbt_del_1_r<='1';
else sample_nbt_del_1_r<='0';
if (sample_nbt_r='1') then sample_nbt_del_1_r<='1';
else sample_nbt_del_1_r<='0';
end if;
if(sample_dbt_r='1')then sample_dbt_del_1_r<='1';
else sample_dbt_del_1_r<='0';
if (sample_dbt_r='1') then sample_dbt_del_1_r<='1';
else sample_dbt_del_1_r<='0';
end if;
if(sample_nbt_del_1_r='1')then sample_nbt_del_2_r<='1';
else sample_nbt_del_2_r<='0';
if (sample_nbt_del_1_r='1') then sample_nbt_del_2_r<='1';
else sample_nbt_del_2_r<='0';
end if;
if(sample_dbt_del_1_r='1')then sample_dbt_del_2_r<='1';
else sample_dbt_del_2_r<='0';
if (sample_dbt_del_1_r='1') then sample_dbt_del_2_r<='1';
else sample_dbt_del_2_r<='0';
end if;
end if;
......
......@@ -4,7 +4,7 @@ USE IEEE.numeric_std.ALL;
USE ieee.std_logic_unsigned.All;
use work.CANconstants.all;
-------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--
-- CAN with Flexible Data-Rate IP Core
--
......@@ -29,28 +29,31 @@ use work.CANconstants.all;
-- Revision History:
--
-- June 2015 Created file
-- 28.5.2016 Starting polynomial changed for crc 17 and crc 21. Highest bit is now fixed in logic one
-- to be compliant with CAN ISO FD. It will be needed to implement both ways still since ISO
-- and non-ISO FD will be changable via configuration bit!
-- 4.6.2016 Added drv_is_fd to cover differencce in highest bit of crc17 and crc21 polynomial
-------------------------------------------------------------------------------------------------------------
-- 28.5.2016 Starting polynomial changed for crc 17 and crc 21. Highest bit
-- is now fixed in logic one to be compliant with CAN ISO FD. It
-- will be needed to implement both ways still since ISO and
-- non-ISO FD will be changable via configuration bit!
-- 4.6.2016 Added drv_is_fd to cover differencce in highest bit of crc17
-- and crc21 polynomial
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- CRC Checking for CAN flexible data Rate. Three CRC are calculated simultaneously. Serial Data input. ---
-- Operation starts with enable transition from 0 to 1. Valid input data has to be present then. --
-- Circuit processes the data on trig signal in logic 1. Circuit operation finishes when 1 to 0 transiti --
-- on on enable signal appears. The output CRC is valid then. CRC stays valid until following 0 to 1 ena --
-- ble transition. This also erases CRC registers.
-- CRC Checking for CAN flexible data Rate. Three CRC are calculated simulta-
-- neously. Serial Data input. Operation starts with enable transition from 0
-- to 1. Valid input data has to be present then. Circuit processes the data on
-- trig signal in logic 1. Circuit operation finishes when 1 to 0 transition on
-- enable signal appears. The output CRC is valid then. CRC stays valid until
-- following 0 to 1 enable transition. This also erases CRC registers.
--
-- Refer to CAN 2.0 or CAN FD Specification for CRC calculation algorythm --
----------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity canCRC is
generic(
constant crc15_pol : std_logic_vector(15 downto 0):=std_logic_vector'(X"C599");
constant crc17_pol : std_logic_vector(19 downto 0):=std_logic_vector'(X"3685B");
constant crc21_pol : std_logic_vector(23 downto 0):=std_logic_vector'(X"302899")
constant crc15_pol : std_logic_vector(15 downto 0):=x"C599";
constant crc17_pol : std_logic_vector(19 downto 0):=x"3685B";
constant crc21_pol : std_logic_vector(23 downto 0):=x"302899"
);
port(
----------
......@@ -65,8 +68,9 @@ entity canCRC is
signal res_n :in std_logic; --Asynchronous reset
signal enable :in std_logic;
--By transition from 0 to 1 on enable sampled on clk_sys rising edge (and with trig='1')
--operation is started. First bit of data already has to be on data_in input.
--By transition from 0 to 1 on enable sampled on clk_sys rising edge
--(and with trig='1') operation is started. First bit of data already has
--to be on data_in input.
--Circuit works as long as enable=1.
signal drv_bus :in std_logic_vector(1023 downto 0);
......@@ -86,8 +90,11 @@ entity canCRC is
signal crc17_reg : std_logic_vector(16 downto 0);
signal crc21_reg : std_logic_vector(20 downto 0);
signal start_reg : std_logic; --Holds previous value of enable input. Detects 0 to 1 transition
signal drv_fd_type : std_logic; --ISO CAN FD or NON ISO CAN FD Value
--Holds previous value of enable input. Detects 0 to 1 transition
signal start_reg : std_logic;
--ISO CAN FD or NON ISO CAN FD Value
signal drv_fd_type : std_logic;
end entity;
......@@ -206,7 +213,7 @@ begin
crc21_reg <= (OTHERS=>'0');
crc21_reg(20) <= '1';
crc21_nxt := '0';
elsif rising_edge(clk_sys)then --TODO think of optimization IF clocks are synthetized via AND gate!!!
elsif rising_edge(clk_sys)then
--Erase the CRC value at the begining of
--calculation
......
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE ieee.std_logic_unsigned.All;
USE WORK.CANconstants.ALL;
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
use WORK.CANconstants.all;
-------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--
-- CAN with Flexible Data-Rate IP Core
--
......@@ -30,88 +30,114 @@ USE WORK.CANconstants.ALL;
--
-- July 2015 Created file
-- 19.5.2016 1. Added Stuff bit counter to cover ISO FD extra field!
-- 2. Edge detection 0->1 added at fixed_stuff input. Once edge is detected
-- same_bits counter is erased! This prevents the error of inserting stuff
-- bit sooner than fixed length when last bit of data field have equal value!
-- 6.6.2016 Added fixed stuff bit at the transition from non fixed stuff to fixed stuff! Thisway
-- bit stuffing also covers the one fixed stuff bit in the beginning of CRC phase!!
-- Added bit stuffing counter to count the dynamic stuff bits in ISO FD.
-- 2. Edge detection 0->1 added at fixed_stuff input. Once edge
-- is detected same_bits counter is erased! This prevents the
-- error of inserting stuff bit sooner than fixed length when
-- last bit of data field have equal value!
-- 6.6.2016 Added fixed stuff bit at the transition from non fixed stuff
-- to fixed stuff! Thisway bit stuffing also covers the one fixed
-- stuff bit in the beginning of CRC phase!! Added bit stuffing
-- counter to count the dynamic stuff bits in ISO FD.
-- 13.6.2016 1.Added mod 8 into same_bits counter increase
-- 2.Added keeping previous value of dst_counter when circuit is disabled instead of erasing!
-- This way ciruit is compatible with bit stuffing!
-- 3.dst_bit_ctr value kept when destuffing error occured for correct behaviour in testbench.
-- This is only a small thing since when stuff error occurs bit stuffing is turned off
-- immediately due to error frame transmittion and dst_ctr is not needed anymore!!!
-- 4.Added warning when bit stuffing rule is set to 0 or 1 which is invalid setting!
-- 12.1.2017 Changed priority of fixed bit-destuffing processing. Fixed bit destuffing should always have
-- higher priority than non-fixed bit-destuffing and thus be before in the If-elsif condition!
-- This is due to possible conflic of normal and fixed bit destuffing in the start of FD CRC.
-- Fixed bit-destuff should win!
-------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- 2.Added keeping previous value of dst_counter when circuit is
-- disabled instead of erasing! This way ciruit is compatible
-- with bit stuffing!
-- 3.dst_bit_ctr value kept when destuffing error occured for
-- correct behaviour in testbench. This is only a small thing
-- since when stuff error occurs bit stuffing is turned off
-- immediately due to error frame transmittion and dst_ctr is
-- not needed anymore!!!
-- 4.Added warning when bit stuffing rule is set to 0 or 1 which
-- is invalid setting!
-- 12.1.2017 Changed priority of fixed bit-destuffing processing. Fixed bit
-- destuffing should always have higher priority than non-fixed
-- bit-destuffing and thus be before in the If-elsif condition!
-- This is due to possible conflic of normal and fixed bit destu-
-- ffing in the start of FD CRC. Fixed bit-destuff should win!
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--Purpose:
-- Bit destuffing circuit. Data sampled always with valid trig_spl_1 signal. Length of bitStuffing controlled via
-- stuff_length input. Stuff error signalises Error when the stuff rule is not valid (stuff_lenght+1) consecutive
-- bits of the same polarity. Signal destuffed indicates that current output bit is not valid data bit, but is
-- destuffed bit taken out from input data stream!
-----------------------------------------------------------------------------------------------------------------------
-- Bit destuffing circuit. Data sampled always with valid trig_spl_1 signal.
-- Length of bitStuffing controlled via stuff_length input. Stuff error signa-
-- lises Error when the stuff rule is not valid (stuff_lenght+1) consecutive
-- bits of the same polarity. Signal destuffed indicates that current output
-- bit is not valid data bit, but is destuffed bit taken out from input data
-- stream!
--------------------------------------------------------------------------------
entity bitDestuffing is
PORT(
port(
-------------------
--Clock And Reset--
-------------------
signal clk_sys :in std_logic; --System clock
signal res_n :in std_logic; --Async Reset
signal clk_sys : in std_logic; --System clock
signal res_n : in std_logic; --Async Reset
-------------------------
--Bus Sampling Interface-
-------------------------
signal data_in :in std_logic; --Sampled data from busSync.vhd
signal data_in : in std_logic; --Sampled data from busSync.vhd
-----------------------
--Prescaler interface -
-----------------------
signal trig_spl_1 :in std_logic; --Triggering signal with one clk_sys delay behind the used sampling signal
--Triggering signal with one clk_sys delay behind the used sampling signal
signal trig_spl_1 : in std_logic;
--Note: signals nbt_trig_spl_1 or dbt_trig_spl_1 can be used
-- depending whenever data bit time or nominal bit tim is used
--------------------
--Error Signalling--
--------------------
signal stuff_Error :out std_logic; --Stuff Error
signal stuff_Error : out std_logic; --Stuff Error
-----------------------
--CAN Core interface --
-----------------------
signal data_out :out std_logic; --Data output for CAN Core
signal destuffed :out std_logic; --Signal that data on output are not valid but it is a stuff bit
signal enable :in std_logic; --Enable of the circuit
signal stuff_Error_enable :in std_logic; --Enable stuff Error logging
signal fixed_stuff :in std_logic; --Whenever fixed bit Destuffing method is used
signal length :in std_logic_vector(2 downto 0); --Length of bit stuffing rule
signal dst_ctr :out natural range 0 to 7 --Number of destuffed bits with
--regular bit stuffing method
);
--Data output for CAN Core
signal data_out : out std_logic;
--Signal that data on output are not valid but it is a stuff bit
signal destuffed : out std_logic;
--Enable of the circuit
signal enable : in std_logic;
--Enable stuff Error logging
signal stuff_Error_enable : in std_logic;
--Whenever fixed bit Destuffing method is used
signal fixed_stuff : in std_logic;
--Length of bit stuffing rule
signal length : in std_logic_vector(2 downto 0);
--Number of destuffed bits with regular bit stuffing method
signal dst_ctr : out natural range 0 to 7
);
--Note:Bit Destuffing has no driving bus aliases
---------------------------------
--Internal signals and registers
---------------------------------
signal same_bits : natural range 0 to 15; --Number of equal consecutive bits
signal prev_val : std_logic; --Previous value of the bit
signal destuffed_reg : std_logic; --Registered value of destuffed
signal error_reg : std_logic; --Registred value of destuffed
signal enable_prev : std_logic; --Previous value of enable
signal fixed_prev : std_logic; --Previous value of fixed stuff method
--ISO CAN FD destuff bit counter
signal dst_bit_ctr : natural range 0 to 7;
--Note: Number of stuffed, destuffed bits is transmitted
-- modulo 8. Thus only 3 bits counter is enough!!
--Number of equal consecutive bits
signal same_bits : natural range 0 to 15;
signal prev_val : std_logic; --Previous value of the bit
signal destuffed_reg : std_logic; --Registered value of destuffed
signal error_reg : std_logic; --Registred value of destuffed
signal enable_prev : std_logic; --Previous value of enable
signal fixed_prev : std_logic; --Previous value of fixed stuff method
--ISO CAN FD destuff bit counter
signal dst_bit_ctr : natural range 0 to 7;
--Note: Number of stuffed, destuffed bits is transmitted modulo 8. Thus
-- only 3 bits counter is enough!!
end entity;
architecture rtl of bitDestuffing is
......@@ -120,129 +146,129 @@ begin
-----------------------
--Destuffing process
-----------------------
destuf_proc:process(res_n,clk_sys)
destuf_proc : process(res_n, clk_sys)
begin
if(res_n=ACT_RESET)then
same_bits <= 1;
prev_val <= RECESSIVE;
fixed_prev <= '0';
destuffed_reg <= '0';
error_reg <= '0';
--Bit stuff counter for ISO FD
dst_bit_ctr <= 0;
enable_prev <= '0';
elsif (rising_edge(clk_sys))then
--Edge detection on enable and fixed stuff
enable_prev <= enable;
dst_bit_ctr <= dst_bit_ctr;
if((length="000" or length="001")and (enable='1'))then
report "0 and 1 bit stuffing length is invalid" severity warning;
end if;
if(enable='1')then
if(res_n = ACT_RESET)then
same_bits <= 1;
prev_val <= RECESSIVE;
fixed_prev <= '0';
destuffed_reg <= '0';
error_reg <= '0';
--Bit stuff counter for ISO FD
dst_bit_ctr <= 0;
enable_prev <= '0';
elsif (rising_edge(clk_sys))then
--Edge detection on enable and fixed stuff
enable_prev <= enable;
dst_bit_ctr <= dst_bit_ctr;
if((length = "000" or length = "001")and (enable='1'))then
report "0 and 1 bit stuffing length is invalid" severity warning;
end if;
if(enable = '1')then
--When transition starts prev_val needs to be deleted! Otherwise
--stuff error might occur when first bits of identifier are zero
if(enable_prev='0')then
prev_val <= RECESSIVE;
dst_bit_ctr <= 0;
fixed_prev <= '0';
same_bits <= 1;
if(enable_prev = '0')then
prev_val <= RECESSIVE;
dst_bit_ctr <= 0;
fixed_prev <= '0';
same_bits <= 1;
--Destuffing is processed with triggering signal
elsif(trig_spl_1='1')then
prev_val <= data_in; --Data is always propagated
elsif(trig_spl_1 = '1')then
prev_val <= data_in; --Data is always propagated
--When stuffing method is changed in the beginning of the
--CRC field the stuffing counter needs to be erased!
if(fixed_stuff='1' and fixed_prev='0')then
prev_val <= RECESSIVE;
same_bits <= 1; --TODO: think if here shouldnt be zero
-- due to extra inserted stuff bit!!!
destuffed_reg <= '1';
fixed_prev <= fixed_stuff;
if(fixed_stuff = '1' and fixed_prev = '0')then
prev_val <= RECESSIVE;
same_bits <= 1; --TODO: think if here shouldnt be zero
-- due to extra inserted stuff bit!!!
destuffed_reg <= '1';