Commit d042eb84 authored by Martin Jeřábek's avatar Martin Jeřábek

apb_ifc: assert rden for only one cycle; enable psl assertions

parent 4b3d163f
...@@ -38,9 +38,14 @@ ...@@ -38,9 +38,14 @@
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Purpose: -- Purpose:
-- Adaptor from APB4 to internal bus. -- Adaptor from APB4 to internal bus.
-- NOTE: This is not strictly APB conformant as the read data stays only
-- for the next cycle; after that they are zeroed.
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Revision History: -- Revision History:
-- May 2018 First Implementation - Martin Jerabek -- May 2018 First Implementation - Martin Jerabek
-- 31.08.2018 Ensure that reg_rden_o is always asserted for only one cycle.
-- This is important for reads with side effects, such as
-- reading from FIFO.
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
...@@ -78,7 +83,21 @@ end entity; ...@@ -78,7 +83,21 @@ end entity;
architecture rtl of apb_ifc is architecture rtl of apb_ifc is
signal rst_countdown_reg : natural range 0 to 3; signal rst_countdown_reg : natural range 0 to 3;
signal next_apb_pready : std_logic;
signal ready_for_read : std_logic;
function to_std_logic(a : boolean) return std_logic is
begin
if a then
return '1';
else
return '0';
end if;
end function to_std_logic;
begin begin
-- psl default clock is rising_edge (aclk);
-- psl assert_onecycle_rden: assert always reg_rden_o = '1' -> next reg_rden_o = '0';
reg_data_in_o <= s_apb_pwdata; reg_data_in_o <= s_apb_pwdata;
s_apb_prdata <= reg_data_out_i; s_apb_prdata <= reg_data_out_i;
...@@ -100,7 +119,14 @@ begin ...@@ -100,7 +119,14 @@ begin
else else
(others => '1'); (others => '1');
reg_rden_o <= s_apb_psel and not s_apb_pwrite;
-- Read must be issued one cycle before finishing the transaction
-- and must be active only for 1 cycle so that when reading from a FIFO
-- the pointer is only incremented once.
-- rst_countdown_reg = 0 -> not s_apb_penable
-- otherwise rst_countdown_reg = 1 (s_apb_penable will stay in '1', so double trigger won't happen)
ready_for_read <= (not s_apb_penable and next_apb_pready) or to_std_logic(rst_countdown_reg = 1);
reg_rden_o <= s_apb_psel and not s_apb_pwrite and ready_for_read;
-- path can be shortened by registering it -- path can be shortened by registering it
-- ignore s_apb_pprot -- ignore s_apb_pprot
...@@ -117,6 +143,7 @@ begin ...@@ -117,6 +143,7 @@ begin
end if; end if;
end process; end process;
s_apb_pready <= '1' when rst_countdown_reg = 0 else '0'; next_apb_pready <= '1' when rst_countdown_reg = 0 else '0';
s_apb_pready <= next_apb_pready;
s_apb_pslverr <= '0'; s_apb_pslverr <= '0';
end architecture rtl; end architecture rtl;
...@@ -86,8 +86,8 @@ def add_flags(ui, lib, build): ...@@ -86,8 +86,8 @@ def add_flags(ui, lib, build):
rt.scan_tests_from_file(str(build / "../reference/vunit_reference_wrapper.vhd")) rt.scan_tests_from_file(str(build / "../reference/vunit_reference_wrapper.vhd"))
#lib.add_compile_option("ghdl.flags", ["-Wc,-g"]) #lib.add_compile_option("ghdl.flags", ["-Wc,-g"])
lib.add_compile_option("ghdl.flags", ["-fprofile-arcs", "-ftest-coverage"]) lib.add_compile_option("ghdl.flags", ["-fprofile-arcs", "-ftest-coverage", "-fpsl"])
ui.set_sim_option("ghdl.elab_flags", ["-Wl,-lgcov", "-Wl,--coverage", "-Wl,-no-pie"]) ui.set_sim_option("ghdl.elab_flags", ["-Wl,-lgcov", "-Wl,--coverage", "-Wl,-no-pie", "-fpsl"])
ui.set_sim_option("ghdl.sim_flags", ["--ieee-asserts=disable-at-0"]) ui.set_sim_option("ghdl.sim_flags", ["--ieee-asserts=disable-at-0"])
modelsim_init_files = get_common_modelsim_init_files() modelsim_init_files = get_common_modelsim_init_files()
ui.set_sim_option("modelsim.init_files.after_load", modelsim_init_files) ui.set_sim_option("modelsim.init_files.after_load", modelsim_init_files)
......
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