Commit cfef3b2d authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Optimization of RX Data storing.

From paralell logic vector sequential RAM is now
used in Protocol controller. RX Buffer
testbench accustomized, though still not passing!
Protocol control testbench: TODO!!!
parent 1f77dc66
......@@ -53,6 +53,9 @@ use work.CANconstants.all;
-- Now memory registers set drv_read_start only for ONE clock cycle per each access. So it is enough to
-- check whether signal is active! Thisway it is not necessary to add empty clock cycles between consecutive
-- reads from RX_DATA register!
-- 29.11.2017 Changed hadnling of received data. "rec_data_in" replaced by "rec_dram_word" and "rec_dram_addr" as part of
-- resource optimizations. Data are not available in parallel at input of the RX buffer but addressed in
-- internal RAM of Protocol controller.
--
-----------------------------------------------------------------------------------------------------------------------------------------------------
......@@ -87,7 +90,6 @@ entity rxBuffer is
--CAN Core interface (rec. data,validity, acknowledge)-
-------------------------------------------------------
signal rec_ident_in :in std_logic_vector(28 downto 0); --Message Identifier
signal rec_data_in :in std_logic_vector(511 downto 0); --Message Data (up to 64 bytes);
signal rec_dlc_in :in std_logic_vector(3 downto 0); --Data length code
signal rec_ident_type_in :in std_logic; --Recieved identifier type (0-BASE Format, 1-Extended Format);
signal rec_frame_type_in :in std_logic; --Recieved frame type (0-Normal CAN, 1- CAN FD)
......@@ -98,6 +100,10 @@ entity rxBuffer is
signal rec_message_ack :out std_logic; --Acknowledge for CAN Core about accepted data
signal rec_message_valid :in std_logic; --Output from acceptance filters (out_ident_valid) if message fits the filters
--Added interface for aux SRAM
signal rec_dram_word :in std_logic_vector(31 downto 0);
signal rec_dram_addr :out natural range 0 to 15;
------------------------------------
--Status signals of recieve buffer--
------------------------------------
......@@ -174,13 +180,16 @@ begin
rx_read_buff <= memory(read_pointer) when (memory_valid(read_pointer)='1')
else (OTHERS => '0'); --Read data from SRAM memory (1 port, async read)
-- Address for the Receive data RAM in the CAN Core!
-- Comparator is temporary before the data order will be reversed!
rec_dram_addr <= 18-copy_counter when (copy_counter>2 and copy_counter<19) else 0;
------------------------------------------------------------------
--Storing data from CANCore and loading data into reading buffer--
------------------------------------------------------------------
memory_acess:process(clk_sys,res_n)
variable data_length : natural range 0 to 16; --Length variable for frame stored into reading buffer (in 32 bit words)
variable mem_free : natural range 0 to buff_size; --Amount of free words
variable mem_free : natural range 0 to buff_size:= buff_size; --Amount of free words
variable message_count : natural range 0 to 255; --Message Count already stored
begin
if (res_n=ACT_RESET) or (drv_erase_rx='1') then
......@@ -354,8 +363,9 @@ begin
elsif(copy_counter<data_size)then -- Here the data words are stored
--Note: copy_counter is at least 3 here!! (3 to 18), therefore we have to decrease it by 3 -> increase the index by 96
memory(write_pointer) <= rec_data_in(607-((copy_counter)*32) downto 576-((copy_counter)*32));
--Optimized implementation of the storing with auxiliarly receive data RAM
memory(write_pointer) <= rec_dram_word;
memory_valid(write_pointer) <= '1';
write_pointer <= (write_pointer+1) mod buff_size;
copy_counter <= copy_counter+1;
......
......@@ -91,7 +91,6 @@ entity core_top is
--Recieve Buffer and Message Filter Interface--
-----------------------------------------------
signal rec_ident_out :out std_logic_vector(28 downto 0); --Message Identifier
signal rec_data_out :out std_logic_vector(511 downto 0); --Message Data (up to 64 bytes);
signal rec_dlc_out :out std_logic_vector(3 downto 0); --Data length code
signal rec_ident_type_out :out std_logic; --Recieved identifier type (0-BASE Format, 1-Extended Format);
signal rec_frame_type_out :out std_logic; --Recieved frame type (0-Normal CAN, 1- CAN FD)
......@@ -100,6 +99,8 @@ entity core_top is
signal rec_esi_out :out std_logic; --Error state indicator
signal rec_message_valid_out :out std_logic; --Output from acceptance filters (out_ident_valid) if message fits the filters
signal rec_message_ack_out :in std_logic; --Acknowledge for CAN Core about accepted data
signal rec_dram_word_out :out std_logic_vector(31 downto 0);
signal rec_dram_addr_out :in natural range 0 to 15;
-------------------------------
--Interrupt Manager Interface--
......@@ -264,7 +265,6 @@ entity core_top is
signal dec_one : std_logic;
--Protocol control signals
signal rec_data : std_logic_vector(511 downto 0);
signal rec_ident : std_logic_vector(28 downto 0);
signal rec_dlc : std_logic_vector(3 downto 0);
signal rec_is_rtr : std_logic;
......@@ -274,6 +274,8 @@ entity core_top is
signal rec_crc : std_logic_vector(20 downto 0); --Recieved CRC value
signal rec_esi : std_logic; --Recieved Error state indicator
signal ack_recieved_out : std_logic;
signal rec_dram_word : std_logic_vector(31 downto 0);
signal rec_dram_addr : natural range 0 to 15;
--CRC Interfaces
signal crc_enable : std_logic; --Transition from 0 to 1 erases the CRC and operation holds as long as enable=1
......@@ -344,13 +346,14 @@ begin
sync_control <= sync_control_int;
rec_ident_out <= rec_ident;
rec_data_out <= rec_data;
rec_dlc_out <= rec_dlc;
rec_ident_type_out <= rec_ident_type;
rec_frame_type_out <= rec_frame_type;
rec_is_rtr_out <= rec_is_rtr;
rec_brs_out <= rec_brs;
rec_esi_out <= rec_esi;
rec_dram_word_out <= rec_dram_word;
rec_dram_addr <= rec_dram_addr_out;
rec_message_valid_out <= rec_valid; --Confirmation about valid recieved data for RX Buffer
--rec_message_ack_out --NOTE: HandShake protocol with acknowledge not used in the end
......@@ -419,7 +422,6 @@ begin
tran_frame_valid_in=> tran_frame_valid_in,
tran_data_ack => tran_data_ack,
rec_data => rec_data,
rec_ident => rec_ident,
rec_dlc => rec_dlc,
rec_is_rtr => rec_is_rtr,
......@@ -428,6 +430,8 @@ begin
rec_brs => rec_brs,
rec_crc => rec_crc,
rec_esi => rec_esi,
rec_dram_word => rec_dram_word,
rec_dram_addr => rec_dram_addr,
OP_state => OP_state,
arbitration_lost => arbitration_lost,
......@@ -440,7 +444,7 @@ begin
CRC_Error => CRC_Error,
ack_Error => ack_Error,
unknown_state_Error => unknown_state_Error,
bit_stuff_Error_valid =>bit_stuff_Error_valid,
bit_stuff_Error_valid => bit_stuff_Error_valid,
inc_one => inc_one,
inc_eight => inc_eight,
......
......@@ -89,6 +89,15 @@ use work.CANconstants.all;
-- 12.1.2017 1. Added CRC fix for ISO FD CAN. CRC was stopped before the stuff count field. Due to this
-- Stuff count was not included into CRC which made the calculated CRC always wrong!
-- 2. Fixed CRC length for small FD frames to be always 17 instead of 15!
-- 29.11.2017 1. Optimized storing of received data. Data stored into 16*32 RAM (array) after each byte was
-- received. Since RX Buffer is reading the data serially, it does not need to have
-- the data available in parallel! Removed signal "rec_data_r" and replaced it with "rec_dram".
-- RX buffer now provides address signal which combinationally reads the data on RAM output!
-- This approach saved approx. 1000 LC combinationals of Altera device. No RAM was inferred,
-- and the memory was stored in LUT combinational memory! An additional effect of this change
-- is that Received Data are not erased in the SOF of next frame and thus it stays on the output
-- of CAN Core until it is rewritten by next data.
--
-------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------
......@@ -126,7 +135,6 @@ entity protocolControl is
-------------------------
--Recieved data output --
-------------------------
signal rec_data :out std_logic_vector(511 downto 0);
signal rec_ident :out std_logic_vector(28 downto 0);
signal rec_dlc :out std_logic_vector(3 downto 0);
signal rec_is_rtr :out std_logic;
......@@ -136,6 +144,10 @@ entity protocolControl is
signal rec_crc :out std_logic_vector(20 downto 0); --Recieved CRC value
signal rec_esi :out std_logic; --Recieved Error state indicator
--Added interface for aux SRAM
signal rec_dram_word :out std_logic_vector(31 downto 0);
signal rec_dram_addr :in natural range 0 to 15;
--------------------------------
--Operation mode FSM Interface--
--------------------------------
......@@ -302,7 +314,6 @@ entity protocolControl is
---------------------------
--Recieved data registers--
---------------------------
signal rec_data_r : std_logic_vector(511 downto 0);
signal rec_ident_r : std_logic_vector(28 downto 0);
signal rec_dlc_r : std_logic_vector(3 downto 0);
signal rec_is_rtr_r : std_logic;
......@@ -349,6 +360,15 @@ entity protocolControl is
signal stl_pointer : natural range 0 to 3; --Pointer for transcieving the stuf length field
signal data_size : natural range 0 to 511;
-- Signals for optimalization of data reception usage
-- Refer to Revision comment: 29.11.2017
type rec_data_RAM_type is array (0 to 15) of std_logic_vector(31 downto 0);
signal rec_data_sr : std_logic_vector(7 downto 0); --Shift register for data reception
signal rec_dram_ptr : natural range 0 to 7; --Register for counting received bytes in shift register
signal rec_dram_bind : natural range 0 to 3; --Byte index into RAM
signal rec_dram : rec_data_RAM_type;
-----------------------
--CRC field registers--
-----------------------
......@@ -448,7 +468,6 @@ begin
sync_control <= sync_control_r;
--Recieved data registers to output propagation
rec_data <= rec_data_r;
rec_ident <= rec_ident_r;
rec_dlc <= rec_dlc_r;
rec_is_rtr <= rec_is_rtr_r;
......@@ -486,6 +505,11 @@ begin
stuff_parity <= '0' when (dst_ctr mod 2)=0 else
'1';
-------------------------------------
-- Output of receive data RAM
-------------------------------------
rec_dram_word <= rec_dram(rec_dram_addr);
---------------------------------------
---------------------------------------
--Protocol control process
......@@ -563,13 +587,17 @@ begin
data_size <= 0;
--Nulling recieve registers
rec_data_r <= (OTHERS=>'0');
rec_ident_r <= (OTHERS=>'0');
rec_dlc_r <= (OTHERS=>'0');
rec_is_rtr_r <= '0';
rec_ident_type_r <= '0';
rec_frame_type_r <= '0';
-- Receive data RAM
rec_dram_ptr <= 0;
rec_dram_bind <= 0;
rec_data_sr <= (OTHERS => '0');
--Presetting the sampling point control
sp_control_r <= NOMINAL_SAMPLE;
ssp_reset_r <= '0';
......@@ -610,7 +638,6 @@ begin
fixed_destuff_r <= fixed_destuff_r;
destuff_length_r <= destuff_length_r;
stuff_error_enable_r <= stuff_error_enable_r;
rec_data_r <= rec_data_r;
rec_ident_r <= rec_ident_r;
rec_dlc_r <= rec_dlc_r;
rec_is_rtr_r <= rec_is_rtr_r;
......@@ -687,6 +714,10 @@ begin
rx_parity <= rx_parity;
rx_count_grey <= rx_count_grey;
rec_data_sr <= rec_data_sr;
rec_dram_ptr <= rec_dram_ptr;
rec_dram_bind <= rec_dram_bind;
if(drv_ena='0')then
PC_State <= off;
......@@ -781,7 +812,6 @@ begin
crc_enable_r <= '1';
--Erasing the recieved data registers
rec_data_r <= (OTHERS =>'0');
rec_ident_r <= (OTHERS =>'0');
rec_dlc_r <= (OTHERS =>'0');
rec_is_rtr_r <= '0';
......@@ -1258,10 +1288,17 @@ begin
PC_State <= error;
FSM_preset <= '1';
end case;
data_pointer <= 511;
if(OP_State=transciever and tran_frame_type=FD_CAN)then
sync_control_r <= NO_SYNC; --Transmitter shall not synchronize in data phase of CAN FD Frame!
end if;
--Receive RAM signals
rec_dram_ptr <= 0;
rec_dram_bind <= 0;
rec_data_sr <= (OTHERS => '0');
else
if(OP_State=transciever)then
......@@ -1273,9 +1310,31 @@ begin
end if;
if(rec_trig='1')then --Recieving data (also transmitter recieves the same data)
rec_data_r(data_pointer) <= data_rx;
-- Shift register and storing to local RAM
rec_data_sr <= rec_data_sr(6 downto 0)&data_rx;
rec_dram_ptr <= (rec_dram_ptr+1) mod 8;
-- If the whole byte was received
if (rec_dram_ptr=7) then
rec_dram_bind <= (rec_dram_bind+1) mod 4;
case rec_dram_bind is
when 0 =>
rec_dram(data_pointer/32) <= rec_data_sr(6 downto 0)&data_rx&"000000000000000000000000";
when 1 =>
rec_dram(data_pointer/32)(23 downto 0) <= rec_data_sr(6 downto 0)&data_rx&"0000000000000000";
when 2 =>
rec_dram(data_pointer/32)(15 downto 0) <= rec_data_sr(6 downto 0)&data_rx&"00000000";
when 3 =>
rec_dram(data_pointer/32)(7 downto 0) <= rec_data_sr(6 downto 0)&data_rx;
when others =>
report "Unknown state" severity error;
PC_State <= error;
end case;
end if;
if(data_pointer>511-data_size)then
--if(data_pointer>0)then
data_pointer <= data_pointer-1;
else
PC_State <= crc;
......
......@@ -167,6 +167,10 @@ entity CAN_top_level is
signal rec_message_ack : std_logic; --Acknowledge for CAN Core about accepted data
signal rec_esi : std_logic;
signal rec_dram_word : std_logic_vector(31 downto 0);
signal rec_dram_addr : natural range 0 to 15;
--RX Buffer <--> Message filters
signal out_ident_valid : std_logic; --Signal whenever identifier matches the filter identifiers
......@@ -300,7 +304,6 @@ begin
clk_sys => clk_sys,
res_n => res_n_int,
rec_ident_in => rec_ident_in,
rec_data_in => rec_data_in,
rec_dlc_in => rec_dlc_in,
rec_ident_type_in => rec_ident_type_in,
rec_frame_type_in => rec_frame_type_in,
......@@ -309,6 +312,8 @@ begin
rec_brs => rec_brs,
rec_esi => rec_esi,
rec_message_ack => rec_message_ack,
rec_dram_word => rec_dram_word,
rec_dram_addr => rec_dram_addr,
rx_buf_size => rx_buf_size,
rx_full => rx_full,
rx_empty => rx_empty,
......@@ -429,7 +434,6 @@ begin
tran_frame_valid_in => tran_frame_valid_out,
tran_data_ack_out => tran_data_ack,
rec_ident_out => rec_ident_in,
rec_data_out => rec_data_in,
rec_dlc_out => rec_dlc_in,
rec_ident_type_out => rec_ident_type_in,
rec_frame_type_out => rec_frame_type_in,
......@@ -438,6 +442,8 @@ begin
rec_esi_out => rec_esi,
rec_message_valid_out=> rec_message_valid,
rec_message_ack_out => rec_message_ack,
rec_dram_word_out => rec_dram_word,
rec_dram_addr_out => rec_dram_addr,
arbitration_lost_out => arbitration_lost,
wake_up_valid => wake_up_valid,
tx_finished => tx_finished,
......
......@@ -30,6 +30,8 @@ USE WORK.CANconstants.ALL;
--
-- 15.11.2017 Created file
-- 27.11.2017 Added "rst_sync" asynchronous rest synchroniser circuit
-- 29.11.2017 Removed "rec_data" between Protocol control and RX Buffer, replaced with rec_dram_word and
-- rec_dram_addr as part of resource optimization.
-------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------
......@@ -147,7 +149,6 @@ package CANcomponents is
signal res_n :in std_logic; --Async. reset
signal rec_ident_in :in std_logic_vector(28 downto 0); --Message Identifier
signal rec_data_in :in std_logic_vector(511 downto 0); --Message Data (up to 64 bytes);
signal rec_dlc_in :in std_logic_vector(3 downto 0); --Data length code
signal rec_ident_type_in :in std_logic; --Recieved identifier type (0-BASE Format, 1-Extended Format);
signal rec_frame_type_in :in std_logic; --Recieved frame type (0-Normal CAN, 1- CAN FD)
......@@ -157,6 +158,9 @@ package CANcomponents is
signal rec_esi :in std_logic; --Recieved error state indicator
signal rec_message_ack :out std_logic; --Acknowledge for CAN Core about accepted data
signal rec_dram_word :in std_logic_vector(31 downto 0);
signal rec_dram_addr :out natural range 0 to 15;
signal rx_buf_size :out std_logic_vector(7 downto 0); --Actual size of synthetised message buffer (in 32 bit words)
signal rx_full :out std_logic; --Signal whenever buffer is full
signal rx_empty :out std_logic; --Signal whenever buffer is empty
......@@ -345,7 +349,6 @@ package CANcomponents is
signal tran_data_ack_out :out std_logic; --Acknowledge from CAN core that acutal message was stored into internal buffer for transmitting
signal rec_ident_out :out std_logic_vector(28 downto 0); --Message Identifier
signal rec_data_out :out std_logic_vector(511 downto 0); --Message Data (up to 64 bytes);
signal rec_dlc_out :out std_logic_vector(3 downto 0); --Data length code
signal rec_ident_type_out :out std_logic; --Recieved identifier type (0-BASE Format, 1-Extended Format);
signal rec_frame_type_out :out std_logic; --Recieved frame type (0-Normal CAN, 1- CAN FD)
......@@ -354,6 +357,8 @@ package CANcomponents is
signal rec_esi_out :out std_logic; --Error state indicator
signal rec_message_valid_out:out std_logic;
signal rec_message_ack_out :in std_logic; --Acknowledge for CAN Core about accepted data
signal rec_dram_word_out :out std_logic_vector(31 downto 0);
signal rec_dram_addr_out :in natural range 0 to 15;
signal arbitration_lost_out :out std_logic; --Arbitration was lost input
signal wake_up_valid :out std_logic; --Wake up appeared
......@@ -655,7 +660,6 @@ end component;
signal tran_data_ack :out std_logic; --Acknowledge that the frame was stored
signal br_shifted :out std_logic; --Bit Rate Was Shifted
signal rec_data :out std_logic_vector(511 downto 0);
signal rec_ident :out std_logic_vector(28 downto 0);
signal rec_dlc :out std_logic_vector(3 downto 0);
signal rec_is_rtr :out std_logic;
......@@ -664,6 +668,10 @@ end component;
signal rec_brs :out std_logic;
signal rec_crc :out std_logic_vector(20 downto 0); --Recieved CRC value
signal rec_esi :out std_logic; --Recieved Error state indicator
--Added interface for aux SRAM
signal rec_dram_word :out std_logic_vector(31 downto 0);
signal rec_dram_addr :in natural range 0 to 15;
signal OP_state :in oper_mode_type; --Operation mode state
signal arbitration_lost :out std_logic; --Signal for Operational mode state mahine about loosing arbitration
......
......@@ -66,7 +66,6 @@ architecture rx_buf_unit_test of CAN_test is
signal clk_sys : std_logic:='0'; --System clock
signal res_n : std_logic:='0'; --Async. reset
signal rec_ident_in : std_logic_vector(28 downto 0); --Message Identifier
signal rec_data_in : std_logic_vector(511 downto 0); --Message Data (up to 64 bytes);
signal rec_dlc_in : std_logic_vector(3 downto 0); --Data length code
signal rec_ident_type_in : std_logic:='0'; --Recieved identifier type (0-BASE Format, 1-Extended Format);
signal rec_frame_type_in : std_logic:='0'; --Recieved frame type (0-Normal CAN, 1- CAN FD)
......@@ -77,6 +76,9 @@ architecture rx_buf_unit_test of CAN_test is
signal timestamp : std_logic_vector(63 downto 0):=(OTHERS =>'0');
signal drv_bus : std_logic_vector(1023 downto 0):=(OTHERS =>'0'); --Driving bus from registers
signal rec_dram_word : std_logic_vector(31 downto 0);
signal rec_dram_addr : natural range 0 to 15;
signal rec_message_ack_b : std_logic:='0'; --Acknowledge for CAN Core about accepted data
signal rx_buf_size_b : std_logic_vector(7 downto 0):=(OTHERS =>'0'); --Actual size of synthetised message buffer (in 32 bit words)
signal rx_full_b : std_logic:='0'; --Signal whenever buffer is full
......@@ -201,8 +203,8 @@ architecture rx_buf_unit_test of CAN_test is
if(data_overrun_b='1')then
was_inserted:=false;
else
was_inserted:=true;
end if;
was_inserted:=true;
end if;
-----------------------------------------------------------------------
--When frame was truly inserted then add it to the common input memory
......@@ -331,7 +333,8 @@ begin
clk_sys => clk_sys,
res_n => res_n ,
rec_ident_in => rec_ident_in,
rec_data_in => rec_data_in,
rec_dram_word => rec_dram_word,
rec_dram_addr => rec_dram_addr,
rec_dlc_in => rec_dlc_in,
rec_ident_type_in => rec_ident_type_in,
rec_frame_type_in => rec_frame_type_in,
......@@ -368,7 +371,8 @@ begin
-- clk_sys => clk_sys,
-- res_n => res_n ,
-- rec_ident_in => rec_ident_in,
-- rec_data_in => rec_data_in,
-- rec_dram_word => rec_dram_word,
-- rec_dram_addr => rec_dram_addr,
-- rec_dlc_in => rec_dlc_in,
-- rec_ident_type_in => rec_ident_type_in,
-- rec_frame_type_in => rec_frame_type_in,
......@@ -397,7 +401,6 @@ begin
--Connect input frame to stimuli generator
-------------------------------------------
rec_ident_in <= input_frame.rec_ident_in;
rec_data_in <= input_frame.rec_data_in;
rec_dlc_in <= input_frame.rec_dlc_in;
rec_ident_type_in <= input_frame.rec_ident_type_in;
rec_frame_type_in <= input_frame.rec_frame_type_in;
......@@ -406,6 +409,10 @@ begin
rec_esi <= input_frame.rec_esi;
rec_message_valid <= input_frame.rec_message_valid;
-- Change to RAM usage for internal data of Protocol control!
-- Only 32 bytes of data are provided at a time !!!
rec_dram_word <= input_frame.rec_data_in((rec_dram_addr+1)*32-1 downto rec_dram_addr*32);
---------------------------------
--Clock and timestamp generation
---------------------------------
......@@ -520,7 +527,6 @@ begin
end process;
---------------------------------
-- Data reader
---------------------------------
......@@ -546,7 +552,7 @@ begin
sanity_counter:=sanity_counter+1;
--There is nothing to read from the buffers...
if(sanity_counter=30)then
if(sanity_counter=50)then
sanity_check := false;
process_error(read_errs,error_beh,exit_imm_d);
log("There is nothing to read for too long!",error_l,log_level);
......
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