Commit c99a0cdf authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch '59-synthesis-warning-research' into 'master'

Resolve "Synthesis warning research"

Closes #59

See merge request illeondr/CAN_FD_IP_Core!130
parents 444bc2a9 4dc6a154
Pipeline #1568 failed with stages
in 45 minutes and 46 seconds
......@@ -228,7 +228,6 @@ entity txArbitrator is
-- Registered values for detection of change
signal select_buf_index_reg : natural range 0 to buf_count - 1;
signal select_buf_avail_reg : boolean;
-- State machine for following when the frame was already transmitted!
signal tx_arb_fsm : tx_arb_state_type;
......@@ -401,7 +400,6 @@ begin
int_txtb_index <= 0;
select_buf_index_reg <= 0;
select_buf_avail_reg <= false;
fsm_wait_state <= true;
txtb_pointer_meta <= to_integer(unsigned(
......@@ -423,7 +421,6 @@ begin
tran_frame_valid_com <= tran_frame_valid_com;
select_buf_index_reg <= select_buf_index;
select_buf_avail_reg <= select_buf_avail;
txtb_pointer_meta <= txtb_pointer_meta;
fsm_wait_state <= fsm_wait_state;
......
......@@ -53,7 +53,9 @@
-- will be needed to implement both ways still since ISO and
-- non-ISO FD will be changable via configuration bit!
-- 4.6.2016 Added drv_is_fd to cover differencce in highest bit of crc17
-- and crc21 polynomial
-- and crc21 polynomial.
-- 13.7.2018 Replaced "crc15_nxt", "crc17_nxt", "crc21_nxt" by
-- signals instead of variable inside process.
--------------------------------------------------------------------------------
Library ieee;
......@@ -118,6 +120,11 @@ entity canCRC is
-- ISO CAN FD or NON ISO CAN FD Value
signal drv_fd_type : std_logic;
-- Combinational signals for next value of CRC
signal crc15_nxt : std_logic;
signal crc17_nxt : std_logic;
signal crc21_nxt : std_logic;
end entity;
......@@ -128,6 +135,13 @@ begin
crc21 <= crc21_reg;
drv_fd_type <= drv_bus(DRV_FD_TYPE_INDEX);
----------------------------------------------------------------------------
-- Calculation of next CRC bit
----------------------------------------------------------------------------
crc15_nxt <= data_in xor crc15_reg(14);
crc17_nxt <= data_in xor crc17_reg(16);
crc21_nxt <= data_in xor crc21_reg(20);
----------------------------------------------------------------------------
-- Registering previous value of enable input to detec 0 to 1 transition
----------------------------------------------------------------------------
......@@ -144,11 +158,9 @@ begin
-- Calculation of CRC15 value
----------------------------------------------------------------------------
crc15_cycle : process(res_n, clk_sys)
variable crc15_nxt : std_logic;
begin
if (res_n = ACT_RESET) then
crc15_reg <= (OTHERS => '0');
crc15_nxt := '0';
elsif rising_edge(clk_sys) then
-- Erase the CRC value at the begining of calculation
......@@ -158,7 +170,6 @@ begin
-- Calculate the next value when triggered
if (enable = '1' and trig = '1') then
crc15_nxt := data_in xor crc15_reg(14);
------------------------------------------------------------
-- CRC calculation
......@@ -187,12 +198,10 @@ begin
-- Calculation of CRC17 value
----------------------------------------------------------------------------
crc17_cycle : process(res_n, clk_sys)
variable crc17_nxt : std_logic;
begin
if (res_n = '0') then
crc17_reg <= (OTHERS => '0');
crc17_reg(16) <= '1';
crc17_nxt := '0';
elsif rising_edge(clk_sys) then
-- Erase the CRC value at the begining of calculation
......@@ -207,7 +216,6 @@ begin
-- Calculate the next value only when triggered
if (enable = '1'and trig = '1') then
crc17_nxt := data_in xor crc17_reg(16);
------------------------------------------------------------
-- CRC calculation
......@@ -234,12 +242,10 @@ begin
-- Calculation of CRC21 value
----------------------------------------------------------------------------
crc21_cycle : process(res_n, clk_sys)
variable crc21_nxt : std_logic;
begin
if (res_n = '0') then
crc21_reg <= (OTHERS => '0');
crc21_reg(20) <= '1';
crc21_nxt := '0';
elsif rising_edge(clk_sys) then
-- Erase the CRC value at the begining of calculation
......@@ -254,7 +260,6 @@ begin
-- Calculate the next value only when triggered
if (enable = '1'and trig = '1') then
crc21_nxt := data_in xor crc21_reg(20);
------------------------------------------------------------
-- CRC calculation
......
......@@ -74,6 +74,11 @@
-- on the output of TX Arbitrator combinationally ! During the
-- transmission metadata will not change since TX arbitrator is
-- locked!
-- 13.7.2018 Removed obsolete "drv_bus_mon_ena". Bus monitoring mode (or
-- Listen only mode, it is the same thing) is realized by Protocol
-- Control which sets "int_loop_back_ena" to perform internal
-- loopback upon transmission of DOMINANT bit which should not
-- get to the bus!
--------------------------------------------------------------------------------
Library ieee;
......@@ -279,7 +284,6 @@ entity core_top is
signal drv_set_rx_ctr : std_logic;
signal drv_set_tx_ctr : std_logic;
signal drv_int_loopback_ena : std_logic;
signal drv_lom_ena : std_logic;
----------------------------------------------------------------------------
......@@ -314,7 +318,6 @@ entity core_top is
signal sp_control_int : std_logic_vector(1 downto 0);
signal ssp_reset_int : std_logic;
signal trv_delay_calib_int : std_logic;
signal bit_err_enable_int : std_logic;
-- Synchronisation control signal
signal sync_control_int : std_logic_vector(1 downto 0);
......@@ -510,7 +513,6 @@ entity core_top is
signal sync_nbt_del_2 : std_logic;
signal tran_trig_del_1 : std_logic;
signal tran_trig_del_2 : std_logic;
-- Bus traffic measurment
signal tx_counter : std_logic_vector(31 downto 0);
......@@ -694,7 +696,6 @@ begin
sp_control => sp_control_int,
ssp_reset => ssp_reset_int,
trv_delay_calib => trv_delay_calib_int,
bit_err_enable => bit_err_enable_int,
sof_pulse => sof_pulse_r
);
......@@ -881,39 +882,52 @@ begin
);
-- Temporary different data source of crc for transciever FD!!!
-- CRC calculated from transcieved data!!
----------------------------------------------------------------------------
-- CRC From RX Data can't be always calculated from RX Data! In case of
-- secondary sampling, bit length might be shorter than Propagation from TX
-- to RX over transceiver! Thus in case of secondary sampling, even CRC
-- from RX data is calculated from TX Data!
----------------------------------------------------------------------------
data_crc_wbs <= data_tx_int when sp_control_int = SECONDARY_SAMPLE else
data_rx_int;
data_crc_nbs <= data_tx_before_stuff when sp_control_int = SECONDARY_SAMPLE
else
data_destuffed ;
data_destuffed;
----------------------------------------------------------------------------
-- Driving bus aliases
----------------------------------------------------------------------------
drv_set_ctr_val <= drv_bus(DRV_SET_CTR_VAL_HIGH downto
DRV_SET_CTR_VAL_LOW);
drv_set_rx_ctr <= drv_bus(DRV_SET_RX_CTR_INDEX);
drv_set_tx_ctr <= drv_bus(DRV_SET_TX_CTR_INDEX);
drv_int_loopback_ena <= drv_bus(DRV_INT_LOOBACK_ENA_INDEX);
drv_lom_ena <= drv_bus(DRV_BUS_MON_ENA_INDEX);
----------------------------------------------------------------------------
-- Output propagation
----------------------------------------------------------------------------
arbitration_lost_out <= arbitration_lost;
tx_finished <= tran_valid;
sof_pulse <= sof_pulse_r;
bus_off_start <= bus_off_start_int;
br_shifted <= br_shifted_int;
ssp_reset <= ssp_reset_int;
trv_delay_calib <= trv_delay_calib_int;
---------------------
--CRC Multiplexing --
---------------------
----------------------------------------------------------------------------
-- CRC Multiplexors.
--
-- CRC data sources like so:
-- 1. Transceiver, CAN FD Frame -> TX Data after bit stuffing.
-- 2. Transceiver, CAN 2.0 Frame -> TX Data before bit stuffing.
-- 3. Receiver, CAN FD Frame -> RX Data before bit destuffing.
-- 4. Receiver, CAN 2.0 Frame -> RX Data after bit destuffing.
----------------------------------------------------------------------------
crc15 <= crc15_wbs_tx when (OP_State = transciever and
tran_frame_type = FD_CAN) else
......@@ -966,7 +980,7 @@ begin
----------------------------------------------------------------------------
-- Trigger signals multiplexing
-- Trigger signals registering. Creating delayed signals
----------------------------------------------------------------------------
trig_cr : process(clk_sys, res_n)
begin
......@@ -974,17 +988,22 @@ begin
sync_dbt_del_2 <= '0';
sync_nbt_del_2 <= '0';
tran_trig_del_1 <= '0';
tran_trig_del_2 <= '0';
bds_trig_del_1 <= '0';
elsif rising_edge(clk_sys) then
sync_dbt_del_2 <= sync_dbt_del_1;
sync_nbt_del_2 <= sync_nbt_del_1;
tran_trig_del_1 <= tran_trig;
tran_trig_del_2 <= tran_trig_del_1;
bds_trig_del_1 <= bds_trig;
end if;
end process;
-- Note: when secondary sampling point is used transcieve signals
-- remains the same
----------------------------------------------------------------------------
-- Multiplexors for TX/RX Triggers. These Triggers are used to
-- transmitt/receive data from/to Protocol Control.
-- Note that Secondary sampling point is used only by Bus sync for bit
-- error detection!
----------------------------------------------------------------------------
tran_trig <= sync_nbt and (not data_halt)
when (sp_control_int = NOMINAL_SAMPLE) else
......@@ -1007,12 +1026,13 @@ begin
'0';
----------------------------------------------------------------------------
--Note: Due to not functioning Secondary sample point normal data phasee
-- sample point used!!! Secondary sample point used only for bit error
-- detection during Data Phase!!!
-- Multiplexors for Bit Stuffing/Destuffing triggers. These are used to
-- process data by Bit Stuffing/Destuffing circuits.
-- Note that Secondary sampling point is used only by Bus sync for bit
-- error detection!
----------------------------------------------------------------------------
bs_trig <= sync_nbt_del_1 when (sp_control_int = NOMINAL_SAMPLE) else
sync_dbt_del_1 when (sp_control_int = DATA_SAMPLE) else
sync_dbt_del_1 when (sp_control_int = SECONDARY_SAMPLE) else
......@@ -1023,6 +1043,7 @@ begin
sync_dbt_del_1 when (sp_control_int = SECONDARY_SAMPLE) else
'0';
----------------------------------------------------------------------------
-- According to CAN FD specification fixed stuff bits are never included in
-- CRC calculation. With NON ISO there is no problem. CRC calculation in the
......@@ -1043,16 +1064,6 @@ begin
bds_trig_del_1;
bds_del_proc : process(clk_sys, res_n)
begin
if (res_n = ACT_RESET) then
bds_trig_del_1 <= '0';
elsif rising_edge(clk_sys) then
bds_trig_del_1 <= bds_trig;
end if;
end process;
crc_nbs_trig <= (sync_dbt and (not data_halt))
when (sp_control_int = SECONDARY_SAMPLE)
else rec_trig;
......@@ -1067,8 +1078,19 @@ begin
error_passive_changed <= error_passive_changed_int;
error_warning_limit <= error_warning_limit_int;
----------------------------------------------------------------------------
-- Internal loopback multiplexing
-- Data Received by Protocol control are from Bit Destuffing, apart from
-- following cases:
-- 1. Internal loopback is set by Protocol control (due to some special
-- mode such as LOM), or rerouting acknowledge internally in case of
-- STM mode.
-- 2. Internal loopback is permanently turned on from SW for debugging!
-- 3. Secondary sampling point is set. This is ONLY in Data phase of
-- CAN FD Transmitter after Bit rate shift! This is needed for proper
-- reception of own data in the same bit! Note that Bit error in this
-- case is detected by Bus Sync circuit which has shift registers for
-- secondary sampling point!
----------------------------------------------------------------------------
data_rx_int <= data_tx_from_PC when (int_loop_back_ena = '1' or
drv_int_loopback_ena = '1' or
......@@ -1077,14 +1099,18 @@ begin
data_rx;
----------------------------------------------------------------------------
--Note: int_loop_back_ena is for bus monitoring mode. drv_int_loopback_ena
-- is for internal loopback set by user!
-- Data transmitted by Protocol control are sent out of CAN Core to
-- Bit stuffing, apart from following cases:
-- 1. Protocol Control has "int_loop_back_ena" which forbids bit to be
-- transmitted further!
-- 2. User has set (for debugging purposes) permanent Internal Loopback!
----------------------------------------------------------------------------
data_tx_before_stuff <= RECESSIVE when (int_loop_back_ena = '1' or
drv_int_loopback_ena = '1')
else
data_tx_from_PC;
----------------------------------------------------------------------------
-- Bus traffic measurement
----------------------------------------------------------------------------
......@@ -1099,19 +1125,25 @@ begin
if (drv_set_rx_ctr = '1') then
rx_counter <= drv_set_ctr_val;
elsif(rec_valid='1')then
rx_counter <= std_logic_vector(unsigned(rx_counter) + 1);
elsif (rec_valid = '1') then
rx_counter <= std_logic_vector(to_unsigned(
to_integer(unsigned(rx_counter)) + 1,
rx_counter'length));
end if;
if (drv_set_tx_ctr = '1') then
tx_counter <= drv_set_ctr_val;
elsif (tran_valid = '1') then
tx_counter <= std_logic_vector(unsigned(tx_counter) + 1);
tx_counter <= std_logic_vector(to_unsigned(
to_integer(unsigned(tx_counter)) + 1,
tx_counter'length));
end if;
end if;
end process;
----------------------------------------------------------------------------
-- STATUS Bus Implementation
----------------------------------------------------------------------------
......
......@@ -216,7 +216,7 @@
-- 10.7.2018 Changed length of data length field for DLC > 8 in case of
-- CAN 2.0 frame! For CAN 2.0 frame DLC higher than 8 should be
-- interpreted as 8!
-- 13.7.2018 Removed "unknown_state_Error_r" since it was unused. Unified
-- 13.7.2018 1. Removed "unknown_state_Error_r" since it was unused. Unified
-- all "when others" statements to go to "error" state an cause
-- error frame transmission! This is however synthesis tool
-- dependent! If FSM synthesis on invalid state (e.g. glitch)
......@@ -228,6 +228,12 @@
-- "internal" error, which would cause transmission of error
-- frame! Such a behaviour is not defined by standard, but it
-- is logical to do it like so!
-- 2. Removed "bit_err_ena" since it was unused! Selection of
-- valid bit error is done by Fault confinement!
-- 13.8.2018 fixed_CRC_FD removed since fixed stuff bit before CRC field
-- is inserted by Bit Stuffing and discarded by Bit Destuffing
-- automatically upon detection of 0 -> 1 transition on
-- "fixed_stuff" / "fixed_destuff" signals.
--------------------------------------------------------------------------------
Library ieee;
......@@ -418,11 +424,6 @@ entity protocolControl is
--Calibration command for transciever delay compenstation (counter)
signal trv_delay_calib :out std_logic;
--Bit Error detection enable (Ex. disabled when recieving data)
signal bit_err_enable :out std_logic;
--Note: In the end bit Error detection is always enabled, Fault confinement
-- module decides whenever the bit Error is VALID!!!
--Synchronisation edge validated by prescaler!!!
signal hard_sync_edge :in std_logic;
......@@ -514,7 +515,6 @@ entity protocolControl is
signal trv_delay_calib_r : std_logic;
--Bit Error detection enable (Ex. disabled when recieving data)
signal bit_err_enable_r : std_logic;
signal sync_control_r : std_logic_vector(1 downto 0);
signal alc_r : std_logic_vector(7 downto 0);
......@@ -616,9 +616,6 @@ entity protocolControl is
-- state based on type of transcieved/recieved frame
signal FSM_preset : std_logic;
--State machine for managing the bits inside the control field
signal control_state : control_type;
--Register for transcieving the data in control field bits
signal ctrl_tran_reg : std_logic_vector(7 downto 0);
......@@ -665,12 +662,6 @@ entity protocolControl is
--Recieved CRC matches the calculated one
signal crc_check : std_logic;
--Fixed stuff bit before CRC of FD Frame
signal fixed_CRC_FD : std_logic;
--Fixed stuff bit before CRC of FD Frame, for reciever
signal fixed_CRC_FD_rec : std_logic;
--Pointer for transcieving the stuf length field
signal stl_pointer : natural range 0 to 3;
......@@ -782,7 +773,6 @@ begin
sp_control <= sp_control_r;
ssp_reset <= ssp_reset_r;
trv_delay_calib <= trv_delay_calib_r;
bit_err_enable <= bit_err_enable_r;
--Synchronisation control
sync_control <= sync_control_r;
......@@ -1001,9 +991,6 @@ begin
sp_control_r <= NOMINAL_SAMPLE;
ssp_reset_r <= '0';
trv_delay_calib_r <= '0';
bit_err_enable_r <= '0';
fixed_CRC_FD <= '0';
fixed_CRC_FD_rec <= '0';
sync_control_r <= NO_SYNC;
--Error presetting
......@@ -1081,9 +1068,6 @@ begin
--correct state
FSM_preset <= FSM_preset;
--State machine for managing the bits inside the control field
control_state <= control_state;
--Register for transcieving the data in control field bits
ctrl_tran_reg <= ctrl_tran_reg;
......@@ -1108,8 +1092,6 @@ begin
sec_ack <= sec_ack;
interm_state <= interm_state;
err_frame_state <= err_frame_state;
fixed_CRC_FD <= fixed_CRC_FD;
fixed_CRC_FD_rec <= fixed_CRC_FD_rec;
err_pas_bit_val <= err_pas_bit_val;
data_tx_index <= data_tx_index;
......@@ -1143,7 +1125,6 @@ begin
sp_control_r <= sp_control_r;
ssp_reset_r <= '0';
trv_delay_calib_r <= trv_delay_calib_r;
bit_err_enable_r <= bit_err_enable_r;
sync_control_r <= sync_control_r;
......@@ -1294,7 +1275,6 @@ begin
-- Bus synchronisation settings
sp_control_r <= NOMINAL_SAMPLE;
bit_err_enable_r <= '1';
-- Configuration of Bit Destuffing (Both transciever and reciever)
destuff_enable_r <= '1';
......@@ -1661,13 +1641,6 @@ begin
if (FSM_preset = '1') then
FSM_preset <= '0';
----------------------------------------------------------------
-- Enable Bit Error detection. From now on everything that
-- we transceive, we must also receive (Either by NOMINAL or
-- SECONDARY sampling).
----------------------------------------------------------------
bit_err_enable_r <= '1';
----------------------------------------------------------------
-- Calculate real length of data field, which does not
-- always correspond to DLC!
......@@ -2234,8 +2207,6 @@ begin
to_unsigned(FD_STUFF_LENGTH, 3));
destuff_length_r <= std_logic_vector(
to_unsigned(FD_STUFF_LENGTH, 3));
fixed_CRC_FD <= '1';
fixed_CRC_FD_rec <= '1';
----------------------------------------------------------------
-- Go to stuff count transmission if ISO FD is configured.
......@@ -2249,8 +2220,6 @@ begin
end if;
else
fixed_CRC_FD <= '0';
fixed_CRC_FD_rec <= '0';
crc_state <= real_crc;
crc_enable_r <= '0';
end if;
......
......@@ -215,10 +215,6 @@ entity CAN_top_level is
signal rx_store_data_valid : std_logic;
signal rec_message_store : std_logic;
-- With new RX Buffer commands, ID valid input to message filter can be constantly valid!
signal mess_filt_input_valid : std_logic := '1';
----------------------------------------------------------------------------
-- Registers <--> TX Buffer, TXT Buffer
----------------------------------------------------------------------------
......@@ -650,8 +646,13 @@ begin
ident_type => rec_ident_type_in,
frame_type => rec_frame_type_in,
-- Identifier comparison can be done when metadata are received!
rec_ident_valid => mess_filt_input_valid,
------------------------------------------------------------------------
-- All commands on RX Buffer are generated by Protocol control when
-- ID is already received (between CONTROL and EOF), thus ID
-- comparison can be enabled always!
------------------------------------------------------------------------
rec_ident_valid => '1',
drv_bus => drv_bus,
out_ident_valid => out_ident_valid
);
......@@ -839,6 +840,7 @@ begin
log_write_pointer <= (others => '0');
log_read_pointer <= (others => '0');
log_size <= (others => '0');
log_state_out <= config;
end generate LOG_GEN2;
--Bit time clock output propagation
......
......@@ -671,7 +671,6 @@ package CANcomponents is
signal sp_control : out std_logic_vector(1 downto 0);
signal ssp_reset : out std_logic;
signal trv_delay_calib : out std_logic;
signal bit_err_enable : out std_logic;
signal hard_sync_edge : in std_logic;
signal sof_pulse : out std_logic
);
......
......@@ -202,18 +202,6 @@ package CANconstants is
one_bit
);
-- State machine type for sending control field bits
-- Note: control_type is only for sending. For recieving frame
-- type is unknown until EDL bit
type control_type is (
r0,
r1,
edl,
brs,
esi,
dlc
);
-- Within ISO CAN FD new field stuff count is needed!
type crc_type is(
stuff_count,
......
......@@ -298,9 +298,6 @@ architecture Protocol_Control_unit_test of CAN_test is
-- Calibration command for transciever delay compenstation
signal trv_delay_calib_1 : std_logic;
-- Bit Error detection enable (Ex. disabled when recieving data)
signal bit_err_enable_1 : std_logic;
-- Synchronisation edge validated by prescaler!!!
signal hard_sync_edge_1 : std_logic;
......@@ -465,9 +462,6 @@ architecture Protocol_Control_unit_test of CAN_test is
-- Calibration command for transciever delay compenstation
signal trv_delay_calib_2 : std_logic;
-- Bit Error detection enable (Ex. disabled when recieving data)
signal bit_err_enable_2 : std_logic;
-- Synchronisation edge validated by prescaler!!!
signal hard_sync_edge_2 : std_logic;
......@@ -873,7 +867,6 @@ begin
sp_control => sp_control_1,
ssp_reset => ssp_reset_1,
trv_delay_calib => trv_delay_calib_1,
bit_err_enable => bit_err_enable_1,
hard_sync_edge => hard_sync_edge_1,
sof_pulse => sof_pulse_1
);
......@@ -948,7 +941,6 @@ begin
sp_control => sp_control_2,
ssp_reset => ssp_reset_2,
trv_delay_calib => trv_delay_calib_2,
bit_err_enable => bit_err_enable_2,
hard_sync_edge => hard_sync_edge_2,
sof_pulse => sof_pulse_2
);
......
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