Commit c99a0cdf authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch '59-synthesis-warning-research' into 'master'

Resolve "Synthesis warning research"

Closes #59

See merge request illeondr/CAN_FD_IP_Core!130
parents 444bc2a9 4dc6a154
Pipeline #1568 failed with stages
in 45 minutes and 46 seconds
...@@ -228,7 +228,6 @@ entity txArbitrator is ...@@ -228,7 +228,6 @@ entity txArbitrator is
-- Registered values for detection of change -- Registered values for detection of change
signal select_buf_index_reg : natural range 0 to buf_count - 1; signal select_buf_index_reg : natural range 0 to buf_count - 1;
signal select_buf_avail_reg : boolean;
-- State machine for following when the frame was already transmitted! -- State machine for following when the frame was already transmitted!
signal tx_arb_fsm : tx_arb_state_type; signal tx_arb_fsm : tx_arb_state_type;
...@@ -401,7 +400,6 @@ begin ...@@ -401,7 +400,6 @@ begin
int_txtb_index <= 0; int_txtb_index <= 0;
select_buf_index_reg <= 0; select_buf_index_reg <= 0;
select_buf_avail_reg <= false;
fsm_wait_state <= true; fsm_wait_state <= true;
txtb_pointer_meta <= to_integer(unsigned( txtb_pointer_meta <= to_integer(unsigned(
...@@ -423,7 +421,6 @@ begin ...@@ -423,7 +421,6 @@ begin
tran_frame_valid_com <= tran_frame_valid_com; tran_frame_valid_com <= tran_frame_valid_com;
select_buf_index_reg <= select_buf_index; select_buf_index_reg <= select_buf_index;
select_buf_avail_reg <= select_buf_avail;
txtb_pointer_meta <= txtb_pointer_meta; txtb_pointer_meta <= txtb_pointer_meta;
fsm_wait_state <= fsm_wait_state; fsm_wait_state <= fsm_wait_state;
......
...@@ -53,7 +53,9 @@ ...@@ -53,7 +53,9 @@
-- will be needed to implement both ways still since ISO and -- will be needed to implement both ways still since ISO and
-- non-ISO FD will be changable via configuration bit! -- non-ISO FD will be changable via configuration bit!
-- 4.6.2016 Added drv_is_fd to cover differencce in highest bit of crc17 -- 4.6.2016 Added drv_is_fd to cover differencce in highest bit of crc17
-- and crc21 polynomial -- and crc21 polynomial.
-- 13.7.2018 Replaced "crc15_nxt", "crc17_nxt", "crc21_nxt" by
-- signals instead of variable inside process.
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Library ieee; Library ieee;
...@@ -116,7 +118,12 @@ entity canCRC is ...@@ -116,7 +118,12 @@ entity canCRC is
signal start_reg : std_logic; signal start_reg : std_logic;
-- ISO CAN FD or NON ISO CAN FD Value -- ISO CAN FD or NON ISO CAN FD Value
signal drv_fd_type : std_logic; signal drv_fd_type : std_logic;
-- Combinational signals for next value of CRC
signal crc15_nxt : std_logic;
signal crc17_nxt : std_logic;
signal crc21_nxt : std_logic;
end entity; end entity;
...@@ -127,6 +134,13 @@ begin ...@@ -127,6 +134,13 @@ begin
crc17 <= crc17_reg; crc17 <= crc17_reg;
crc21 <= crc21_reg; crc21 <= crc21_reg;
drv_fd_type <= drv_bus(DRV_FD_TYPE_INDEX); drv_fd_type <= drv_bus(DRV_FD_TYPE_INDEX);
----------------------------------------------------------------------------
-- Calculation of next CRC bit
----------------------------------------------------------------------------
crc15_nxt <= data_in xor crc15_reg(14);
crc17_nxt <= data_in xor crc17_reg(16);
crc21_nxt <= data_in xor crc21_reg(20);
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Registering previous value of enable input to detec 0 to 1 transition -- Registering previous value of enable input to detec 0 to 1 transition
...@@ -144,11 +158,9 @@ begin ...@@ -144,11 +158,9 @@ begin
-- Calculation of CRC15 value -- Calculation of CRC15 value
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
crc15_cycle : process(res_n, clk_sys) crc15_cycle : process(res_n, clk_sys)
variable crc15_nxt : std_logic;
begin begin
if (res_n = ACT_RESET) then if (res_n = ACT_RESET) then
crc15_reg <= (OTHERS => '0'); crc15_reg <= (OTHERS => '0');
crc15_nxt := '0';
elsif rising_edge(clk_sys) then elsif rising_edge(clk_sys) then
-- Erase the CRC value at the begining of calculation -- Erase the CRC value at the begining of calculation
...@@ -158,7 +170,6 @@ begin ...@@ -158,7 +170,6 @@ begin
-- Calculate the next value when triggered -- Calculate the next value when triggered
if (enable = '1' and trig = '1') then if (enable = '1' and trig = '1') then
crc15_nxt := data_in xor crc15_reg(14);
------------------------------------------------------------ ------------------------------------------------------------
-- CRC calculation -- CRC calculation
...@@ -187,12 +198,10 @@ begin ...@@ -187,12 +198,10 @@ begin
-- Calculation of CRC17 value -- Calculation of CRC17 value
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
crc17_cycle : process(res_n, clk_sys) crc17_cycle : process(res_n, clk_sys)
variable crc17_nxt : std_logic;
begin begin
if (res_n = '0') then if (res_n = '0') then
crc17_reg <= (OTHERS => '0'); crc17_reg <= (OTHERS => '0');
crc17_reg(16) <= '1'; crc17_reg(16) <= '1';
crc17_nxt := '0';
elsif rising_edge(clk_sys) then elsif rising_edge(clk_sys) then
-- Erase the CRC value at the begining of calculation -- Erase the CRC value at the begining of calculation
...@@ -207,7 +216,6 @@ begin ...@@ -207,7 +216,6 @@ begin
-- Calculate the next value only when triggered -- Calculate the next value only when triggered
if (enable = '1'and trig = '1') then if (enable = '1'and trig = '1') then
crc17_nxt := data_in xor crc17_reg(16);
------------------------------------------------------------ ------------------------------------------------------------
-- CRC calculation -- CRC calculation
...@@ -234,12 +242,10 @@ begin ...@@ -234,12 +242,10 @@ begin
-- Calculation of CRC21 value -- Calculation of CRC21 value
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
crc21_cycle : process(res_n, clk_sys) crc21_cycle : process(res_n, clk_sys)
variable crc21_nxt : std_logic;
begin begin
if (res_n = '0') then if (res_n = '0') then
crc21_reg <= (OTHERS => '0'); crc21_reg <= (OTHERS => '0');
crc21_reg(20) <= '1'; crc21_reg(20) <= '1';
crc21_nxt := '0';
elsif rising_edge(clk_sys) then elsif rising_edge(clk_sys) then
-- Erase the CRC value at the begining of calculation -- Erase the CRC value at the begining of calculation
...@@ -254,7 +260,6 @@ begin ...@@ -254,7 +260,6 @@ begin
-- Calculate the next value only when triggered -- Calculate the next value only when triggered
if (enable = '1'and trig = '1') then if (enable = '1'and trig = '1') then
crc21_nxt := data_in xor crc21_reg(20);
------------------------------------------------------------ ------------------------------------------------------------
-- CRC calculation -- CRC calculation
......
...@@ -74,6 +74,11 @@ ...@@ -74,6 +74,11 @@
-- on the output of TX Arbitrator combinationally ! During the -- on the output of TX Arbitrator combinationally ! During the
-- transmission metadata will not change since TX arbitrator is -- transmission metadata will not change since TX arbitrator is
-- locked! -- locked!
-- 13.7.2018 Removed obsolete "drv_bus_mon_ena". Bus monitoring mode (or
-- Listen only mode, it is the same thing) is realized by Protocol
-- Control which sets "int_loop_back_ena" to perform internal
-- loopback upon transmission of DOMINANT bit which should not
-- get to the bus!
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Library ieee; Library ieee;
...@@ -279,7 +284,6 @@ entity core_top is ...@@ -279,7 +284,6 @@ entity core_top is
signal drv_set_rx_ctr : std_logic; signal drv_set_rx_ctr : std_logic;
signal drv_set_tx_ctr : std_logic; signal drv_set_tx_ctr : std_logic;
signal drv_int_loopback_ena : std_logic; signal drv_int_loopback_ena : std_logic;
signal drv_lom_ena : std_logic;
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
...@@ -314,7 +318,6 @@ entity core_top is ...@@ -314,7 +318,6 @@ entity core_top is
signal sp_control_int : std_logic_vector(1 downto 0); signal sp_control_int : std_logic_vector(1 downto 0);
signal ssp_reset_int : std_logic; signal ssp_reset_int : std_logic;
signal trv_delay_calib_int : std_logic; signal trv_delay_calib_int : std_logic;
signal bit_err_enable_int : std_logic;
-- Synchronisation control signal -- Synchronisation control signal
signal sync_control_int : std_logic_vector(1 downto 0); signal sync_control_int : std_logic_vector(1 downto 0);
...@@ -510,7 +513,6 @@ entity core_top is ...@@ -510,7 +513,6 @@ entity core_top is
signal sync_nbt_del_2 : std_logic; signal sync_nbt_del_2 : std_logic;
signal tran_trig_del_1 : std_logic; signal tran_trig_del_1 : std_logic;
signal tran_trig_del_2 : std_logic;
-- Bus traffic measurment -- Bus traffic measurment
signal tx_counter : std_logic_vector(31 downto 0); signal tx_counter : std_logic_vector(31 downto 0);
...@@ -694,7 +696,6 @@ begin ...@@ -694,7 +696,6 @@ begin
sp_control => sp_control_int, sp_control => sp_control_int,
ssp_reset => ssp_reset_int, ssp_reset => ssp_reset_int,
trv_delay_calib => trv_delay_calib_int, trv_delay_calib => trv_delay_calib_int,
bit_err_enable => bit_err_enable_int,
sof_pulse => sof_pulse_r sof_pulse => sof_pulse_r
); );
...@@ -880,40 +881,53 @@ begin ...@@ -880,40 +881,53 @@ begin
dst_ctr => dst_ctr dst_ctr => dst_ctr
); );
-- Temporary different data source of crc for transciever FD!!!
-- CRC calculated from transcieved data!! ----------------------------------------------------------------------------
-- CRC From RX Data can't be always calculated from RX Data! In case of
-- secondary sampling, bit length might be shorter than Propagation from TX
-- to RX over transceiver! Thus in case of secondary sampling, even CRC
-- from RX data is calculated from TX Data!
----------------------------------------------------------------------------
data_crc_wbs <= data_tx_int when sp_control_int = SECONDARY_SAMPLE else data_crc_wbs <= data_tx_int when sp_control_int = SECONDARY_SAMPLE else
data_rx_int; data_rx_int;
data_crc_nbs <= data_tx_before_stuff when sp_control_int = SECONDARY_SAMPLE data_crc_nbs <= data_tx_before_stuff when sp_control_int = SECONDARY_SAMPLE
else else
data_destuffed ; data_destuffed;
----------------------------------------------------------------------------
-- Driving bus aliases -- Driving bus aliases
----------------------------------------------------------------------------
drv_set_ctr_val <= drv_bus(DRV_SET_CTR_VAL_HIGH downto drv_set_ctr_val <= drv_bus(DRV_SET_CTR_VAL_HIGH downto
DRV_SET_CTR_VAL_LOW); DRV_SET_CTR_VAL_LOW);
drv_set_rx_ctr <= drv_bus(DRV_SET_RX_CTR_INDEX); drv_set_rx_ctr <= drv_bus(DRV_SET_RX_CTR_INDEX);
drv_set_tx_ctr <= drv_bus(DRV_SET_TX_CTR_INDEX); drv_set_tx_ctr <= drv_bus(DRV_SET_TX_CTR_INDEX);
drv_int_loopback_ena <= drv_bus(DRV_INT_LOOBACK_ENA_INDEX); drv_int_loopback_ena <= drv_bus(DRV_INT_LOOBACK_ENA_INDEX);
drv_lom_ena <= drv_bus(DRV_BUS_MON_ENA_INDEX);
----------------------------------------------------------------------------
-- Output propagation -- Output propagation
----------------------------------------------------------------------------
arbitration_lost_out <= arbitration_lost; arbitration_lost_out <= arbitration_lost;
tx_finished <= tran_valid; tx_finished <= tran_valid;
sof_pulse <= sof_pulse_r; sof_pulse <= sof_pulse_r;
bus_off_start <= bus_off_start_int; bus_off_start <= bus_off_start_int;
br_shifted <= br_shifted_int; br_shifted <= br_shifted_int;
ssp_reset <= ssp_reset_int; ssp_reset <= ssp_reset_int;
trv_delay_calib <= trv_delay_calib_int; trv_delay_calib <= trv_delay_calib_int;
---------------------
--CRC Multiplexing -- ----------------------------------------------------------------------------
--------------------- -- CRC Multiplexors.
--
-- CRC data sources like so:
-- 1. Transceiver, CAN FD Frame -> TX Data after bit stuffing.
-- 2. Transceiver, CAN 2.0 Frame -> TX Data before bit stuffing.
-- 3. Receiver, CAN FD Frame -> RX Data before bit destuffing.
-- 4. Receiver, CAN 2.0 Frame -> RX Data after bit destuffing.
----------------------------------------------------------------------------
crc15 <= crc15_wbs_tx when (OP_State = transciever and crc15 <= crc15_wbs_tx when (OP_State = transciever and
tran_frame_type = FD_CAN) else tran_frame_type = FD_CAN) else
...@@ -958,7 +972,7 @@ begin ...@@ -958,7 +972,7 @@ begin
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Multiplexing of stuff counter and destuff counter -- Multiplexing of stuff counter and destuff counter
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
st_ctr_resolved <= dst_ctr when (OP_State = reciever) else st_ctr_resolved <= dst_ctr when (OP_State = reciever) else
bst_ctr when (OP_State = transciever) else bst_ctr when (OP_State = transciever) else
...@@ -966,7 +980,7 @@ begin ...@@ -966,7 +980,7 @@ begin
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Trigger signals multiplexing -- Trigger signals registering. Creating delayed signals
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
trig_cr : process(clk_sys, res_n) trig_cr : process(clk_sys, res_n)
begin begin
...@@ -974,17 +988,22 @@ begin ...@@ -974,17 +988,22 @@ begin
sync_dbt_del_2 <= '0'; sync_dbt_del_2 <= '0';
sync_nbt_del_2 <= '0'; sync_nbt_del_2 <= '0';
tran_trig_del_1 <= '0'; tran_trig_del_1 <= '0';
tran_trig_del_2 <= '0'; bds_trig_del_1 <= '0';
elsif rising_edge(clk_sys) then elsif rising_edge(clk_sys) then
sync_dbt_del_2 <= sync_dbt_del_1; sync_dbt_del_2 <= sync_dbt_del_1;
sync_nbt_del_2 <= sync_nbt_del_1; sync_nbt_del_2 <= sync_nbt_del_1;
tran_trig_del_1 <= tran_trig; tran_trig_del_1 <= tran_trig;
tran_trig_del_2 <= tran_trig_del_1; bds_trig_del_1 <= bds_trig;
end if; end if;
end process; end process;
-- Note: when secondary sampling point is used transcieve signals
-- remains the same ----------------------------------------------------------------------------
-- Multiplexors for TX/RX Triggers. These Triggers are used to
-- transmitt/receive data from/to Protocol Control.
-- Note that Secondary sampling point is used only by Bus sync for bit
-- error detection!
----------------------------------------------------------------------------
tran_trig <= sync_nbt and (not data_halt) tran_trig <= sync_nbt and (not data_halt)
when (sp_control_int = NOMINAL_SAMPLE) else when (sp_control_int = NOMINAL_SAMPLE) else
...@@ -1006,13 +1025,14 @@ begin ...@@ -1006,13 +1025,14 @@ begin
when (sp_control_int = SECONDARY_SAMPLE) else when (sp_control_int = SECONDARY_SAMPLE) else
'0'; '0';
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
--Note: Due to not functioning Secondary sample point normal data phasee -- Multiplexors for Bit Stuffing/Destuffing triggers. These are used to
-- sample point used!!! Secondary sample point used only for bit error -- process data by Bit Stuffing/Destuffing circuits.
-- detection during Data Phase!!! -- Note that Secondary sampling point is used only by Bus sync for bit
-- error detection!
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
bs_trig <= sync_nbt_del_1 when (sp_control_int = NOMINAL_SAMPLE) else bs_trig <= sync_nbt_del_1 when (sp_control_int = NOMINAL_SAMPLE) else
sync_dbt_del_1 when (sp_control_int = DATA_SAMPLE) else sync_dbt_del_1 when (sp_control_int = DATA_SAMPLE) else
sync_dbt_del_1 when (sp_control_int = SECONDARY_SAMPLE) else sync_dbt_del_1 when (sp_control_int = SECONDARY_SAMPLE) else
...@@ -1023,6 +1043,7 @@ begin ...@@ -1023,6 +1043,7 @@ begin
sync_dbt_del_1 when (sp_control_int = SECONDARY_SAMPLE) else sync_dbt_del_1 when (sp_control_int = SECONDARY_SAMPLE) else
'0'; '0';
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- According to CAN FD specification fixed stuff bits are never included in -- According to CAN FD specification fixed stuff bits are never included in
-- CRC calculation. With NON ISO there is no problem. CRC calculation in the -- CRC calculation. With NON ISO there is no problem. CRC calculation in the
...@@ -1042,16 +1063,6 @@ begin ...@@ -1042,16 +1063,6 @@ begin
else else
bds_trig_del_1; bds_trig_del_1;
bds_del_proc : process(clk_sys, res_n)
begin
if (res_n = ACT_RESET) then
bds_trig_del_1 <= '0';
elsif rising_edge(clk_sys) then
bds_trig_del_1 <= bds_trig;
end if;
end process;
crc_nbs_trig <= (sync_dbt and (not data_halt)) crc_nbs_trig <= (sync_dbt and (not data_halt))
when (sp_control_int = SECONDARY_SAMPLE) when (sp_control_int = SECONDARY_SAMPLE)
...@@ -1067,8 +1078,19 @@ begin ...@@ -1067,8 +1078,19 @@ begin
error_passive_changed <= error_passive_changed_int; error_passive_changed <= error_passive_changed_int;
error_warning_limit <= error_warning_limit_int; error_warning_limit <= error_warning_limit_int;
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Internal loopback multiplexing -- Data Received by Protocol control are from Bit Destuffing, apart from
-- following cases:
-- 1. Internal loopback is set by Protocol control (due to some special
-- mode such as LOM), or rerouting acknowledge internally in case of
-- STM mode.
-- 2. Internal loopback is permanently turned on from SW for debugging!
-- 3. Secondary sampling point is set. This is ONLY in Data phase of
-- CAN FD Transmitter after Bit rate shift! This is needed for proper
-- reception of own data in the same bit! Note that Bit error in this
-- case is detected by Bus Sync circuit which has shift registers for
-- secondary sampling point!
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
data_rx_int <= data_tx_from_PC when (int_loop_back_ena = '1' or data_rx_int <= data_tx_from_PC when (int_loop_back_ena = '1' or
drv_int_loopback_ena = '1' or drv_int_loopback_ena = '1' or
...@@ -1077,14 +1099,18 @@ begin ...@@ -1077,14 +1099,18 @@ begin
data_rx; data_rx;
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
--Note: int_loop_back_ena is for bus monitoring mode. drv_int_loopback_ena -- Data transmitted by Protocol control are sent out of CAN Core to
-- is for internal loopback set by user! -- Bit stuffing, apart from following cases:
-- 1. Protocol Control has "int_loop_back_ena" which forbids bit to be
-- transmitted further!
-- 2. User has set (for debugging purposes) permanent Internal Loopback!
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
data_tx_before_stuff <= RECESSIVE when (int_loop_back_ena = '1' or data_tx_before_stuff <= RECESSIVE when (int_loop_back_ena = '1' or
drv_int_loopback_ena = '1') drv_int_loopback_ena = '1')
else else
data_tx_from_PC; data_tx_from_PC;
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Bus traffic measurement -- Bus traffic measurement
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
...@@ -1099,19 +1125,25 @@ begin ...@@ -1099,19 +1125,25 @@ begin
if (drv_set_rx_ctr = '1') then if (drv_set_rx_ctr = '1') then
rx_counter <= drv_set_ctr_val; rx_counter <= drv_set_ctr_val;
elsif(rec_valid='1')then elsif (rec_valid = '1') then
rx_counter <= std_logic_vector(unsigned(rx_counter) + 1); rx_counter <= std_logic_vector(to_unsigned(
to_integer(unsigned(rx_counter)) + 1,
rx_counter'length));
end if; end if;
if (drv_set_tx_ctr = '1') then if (drv_set_tx_ctr = '1') then
tx_counter <= drv_set_ctr_val; tx_counter <= drv_set_ctr_val;
elsif (tran_valid = '1') then elsif (tran_valid = '1') then
tx_counter <= std_logic_vector(unsigned(tx_counter) + 1); tx_counter <= std_logic_vector(to_unsigned(
to_integer(unsigned(tx_counter)) + 1,
tx_counter'length));
end if; end if;
end if; end if;
end process; end process;
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- STATUS Bus Implementation -- STATUS Bus Implementation
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
......
...@@ -216,18 +216,24 @@ ...@@ -216,18 +216,24 @@
-- 10.7.2018 Changed length of data length field for DLC > 8 in case of -- 10.7.2018 Changed length of data length field for DLC > 8 in case of
-- CAN 2.0 frame! For CAN 2.0 frame DLC higher than 8 should be -- CAN 2.0 frame! For CAN 2.0 frame DLC higher than 8 should be
-- interpreted as 8! -- interpreted as 8!
-- 13.7.2018 Removed "unknown_state_Error_r" since it was unused. Unified -- 13.7.2018 1. Removed "unknown_state_Error_r" since it was unused. Unified
-- all "when others" statements to go to "error" state an cause -- all "when others" statements to go to "error" state an cause
-- error frame transmission! This is however synthesis tool -- error frame transmission! This is however synthesis tool
-- dependent! If FSM synthesis on invalid state (e.g. glitch) -- dependent! If FSM synthesis on invalid state (e.g. glitch)
-- would jump to reset state, then node would become off, and -- would jump to reset state, then node would become off, and
-- communication would not continue! If synthesis tool would -- communication would not continue! If synthesis tool would
-- use "others" to detect invalid FSM state, and go to "error" -- use "others" to detect invalid FSM state, and go to "error"
-- state, then this would be "safety" feature for possible -- state, then this would be "safety" feature for possible
-- glitches. From CAN Node perspective, this would be another -- glitches. From CAN Node perspective, this would be another
-- "internal" error, which would cause transmission of error -- "internal" error, which would cause transmission of error
-- frame! Such a behaviour is not defined by standard, but it -- frame! Such a behaviour is not defined by standard, but it
-- is logical to do it like so! -- is logical to do it like so!
-- 2. Removed "bit_err_ena" since it was unused! Selection of
-- valid bit error is done by Fault confinement!
-- 13.8.2018 fixed_CRC_FD removed since fixed stuff bit before CRC field
-- is inserted by Bit Stuffing and discarded by Bit Destuffing
-- automatically upon detection of 0 -> 1 transition on
-- "fixed_stuff" / "fixed_destuff" signals.
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Library ieee; Library ieee;
...@@ -418,11 +424,6 @@ entity protocolControl is ...@@ -418,11 +424,6 @@ entity protocolControl is
--Calibration command for transciever delay compenstation (counter) --Calibration command for transciever delay compenstation (counter)
signal trv_delay_calib :out std_logic; signal trv_delay_calib :out std_logic;
--Bit Error detection enable (Ex. disabled when recieving data)
signal bit_err_enable :out std_logic;
--Note: In the end bit Error detection is always enabled, Fault confinement
-- module decides whenever the bit Error is VALID!!!
--Synchronisation edge validated by prescaler!!! --Synchronisation edge validated by prescaler!!!
signal hard_sync_edge :in std_logic; signal hard_sync_edge :in std_logic;
...@@ -514,7 +515,6 @@ entity protocolControl is ...@@ -514,7 +515,6 @@ entity protocolControl is
signal trv_delay_calib_r : std_logic; signal trv_delay_calib_r : std_logic;
--Bit Error detection enable (Ex. disabled when recieving data) --Bit Error detection enable (Ex. disabled when recieving data)
signal bit_err_enable_r : std_logic;
signal sync_control_r : std_logic_vector(1 downto 0); signal sync_control_r : std_logic_vector(1 downto 0);
signal alc_r : std_logic_vector(7 downto 0); signal alc_r : std_logic_vector(7 downto 0);